Fix input vector for reduce cells. Infinite loop fixed.

diff --git a/passes/opt/opt_reduce.cc b/passes/opt/opt_reduce.cc
index eb9d02ad538bd8803391c5509ecd57c219237d6b..8126f3c0dcc90fe1f97276624bfbb48747d1d3e3 100644 (file)
--- a/passes/opt/opt_reduce.cc
+++ b/passes/opt/opt_reduce.cc
@@ -44,6 +44,7 @@ struct OptReduceWorker
                cells.erase(cell);
 
                RTLIL::SigSpec sig_a = assign_map(cell->getPort("\\A"));
+               sig_a.sort_and_unify();
                pool<RTLIL::SigBit> new_sig_a_bits;
 
                for (auto &bit : sig_a.to_sigbit_set())
@@ -86,6 +87,7 @@ struct OptReduceWorker
                }
 
                RTLIL::SigSpec new_sig_a(new_sig_a_bits);
+               new_sig_a.sort_and_unify();
 
                if (new_sig_a != sig_a || sig_a.size() != cell->getPort("\\A").size()) {
                        log("    New input vector for %s cell %s: %s\n", cell->type.c_str(), cell->name.c_str(), log_signal(new_sig_a));