radeon/vce: increase cpb height alignment

Height should be aligned with 2 macroblocks, thus making safer
for tiled mode

Signed-off-by: Leo Liu <leo.liu@amd.com>
Reviewed-by: Christian König <christian.koenig@amd.com>

diff --git a/src/gallium/drivers/radeon/radeon_vce.c b/src/gallium/drivers/radeon/radeon_vce.c
index e8aac8ec0e4a8dbe20a53eb274df79632b81576d..92cb8ce101fed2e4bed7213e4926e1cb3f003a7c 100644 (file)
--- a/src/gallium/drivers/radeon/radeon_vce.c
+++ b/src/gallium/drivers/radeon/radeon_vce.c
@@ -454,7 +454,7 @@ struct pipe_video_codec *rvce_create_encoder(struct pipe_context *context,
 
        get_buffer(((struct vl_video_buffer *)tmp_buf)->resources[0], NULL, &tmp_surf);
        cpb_size = align(tmp_surf->level[0].pitch_bytes, 128);
-       cpb_size = cpb_size * align(tmp_surf->npix_y, 16);
+       cpb_size = cpb_size * align(tmp_surf->npix_y, 32);
        cpb_size = cpb_size * 3 / 2;
        cpb_size = cpb_size * enc->cpb_num;
        if (enc->dual_pipe)