Revert "vendor.xilinx_7series: byte swap generated bitstream"
authorwhitequark <whitequark@whitequark.org>
Sat, 12 Dec 2020 22:08:57 +0000 (22:08 +0000)
committerLuke Kenneth Casson Leighton <lkcl@lkcl.net>
Fri, 31 Dec 2021 15:24:46 +0000 (15:24 +0000)
This reverts commit 14a5c42a8bd425a4882ba566b26e11bd6d1e1721.

nmigen/vendor/xilinx_7series.py

index 084d2ba521809139d143c8867a8bcde44197facd..e53a7a44b6c40293a96836bd407b9c37c990dc24 100644 (file)
@@ -143,8 +143,7 @@ class Xilinx7SeriesPlatform(TemplatedPlatform):
             report_timing_summary -datasheet -max_paths 10 -file {{name}}_timing.rpt
             report_power -file {{name}}_power.rpt
             {{get_override("script_before_bitstream")|default("# (script_before_bitstream placeholder)")}}
-            write_bitstream -force {{name}}.bit
-            write_cfgmem -force -format bin -interface smapx32 -disablebitswap -loadbit "up 0 {{name}}.bit" {{name}}.bin
+            write_bitstream -force -bin_file {{name}}.bit
             {{get_override("script_after_bitstream")|default("# (script_after_bitstream placeholder)")}}
             quit
         """,