i915: On Gen <= 3 there is no multisampling

Signed-off-by: Ian Romanick <ian.d.romanick@intel.com>
Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com>

diff --git a/src/mesa/drivers/dri/i915/intel_mipmap_tree.c b/src/mesa/drivers/dri/i915/intel_mipmap_tree.c
index 860d053de2c8f2006dc08f8af59cdd41ad11a9bc..92f116b9e055ce5d2dce2136c4103cfa3e0eb225 100644 (file)
--- a/src/mesa/drivers/dri/i915/intel_mipmap_tree.c
+++ b/src/mesa/drivers/dri/i915/intel_mipmap_tree.c
@@ -276,11 +276,7 @@ intel_miptree_create_for_bo(struct intel_context *intel,
 
 
 /**
- * For a singlesample DRI2 buffer, this simply wraps the given region with a miptree.
- *
- * For a multisample DRI2 buffer, this wraps the given region with
- * a singlesample miptree, then creates a multisample miptree into which the
- * singlesample miptree is embedded as a child.
+ * Wraps the given region with a miptree.
  */
 struct intel_mipmap_tree *
 intel_miptree_create_for_dri2_buffer(struct intel_context *intel,
@@ -315,11 +311,7 @@ intel_miptree_create_for_dri2_buffer(struct intel_context *intel,
 }
 
 /**
- * For a singlesample image buffer, this simply wraps the given region with a miptree.
- *
- * For a multisample image buffer, this wraps the given region with
- * a singlesample miptree, then creates a multisample miptree into which the
- * singlesample miptree is embedded as a child.
+ * Wraps the given region with a miptree.
  */
 struct intel_mipmap_tree *
 intel_miptree_create_for_image_buffer(struct intel_context *intel,
@@ -453,24 +445,10 @@ intel_miptree_match_image(struct intel_mipmap_tree *mt,
     * minification.  This will also catch images not present in the
     * tree, changed targets, etc.
     */
-   if (mt->target == GL_TEXTURE_2D_MULTISAMPLE ||
-       mt->target == GL_TEXTURE_2D_MULTISAMPLE_ARRAY) {
-      /* nonzero level here is always bogus */
-      assert(level == 0);
-
-      if (width != mt->logical_width0 ||
-            height != mt->logical_height0 ||
-            depth != mt->logical_depth0) {
-         return false;
-      }
-   }
-   else {
-      /* all normal textures, renderbuffers, etc */
-      if (width != mt->level[level].width ||
-          height != mt->level[level].height ||
-          depth != mt->level[level].depth) {
-         return false;
-      }
+   if (width != mt->level[level].width ||
+       height != mt->level[level].height ||
+       depth != mt->level[level].depth) {
+      return false;
    }
 
    return true;

diff --git a/src/mesa/drivers/dri/i915/intel_mipmap_tree.h b/src/mesa/drivers/dri/i915/intel_mipmap_tree.h
index 853a4a7986de38404de8c50a0db47e8a1ba86d7e..929493118f6b206355a53da25da5ab81b513199c 100644 (file)
--- a/src/mesa/drivers/dri/i915/intel_mipmap_tree.h
+++ b/src/mesa/drivers/dri/i915/intel_mipmap_tree.h
@@ -160,10 +160,8 @@ struct intel_mipmap_tree
    /**
     * Level zero image dimensions.  These dimensions correspond to the
     * physical layout of data in memory.  Accordingly, they account for the
-    * extra width, height, and or depth that must be allocated in order to
-    * accommodate multisample formats, and they account for the extra factor
-    * of 6 in depth that must be allocated in order to accommodate cubemap
-    * textures.
+    * extra factor of 6 in depth that must be allocated in order to
+    * accommodate cubemap textures.
     */
    GLuint physical_width0, physical_height0, physical_depth0;
 
@@ -173,9 +171,7 @@ struct intel_mipmap_tree
    /**
     * Level zero image dimensions.  These dimensions correspond to the
     * logical width, height, and depth of the region as seen by client code.
-    * Accordingly, they do not account for the extra width, height, and/or
-    * depth that must be allocated in order to accommodate multisample
-    * formats, nor do they account for the extra factor of 6 in depth that
+    * Accordingly, they do not account for the extra factor of 6 in depth that
     * must be allocated in order to accommodate cubemap textures.
     */
    uint32_t logical_width0, logical_height0, logical_depth0;

diff --git a/src/mesa/drivers/dri/i915/intel_tex_layout.c b/src/mesa/drivers/dri/i915/intel_tex_layout.c
index 01ea165c7562974acfa6efd60392ddf929a3ac9b..efe7a8db9fca6acf3381d7b10d73acb91dd6ba99 100644 (file)
--- a/src/mesa/drivers/dri/i915/intel_tex_layout.c
+++ b/src/mesa/drivers/dri/i915/intel_tex_layout.c
@@ -97,14 +97,11 @@ intel_vertical_texture_alignment_unit(struct intel_context *intel,
     * | FXT1  compressed format                |  4  |  4  |  4  |  4  |  4  |
     * | Depth Buffer                           |  2  |  2  |  2  |  4  |  4  |
     * | Separate Stencil Buffer                | N/A | N/A | N/A |  4  |  8  |
-    * | Multisampled (4x or 8x) render target  | N/A | N/A | N/A |  4  |  4  |
     * | All Others                             |  2  |  2  |  2  |  2  |  2  |
     * +----------------------------------------------------------------------+
     *
     * On SNB+, non-special cases can be overridden by setting the SURFACE_STATE
     * "Surface Vertical Alignment" field to VALIGN_2 or VALIGN_4.
-    *
-    * We currently don't support multisampling.
     */
    if (_mesa_is_format_compressed(format))
       return 4;