uart: Remove combinational loops on ack and stall signal

They hurt timing forcing signals to come from the master and back
again in one cycle. Stall isn't sampled by the master unless there
is an active cycle so masking it with cyc is pointless. Masking acks
is somewhat pointless too as we don't handle early dropping of cyc
in any of our slaves properly anyways.

Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>

diff --git a/fpga/pp_soc_uart.vhd b/fpga/pp_soc_uart.vhd
index 8c4c93c3f5f0565c70072ce2a42bec2ae658eea3..1ed3bb918522d03d7b85d043c54b4a098fd3e9d1 100644 (file)
--- a/fpga/pp_soc_uart.vhd
+++ b/fpga/pp_soc_uart.vhd
@@ -107,8 +107,6 @@ architecture behaviour of pp_soc_uart is
     type wb_state_type is (IDLE, WRITE_ACK, READ_ACK);
     signal wb_state : wb_state_type;
 
-    signal wb_ack : std_logic; --! Wishbone acknowledge signal
-
     signal rxd2 : std_logic := '1';
     signal rxd3 : std_logic := '1';
     signal txd2 : std_ulogic := '1';
@@ -319,13 +317,11 @@ begin
 
     ---------- Wishbone Interface ---------- 
 
-    wb_ack_out <= wb_ack and wb_cyc_in and wb_stb_in;
-
     wishbone: process(clk)
     begin
        if rising_edge(clk) then
            if reset = '1' then
-               wb_ack <= '0';
+               wb_ack_out <= '0';
                wb_state <= IDLE;
                send_buffer_push <= '0';
                recv_buffer_pop <= '0';
@@ -348,7 +344,7 @@ begin
                            end if;
 
                            -- Invalid writes are acked and ignored.
-                           wb_ack <= '1';
+                           wb_ack_out <= '1';
                            wb_state <= WRITE_ACK;
                        else -- Read from register
                            if wb_adr_in = x"008" then
@@ -356,18 +352,18 @@ begin
                            elsif wb_adr_in = x"010" then
                                wb_dat_out <= x"0" & send_buffer_full & recv_buffer_full &
                                              send_buffer_empty & recv_buffer_empty;
-                               wb_ack <= '1';
+                               wb_ack_out <= '1';
                            elsif wb_adr_in = x"018" then
                                wb_dat_out <= sample_clk_divisor;
-                               wb_ack <= '1';
+                               wb_ack_out <= '1';
                            elsif wb_adr_in = x"020" then
                                wb_dat_out <= (0 => irq_recv_enable,
                                               1 => irq_tx_ready_enable,
                                               others => '0');
-                               wb_ack <= '1';
+                               wb_ack_out <= '1';
                            else
                                wb_dat_out <= (others => '0');
-                               wb_ack <= '1';
+                               wb_ack_out <= '1';
                            end if;
                            wb_state <= READ_ACK;
                        end if;
@@ -376,7 +372,7 @@ begin
                    send_buffer_push <= '0';
 
                    if wb_stb_in = '0' then
-                       wb_ack <= '0';
+                       wb_ack_out <= '0';
                        wb_state <= IDLE;
                    end if;
                when READ_ACK =>
@@ -384,11 +380,11 @@ begin
                        recv_buffer_pop <= '0';
                    else
                        wb_dat_out <= recv_buffer_output;
-                       wb_ack <= '1';
+                       wb_ack_out <= '1';
                    end if;
 
                    if wb_stb_in = '0' then
-                       wb_ack <= '0';
+                       wb_ack_out <= '0';
                        wb_state <= IDLE;
                    end if;
                end case;

diff --git a/soc.vhdl b/soc.vhdl
index 047be9623976c82729592c1baf633fe66f6cff8d..23d388528c1e6b5932dfd93f5ec7e971ac8a2e33 100644 (file)
--- a/soc.vhdl
+++ b/soc.vhdl
@@ -548,7 +548,7 @@ begin
            wb_ack_out => wb_uart0_out.ack
            );
     wb_uart0_out.dat <= x"000000" & uart_dat8;
-    wb_uart0_out.stall <= '0' when wb_uart0_in.cyc = '0' else not wb_uart0_out.ack;
+    wb_uart0_out.stall <= not wb_uart0_out.ack;
 
     spiflash_gen: if HAS_SPI_FLASH generate        
         spiflash: entity work.spi_flash_ctrl