Cleanups and bugfixes in response to new internal cell checker

diff --git a/frontends/ast/genrtlil.cc b/frontends/ast/genrtlil.cc
index 25781ae237a17134247a255cf3759f52e02e6da8..e64193f6e2eee1a695ff27cda1aaaa234d1b0f96 100644 (file)
--- a/frontends/ast/genrtlil.cc
+++ b/frontends/ast/genrtlil.cc
@@ -1199,7 +1199,7 @@ RTLIL::SigSpec AstNode::genRTLIL(int width_hint, bool sign_hint)
                                addr_bits++;
 
                        cell->connections["\\CLK"] = RTLIL::SigSpec(RTLIL::State::Sx, 1);
-                       cell->connections["\\ADDR"] = children[0]->genRTLIL();
+                       cell->connections["\\ADDR"] = children[0]->genWidthRTLIL(addr_bits);
                        cell->connections["\\DATA"] = RTLIL::SigSpec(wire);
 
                        cell->parameters["\\MEMID"] = RTLIL::Const(str);
@@ -1229,10 +1229,13 @@ RTLIL::SigSpec AstNode::genRTLIL(int width_hint, bool sign_hint)
                                addr_bits++;
 
                        cell->connections["\\CLK"] = RTLIL::SigSpec(RTLIL::State::Sx, 1);
-                       cell->connections["\\ADDR"] = children[0]->genRTLIL();
-                       cell->connections["\\DATA"] = children[1]->genRTLIL();
+                       cell->connections["\\ADDR"] = children[0]->genWidthRTLIL(addr_bits);
+                       cell->connections["\\DATA"] = children[1]->genWidthRTLIL(current_module->memories[str]->width);
                        cell->connections["\\EN"] = children[2]->genRTLIL();
 
+                       if (cell->connections["\\EN"].width > 1)
+                               cell->connections["\\EN"] = uniop2rtlil(this, "$reduce_bool", 1, cell->connections["\\EN"], false);
+
                        cell->parameters["\\MEMID"] = RTLIL::Const(str);
                        cell->parameters["\\ABITS"] = RTLIL::Const(addr_bits);
                        cell->parameters["\\WIDTH"] = RTLIL::Const(current_module->memories[str]->width);

diff --git a/passes/opt/opt_muxtree.cc b/passes/opt/opt_muxtree.cc
index 49b72f15bcd8a1cf996ab6e5428dbbbe43aeec67..47100869c27dfdb0b080b4720d259e1118d8b7d5 100644 (file)
--- a/passes/opt/opt_muxtree.cc
+++ b/passes/opt/opt_muxtree.cc
@@ -225,9 +225,9 @@ struct OptMuxtreeWorker
                                mi.cell->connections["\\S"] = new_sig_s;
                                if (new_sig_s.width == 1) {
                                        mi.cell->type = "$mux";
-                                       mi.cell->attributes.erase("\\S_WIDTH");
+                                       mi.cell->parameters.erase("\\S_WIDTH");
                                } else {
-                                       mi.cell->attributes["\\S_WIDTH"] = RTLIL::Const(new_sig_s.width);
+                                       mi.cell->parameters["\\S_WIDTH"] = RTLIL::Const(new_sig_s.width);
                                }
                        }
                }

diff --git a/passes/opt/opt_reduce.cc b/passes/opt/opt_reduce.cc
index 98351762eccd114bd8432300816c0598319c8145..dd1299810f9314cd34efd7c77393d628d8e24452 100644 (file)
--- a/passes/opt/opt_reduce.cc
+++ b/passes/opt/opt_reduce.cc
@@ -127,6 +127,7 @@ struct OptReduceWorker
                                reduce_or_cell->name = NEW_ID;
                                reduce_or_cell->type = "$reduce_or";
                                reduce_or_cell->connections["\\A"] = this_s;
+                               reduce_or_cell->parameters["\\A_SIGNED"] = RTLIL::Const(0);
                                reduce_or_cell->parameters["\\A_WIDTH"] = RTLIL::Const(this_s.width);
                                reduce_or_cell->parameters["\\Y_WIDTH"] = RTLIL::Const(1);
                                module->cells[reduce_or_cell->name] = reduce_or_cell;

diff --git a/techlibs/common/simlib.v b/techlibs/common/simlib.v
index 7c075b8322853066df931d26dfec49e75d959379..beb2b885705bc5fd5b8a0dc4e3b29e0dca2b69a7 100644 (file)
--- a/techlibs/common/simlib.v
+++ b/techlibs/common/simlib.v
@@ -929,6 +929,7 @@ module \$mem (RD_CLK, RD_ADDR, RD_DATA, WR_CLK, WR_EN, WR_ADDR, WR_DATA);
 
 parameter MEMID = "";
 parameter SIZE = 256;
+parameter OFFSET = 0;
 parameter ABITS = 8;
 parameter WIDTH = 8;
 
@@ -957,14 +958,14 @@ generate
        for (i = 0; i < RD_PORTS; i = i+1) begin:rd
                if (RD_CLK_ENABLE[i] == 0) begin:rd_noclk
                        always @(RD_ADDR or update_async_rd)
-                               RD_DATA[ (i+1)*WIDTH-1 : i*WIDTH ] <= data[ RD_ADDR[ (i+1)*ABITS-1 : i*ABITS ] ];
+                               RD_DATA[ (i+1)*WIDTH-1 : i*WIDTH ] <= data[ RD_ADDR[ (i+1)*ABITS-1 : i*ABITS ] - OFFSET ];
                end else
                if (RD_CLK_POLARITY[i] == 1) begin:rd_posclk
                        always @(posedge RD_CLK[i])
-                               RD_DATA[ (i+1)*WIDTH-1 : i*WIDTH ] <= data[ RD_ADDR[ (i+1)*ABITS-1 : i*ABITS ] ];
+                               RD_DATA[ (i+1)*WIDTH-1 : i*WIDTH ] <= data[ RD_ADDR[ (i+1)*ABITS-1 : i*ABITS ] - OFFSET ];
                end else begin:rd_negclk
                        always @(negedge RD_CLK[i])
-                               RD_DATA[ (i+1)*WIDTH-1 : i*WIDTH ] <= data[ RD_ADDR[ (i+1)*ABITS-1 : i*ABITS ] ];
+                               RD_DATA[ (i+1)*WIDTH-1 : i*WIDTH ] <= data[ RD_ADDR[ (i+1)*ABITS-1 : i*ABITS ] - OFFSET ];
                end
        end
 
@@ -972,7 +973,7 @@ generate
                if (WR_CLK_ENABLE[i] == 0) begin:wr_noclk
                        always @(WR_ADDR or WR_DATA or WR_EN) begin
                                if (WR_EN[i]) begin
-                                       data[ WR_ADDR[ (i+1)*ABITS-1 : i*ABITS ] ] <= WR_DATA[ (i+1)*WIDTH-1 : i*WIDTH ];
+                                       data[ WR_ADDR[ (i+1)*ABITS-1 : i*ABITS ] - OFFSET ] <= WR_DATA[ (i+1)*WIDTH-1 : i*WIDTH ];
                                        #1 -> update_async_rd;
                                end
                        end
@@ -980,13 +981,13 @@ generate
                if (RD_CLK_POLARITY[i] == 1) begin:rd_posclk
                        always @(posedge WR_CLK[i])
                                if (WR_EN[i]) begin
-                                       data[ WR_ADDR[ (i+1)*ABITS-1 : i*ABITS ] ] <= WR_DATA[ (i+1)*WIDTH-1 : i*WIDTH ];
+                                       data[ WR_ADDR[ (i+1)*ABITS-1 : i*ABITS ] - OFFSET ] <= WR_DATA[ (i+1)*WIDTH-1 : i*WIDTH ];
                                        #1 -> update_async_rd;
                                end
                end else begin:rd_negclk
                        always @(negedge WR_CLK[i])
                                if (WR_EN[i]) begin
-                                       data[ WR_ADDR[ (i+1)*ABITS-1 : i*ABITS ] ] <= WR_DATA[ (i+1)*WIDTH-1 : i*WIDTH ];
+                                       data[ WR_ADDR[ (i+1)*ABITS-1 : i*ABITS ] - OFFSET ] <= WR_DATA[ (i+1)*WIDTH-1 : i*WIDTH ];
                                        #1 -> update_async_rd;
                                end
                end

diff --git a/techlibs/common/stdcells.v b/techlibs/common/stdcells.v
index e37ad20d5a5cf59a9c841537abd14e86fcd7d088..83384ce6ca5d78f0911ee4d9f6edf95cff2913ae 100644 (file)
--- a/techlibs/common/stdcells.v
+++ b/techlibs/common/stdcells.v
@@ -100,7 +100,7 @@ output [Y_WIDTH-1:0] Y;
        .B_WIDTH(A_WIDTH),
        .Y_WIDTH(Y_WIDTH)
 ) sub (
-       .A(0),
+       .A(1'b0),
        .B(A),
        .Y(Y)
 );
@@ -393,7 +393,7 @@ endmodule
 
 // --------------------------------------------------------
 
-module \$shift (X, A, Y);
+module \$__shift (X, A, Y);
 
 parameter WIDTH = 1;
 parameter SHIFT = 0;
@@ -450,7 +450,7 @@ generate
                wire [WIDTH-1:0] unshifted, shifted, result;
                assign unshifted = chain[WIDTH*i + WIDTH-1 : WIDTH*i];
                assign chain[WIDTH*(i+1) + WIDTH-1 : WIDTH*(i+1)] = result;
-               \$shift #(
+               \$__shift #(
                        .WIDTH(WIDTH),
                        .SHIFT(0 - (2 ** (i > 30 ? 30 : i)))
                ) sh (
@@ -503,7 +503,7 @@ generate
                wire [WIDTH-1:0] unshifted, shifted, result;
                assign unshifted = chain[WIDTH*i + WIDTH-1 : WIDTH*i];
                assign chain[WIDTH*(i+1) + WIDTH-1 : WIDTH*(i+1)] = result;
-               \$shift #(
+               \$__shift #(
                        .WIDTH(WIDTH),
                        .SHIFT(2 ** (i > 30 ? 30 : i))
                ) sh (
@@ -556,7 +556,7 @@ generate
                wire [WIDTH-1:0] unshifted, shifted, result;
                assign unshifted = chain[WIDTH*i + WIDTH-1 : WIDTH*i];
                assign chain[WIDTH*(i+1) + WIDTH-1 : WIDTH*(i+1)] = result;
-               \$shift #(
+               \$__shift #(
                        .WIDTH(WIDTH),
                        .SHIFT(0 - (2 ** (i > 30 ? 30 : i)))
                ) sh (
@@ -618,7 +618,7 @@ generate
                wire [WIDTH-1:0] unshifted, shifted, result;
                assign unshifted = chain[WIDTH*i + WIDTH-1 : WIDTH*i];
                assign chain[WIDTH*(i+1) + WIDTH-1 : WIDTH*(i+1)] = result;
-               \$shift #(
+               \$__shift #(
                        .WIDTH(WIDTH),
                        .SHIFT(2 ** (i > 30 ? 30 : i))
                ) sh (
@@ -641,7 +641,7 @@ endmodule
 
 // --------------------------------------------------------
 
-module \$fulladd (A, B, C, X, Y);
+module \$__fulladd (A, B, C, X, Y);
 
 // {X, Y} = A + B + C
 input A, B, C;
@@ -661,7 +661,7 @@ endmodule
 
 // --------------------------------------------------------
 
-module \$alu (A, B, Cin, Y, Cout, Csign);
+module \$__alu (A, B, Cin, Y, Cout, Csign);
 
 parameter WIDTH = 1;
 
@@ -679,7 +679,7 @@ assign Csign = carry[WIDTH-1];
 genvar i;
 generate
        for (i = 0; i < WIDTH; i = i + 1) begin:V
-               \$fulladd adder (
+               \$__fulladd adder (
                        .A(A[i]),
                        .B(B[i]),
                        .C(carry[i]),
@@ -712,7 +712,7 @@ wire [WIDTH-1:0] A_buf, B_buf, Y_buf;
 \$pos #(.A_SIGNED(A_SIGNED && B_SIGNED), .A_WIDTH(A_WIDTH), .Y_WIDTH(WIDTH)) A_conv (.A(A), .Y(A_buf));
 \$pos #(.A_SIGNED(A_SIGNED && B_SIGNED), .A_WIDTH(B_WIDTH), .Y_WIDTH(WIDTH)) B_conv (.A(B), .Y(B_buf));
 
-\$alu #(
+\$__alu #(
        .WIDTH(WIDTH)
 ) alu (
        .A(A_buf),
@@ -761,7 +761,7 @@ wire [WIDTH-1:0] A_buf, B_buf, Y_buf;
 \$pos #(.A_SIGNED(A_SIGNED && B_SIGNED), .A_WIDTH(A_WIDTH), .Y_WIDTH(WIDTH)) A_conv (.A(A), .Y(A_buf));
 \$pos #(.A_SIGNED(A_SIGNED && B_SIGNED), .A_WIDTH(B_WIDTH), .Y_WIDTH(WIDTH)) B_conv (.A(B), .Y(B_buf));
 
-\$alu #(
+\$__alu #(
        .WIDTH(WIDTH)
 ) alu (
        .A(A_buf),
@@ -857,19 +857,14 @@ output [Y_WIDTH-1:0] Y;
        .A_SIGNED(B_SIGNED),
        .B_SIGNED(A_SIGNED),
        .A_WIDTH(B_WIDTH),
-       .B_WIDTH(A_WIDTH)
+       .B_WIDTH(A_WIDTH),
+       .Y_WIDTH(Y_WIDTH)
 ) ge_via_le (
        .A(B),
        .B(A),
-       .Y(Y[0])
+       .Y(Y)
 );
 
-generate
-       if (Y_WIDTH > 1) begin:V
-               assign Y[Y_WIDTH-1:1] = 0;
-       end
-endgenerate
-
 endmodule
 
 // --------------------------------------------------------
@@ -890,19 +885,14 @@ output [Y_WIDTH-1:0] Y;
        .A_SIGNED(B_SIGNED),
        .B_SIGNED(A_SIGNED),
        .A_WIDTH(B_WIDTH),
-       .B_WIDTH(A_WIDTH)
+       .B_WIDTH(A_WIDTH),
+       .Y_WIDTH(Y_WIDTH)
 ) gt_via_lt (
        .A(B),
        .B(A),
-       .Y(Y[0])
+       .Y(Y)
 );
 
-generate
-       if (Y_WIDTH > 1) begin:V
-               assign Y[Y_WIDTH-1:1] = 0;
-       end
-endgenerate
-
 endmodule
 
 // --------------------------------------------------------
@@ -923,7 +913,7 @@ wire [Y_WIDTH-1:0] A_buf, B_buf;
 \$pos #(.A_SIGNED(A_SIGNED && B_SIGNED), .A_WIDTH(A_WIDTH), .Y_WIDTH(Y_WIDTH)) A_conv (.A(A), .Y(A_buf));
 \$pos #(.A_SIGNED(A_SIGNED && B_SIGNED), .A_WIDTH(B_WIDTH), .Y_WIDTH(Y_WIDTH)) B_conv (.A(B), .Y(B_buf));
 
-\$alu #(
+\$__alu #(
        .WIDTH(Y_WIDTH)
 ) alu (
        .A(A_buf),
@@ -952,7 +942,7 @@ wire [Y_WIDTH-1:0] A_buf, B_buf;
 \$pos #(.A_SIGNED(A_SIGNED && B_SIGNED), .A_WIDTH(A_WIDTH), .Y_WIDTH(Y_WIDTH)) A_conv (.A(A), .Y(A_buf));
 \$pos #(.A_SIGNED(A_SIGNED && B_SIGNED), .A_WIDTH(B_WIDTH), .Y_WIDTH(Y_WIDTH)) B_conv (.A(B), .Y(B_buf));
 
-\$alu #(
+\$__alu #(
        .WIDTH(Y_WIDTH)
 ) alu (
        .A(A_buf),
@@ -965,7 +955,7 @@ endmodule
 
 // --------------------------------------------------------
 
-module \$arraymul (A, B, Y);
+module \$__arraymul (A, B, Y);
 
 parameter WIDTH = 8;
 input [WIDTH-1:0] A, B;
@@ -1001,7 +991,7 @@ wire [Y_WIDTH-1:0] A_buf, B_buf;
 \$pos #(.A_SIGNED(A_SIGNED && B_SIGNED), .A_WIDTH(A_WIDTH), .Y_WIDTH(Y_WIDTH)) A_conv (.A(A), .Y(A_buf));
 \$pos #(.A_SIGNED(A_SIGNED && B_SIGNED), .A_WIDTH(B_WIDTH), .Y_WIDTH(Y_WIDTH)) B_conv (.A(B), .Y(B_buf));
 
-\$arraymul #(
+\$__arraymul #(
        .WIDTH(Y_WIDTH)
 ) arraymul (
        .A(A_buf),
@@ -1013,7 +1003,7 @@ endmodule
 
 // --------------------------------------------------------
 
-module \$div_mod_u (A, B, Y, R);
+module \$__div_mod_u (A, B, Y, R);
 
 parameter WIDTH = 1;
 
@@ -1043,7 +1033,7 @@ endmodule
 
 // --------------------------------------------------------
 
-module \$div_mod (A, B, Y, R);
+module \$__div_mod (A, B, Y, R);
 
 parameter A_SIGNED = 0;
 parameter B_SIGNED = 0;
@@ -1067,7 +1057,7 @@ wire [WIDTH-1:0] A_buf_u, B_buf_u, Y_u, R_u;
 assign A_buf_u = A_SIGNED && B_SIGNED && A_buf[WIDTH-1] ? -A_buf : A_buf;
 assign B_buf_u = A_SIGNED && B_SIGNED && B_buf[WIDTH-1] ? -B_buf : B_buf;
 
-\$div_mod_u #(
+\$__div_mod_u #(
        .WIDTH(WIDTH)
 ) div_mod_u (
        .A(A_buf_u),
@@ -1098,7 +1088,7 @@ output [Y_WIDTH-1:0] Y;
 wire [Y_WIDTH-1:0] Y_buf;
 wire [Y_WIDTH-1:0] Y_div_zero;
 
-\$div_mod #(
+\$__div_mod #(
        .A_SIGNED(A_SIGNED),
        .B_SIGNED(B_SIGNED),
        .A_WIDTH(A_WIDTH),
@@ -1140,7 +1130,7 @@ output [Y_WIDTH-1:0] Y;
 wire [Y_WIDTH-1:0] Y_buf;
 wire [Y_WIDTH-1:0] Y_div_zero;
 
-\$div_mod #(
+\$__div_mod #(
        .A_SIGNED(A_SIGNED),
        .B_SIGNED(B_SIGNED),
        .A_WIDTH(A_WIDTH),
@@ -1204,7 +1194,8 @@ wire A_buf;
 
 \$reduce_bool #(
        .A_SIGNED(A_SIGNED),
-       .A_WIDTH(A_WIDTH)
+       .A_WIDTH(A_WIDTH),
+       .Y_WIDTH(1)
 ) A_logic (
        .A(A), 
        .Y(A_buf)
@@ -1241,7 +1232,8 @@ wire A_buf, B_buf;
 
 \$reduce_bool #(
        .A_SIGNED(A_SIGNED),
-       .A_WIDTH(A_WIDTH)
+       .A_WIDTH(A_WIDTH),
+       .Y_WIDTH(1)
 ) A_logic (
        .A(A), 
        .Y(A_buf)
@@ -1249,7 +1241,8 @@ wire A_buf, B_buf;
 
 \$reduce_bool #(
        .A_SIGNED(B_SIGNED),
-       .A_WIDTH(B_WIDTH)
+       .A_WIDTH(B_WIDTH),
+       .Y_WIDTH(1)
 ) B_logic (
        .A(B), 
        .Y(B_buf)
@@ -1287,7 +1280,8 @@ wire A_buf, B_buf;
 
 \$reduce_bool #(
        .A_SIGNED(A_SIGNED),
-       .A_WIDTH(A_WIDTH)
+       .A_WIDTH(A_WIDTH),
+       .Y_WIDTH(1)
 ) A_logic (
        .A(A), 
        .Y(A_buf)
@@ -1295,7 +1289,8 @@ wire A_buf, B_buf;
 
 \$reduce_bool #(
        .A_SIGNED(B_SIGNED),
-       .A_WIDTH(B_WIDTH)
+       .A_WIDTH(B_WIDTH),
+       .Y_WIDTH(1)
 ) B_logic (
        .A(B), 
        .Y(B_buf)