delete now-unnecessary section on experimental naming schemes

diff --git a/openpower/sv/int_fp_mv_reduced_insn_count.mdwn b/openpower/sv/int_fp_mv_reduced_insn_count.mdwn
index 628a0f863e04069bf906bccfdd085298bec72c10..6dc37dadf10757a253f721cf0b09bf65e7a8f359 100644 (file)
--- a/openpower/sv/int_fp_mv_reduced_insn_count.mdwn
+++ b/openpower/sv/int_fp_mv_reduced_insn_count.mdwn
@@ -2,51 +2,6 @@
 
 Note on considered alternative naming schemes: we decided to switch to using the reduced mnemonic naming scheme (over some people's objections) since it would be 5 instructions instead of dozens, though we did consider trying to match PowerISA's existing naming scheme for the instructions rather than only for the instruction aliases. <https://bugs.libre-soc.org/show_bug.cgi?id=1015#c7>
 
-# Reduced Instruction List Attempt
-
-Attempt at [reducing the number of different instructions](#reduced-instruction-list) used for int/fp moves.
-
-**IMPORTANT**: don't merge until everyone's had a chance to review it.
-
-## tables for reduced instruction list
-
-| S_AND_RC | PowerISA naming scheme |
-|----------|------------------------|
-| 0        | `fmvtg`                |
-| 1        | `fmvtg.`               |
-| 2        | `fmvtgs`               |
-| 3        | `fmvtgs.`              |
-
-| INT_MODE | PowerISA naming scheme | Integer Type    |
-|----------|------------------------|-----------------|
-| 0        | `fcvtfgw[s][.]`        | signed 32-bit   |
-| 1        | `fcvtfguw[s][.]`       | unsigned 32-bit |
-| 2        | `fcvtfgd[s][.]`        | signed 64-bit   |
-| 3        | `fcvtfgud[s][.]`       | unsigned 64-bit |
-
-## reduced instruction list <a name="reduced-instruction-list"></a>
-
-| old                                  | new                                        |
-|--------------------------------------|--------------------------------------------|
-| `fmvis FRS, D`                       | `fmvis FRS, D`                             |
-| `fishmv FRS, D`                      | `fishmv FRS, D`                            |
-| `fmvtg[s][.] RT, FRA`                | `fmvtg RT, FRA, S_AND_RC`                  |
-| `fmvfg[s][.] FRT, RA`                | `fmvfg FRT, RA, S_AND_RC`                  |
-| `fcvtfg[u][w/d][s][.] FRT, RA`       | `fcvtfg FRT, RA, S_AND_RC, INT_MODE`       |
-| `fcvt[s]tg[u][w/d][.] RT, FRA, Mode` | `fcvttg RT, FRA, Mode, S_AND_RC, INT_MODE` |
-
-Notes:
-
-* `fmvis` and `fishmv` have already been submitted to the ISA WG, so don't modify them!
-* PowerISA uses `s` and `.` suffixes instead of an immediate for Single and Rc=1 modes respectively.
-* PowerISA uses `w`, `uw`, `d`, and `ud` suffixes instead of an immediate for selecting between unsigned/signed 32-bit/64-bit.
-* Jacob: About the only operations I can see that we can realistically remove are Rc=1 versions, however imho that isn't necessary.
-* Realistically we can't remove any of the Rc=0 instructions because it would make the instruction set non-orthogonal and it would penalize the code using those operations, almost all of which are quite common.
-* Attempting to condense them into 6 instructions by undoing the PowerISA naming scheme works, but all that changed is the assembler mnemonics (in a bad way by being inconsistent with how PowerISA names things), the instruction encodings don't change at all, unless we want to use an expanded opcode.
-* Jacob: I think we will want to keep the Single versions of moves/conversions from FPRs to GPRs, since it seems likely to run faster than the Double versions on some CPUs.
-
-# Rest of document not yet modified:
-
 # FPR-to-GPR and GPR-to-FPR
 
 TODO special constants instruction (e, tau/N, ln 2, sqrt 2, etc.) -- exclude any constants available through fmvis