Add expected state to case_0_adde in alu_cases unit test

diff --git a/src/openpower/test/alu/alu_cases.py b/src/openpower/test/alu/alu_cases.py
index 677fc009eeb1d42c760ab0ee7a0b6004e48cbb80..4ec302fc16d70e0c47d94054663f1cbd10d9dfa6 100644 (file)
--- a/src/openpower/test/alu/alu_cases.py
+++ b/src/openpower/test/alu/alu_cases.py
@@ -255,19 +255,6 @@ class ALUTestCase(TestAccumulatorBase):
             self.add_case(Program(lst, bigendian), initial_regs)
 
     def case_0_adde(self):
-        lst = ["adde. 5, 6, 7"]
-        for i in range(10):
-            initial_regs = [0] * 32
-            initial_regs[6] = random.randint(0, (1 << 64)-1)
-            initial_regs[7] = random.randint(0, (1 << 64)-1)
-            initial_sprs = {}
-            xer = SelectableInt(0, 64)
-            xer[XER_bits['CA']] = 1
-            initial_sprs[special_sprs['XER']] = xer
-            self.add_case(Program(lst, bigendian),
-                          initial_regs, initial_sprs)
-
-    def cse_0_adde_expected(self):
         lst = ["adde. 5, 6, 7"]
         for i in range(10):
             initial_regs = [0] * 32
@@ -281,7 +268,7 @@ class ALUTestCase(TestAccumulatorBase):
             # (if it overflows, we don't care, because this is not addeo)
             result = 1 + initial_regs[6] + initial_regs[7]
             carry_out = result & (1<<64) # detect 65th bit as carry-out?
-            carry_out32 = result & (1<<32) # detect 33rd bit as carry-out?
+            carry_out32 = ((initial_regs[6] & 0xffff_ffff) + (initial_regs[7] & 0xffff_ffff)) & (1<<32)
             result = result & ((1<<64)-1) # round
             # TODO: calculate CR0
             eq = 0
@@ -298,8 +285,8 @@ class ALUTestCase(TestAccumulatorBase):
             e.intregs[6] = initial_regs[6] # should be same as initial
             e.intregs[7] = initial_regs[7] # should be same as initial
             e.intregs[5] = result
-            e.ca = carry_out | (carry_out32<<1)  # maybe other way round
-            e.crregs[0] = (eq<<1) | (gt<<2) | (le<<3) # something like this
+            e.ca = (carry_out>>64) | (carry_out32>>31)
+            e.crregs[0] = (eq<<1) | (gt<<2) | (le<<3)
 
             self.add_case(Program(lst, bigendian),
                           initial_regs, initial_sprs, expected=e)