}
/* PIPE_LOGICOP_* don't need to be translated, fortunately. */
- /* XXX are logicops still allowed if blending's disabled?
- * Does Gallium take care of it for us? */
if (state->logicop_enable) {
blend->rop = R300_RB3D_ROPCNTL_ROP_ENABLE |
(state->logicop_func) << R300_RB3D_ROPCNTL_ROP_SHIFT;
const struct pipe_clip_state* state)
{
struct r300_context* r300 = r300_context(pipe);
- /* XXX Draw */
+ /* XXX add HW TCL clipping setup */
draw_flush(r300->draw);
draw_set_clip_state(r300->draw, state);
}
const unsigned* bitfield)
{
/* XXX you know it's bad when i915 has this blank too */
+ /* XXX and even worse, I have no idea WTF the bitfield is */
}
static void
static void r300_set_polygon_stipple(struct pipe_context* pipe,
const struct pipe_poly_stipple* state)
{
- /* XXX */
+ /* XXX no idea how to set this up, but not terribly important */
}
/* Create a new rasterizer state based on the CSO rasterizer state.
struct r3xx_fragment_shader* fs);
static struct r300_fragment_shader r300_passthrough_fragment_shader = {
- /* XXX This is the emission code. TODO: decode
- OUT_CS_REG(R300_US_CONFIG, 0);
- OUT_CS_REG(R300_US_CODE_OFFSET, 0x0);
- OUT_CS_REG(R300_US_CODE_ADDR_0, 0x0);
- OUT_CS_REG(R300_US_CODE_ADDR_1, 0x0);
- OUT_CS_REG(R300_US_CODE_ADDR_2, 0x0);
- OUT_CS_REG(R300_US_CODE_ADDR_3, 0x400000);
-*/
.alu_instruction_count = 1,
.tex_instruction_count = 0,
.indirections = 0,
};
static struct r300_fragment_shader r300_texture_fragment_shader = {
- /* XXX This is the emission code. TODO: decode
- OUT_CS_REG(R300_US_CONFIG, 0);
- OUT_CS_REG(R300_US_CODE_OFFSET, 0x0);
- OUT_CS_REG(R300_US_CODE_ADDR_0, 0x0);
- OUT_CS_REG(R300_US_CODE_ADDR_1, 0x0);
- OUT_CS_REG(R300_US_CODE_ADDR_2, 0x0);
- OUT_CS_REG(R300_US_CODE_ADDR_3, 0x400000);
-*/
.alu_instruction_count = 1,
.tex_instruction_count = 0,
.indirections = 0,