Implement the addpcis instruction

This commit adds support for the addpcis instruction from ISA 3.0.

A new input_reg_b_t type, CONST_DX_HI, was added to support the
shifted immediate value used in DX-Form instructions.

Signed-off-by: Shawn Anastasio <shawn@anastas.io>

diff --git a/decode1.vhdl b/decode1.vhdl
index 4cd195f7ca4e262c0d11c5f504797199a9d98b5b..5eedbabf2349fe4a9fa50484e0466858c7ad7ab5 100644 (file)
--- a/decode1.vhdl
+++ b/decode1.vhdl
@@ -106,8 +106,8 @@ architecture behaviour of decode1 is
                --                               op                                            in   out   A   out  in    out  len        ext                                 pipe
                 -- mcrf; and cr logical ops
                2#000#    =>       (ALU,    OP_CROP,      NONE,       NONE,        NONE, NONE, '1', '1', '0', '0', ZERO, '0', NONE, '0', '0', '0', '0', '0', '0', NONE, '0', '0'),
-               -- addpcis not implemented yet
-               2#001#    =>       (ALU,    OP_ILLEGAL,   NONE,       NONE,        NONE, NONE, '0', '0', '0', '0', ZERO, '0', NONE, '0', '0', '0', '0', '0', '0', RC,   '0', '1'),
+               -- addpcis
+               2#001#    =>       (ALU,    OP_ADDPCIS,   NONE,       CONST_DX_HI, NONE, RT,   '0', '0', '0', '0', ZERO, '0', NONE, '0', '0', '0', '0', '0', '0', RC,   '0', '0'),
                 -- bclr, bcctr, bctar
                2#100#    =>       (ALU,    OP_BCREG,     SPR,        SPR,         NONE, SPR,  '1', '0', '0', '0', ZERO, '0', NONE, '0', '0', '0', '0', '0', '0', NONE, '1', '0'),
                 -- isync

diff --git a/decode2.vhdl b/decode2.vhdl
index b23939299e240ca8bfcc46d8ad29b97ba1a1c1ba..da0bdff5af5839586702903bfb8888f9b821f849 100644 (file)
--- a/decode2.vhdl
+++ b/decode2.vhdl
@@ -100,6 +100,8 @@ architecture behaviour of decode2 is
                        ret := ('0', (others => '0'), std_ulogic_vector(resize(signed(insn_bd(insn_in)) & "00", 64)));
                when CONST_DS =>
                        ret := ('0', (others => '0'), std_ulogic_vector(resize(signed(insn_ds(insn_in)) & "00", 64)));
+               when CONST_DX_HI =>
+                       ret := ('0', (others => '0'), std_ulogic_vector(resize(signed(insn_dx(insn_in)) & x"0000", 64)));
                 when CONST_M1 =>
                        ret := ('0', (others => '0'), x"FFFFFFFFFFFFFFFF");
                when CONST_SH =>

diff --git a/decode_types.vhdl b/decode_types.vhdl
index 8f000a0f9876c79367ebb39a575cf9dc98720fdf..bd1650780ca6363af2d34d0497953d1e5d4728e4 100644 (file)
--- a/decode_types.vhdl
+++ b/decode_types.vhdl
@@ -21,7 +21,7 @@ package decode_types is
                          OP_FETCH_FAILED
                         );
     type input_reg_a_t is (NONE, RA, RA_OR_ZERO, SPR);
-    type input_reg_b_t is (NONE, RB, CONST_UI, CONST_SI, CONST_SI_HI, CONST_UI_HI, CONST_LI, CONST_BD, CONST_DS, CONST_M1, CONST_SH, CONST_SH32, SPR);
+    type input_reg_b_t is (NONE, RB, CONST_UI, CONST_SI, CONST_SI_HI, CONST_UI_HI, CONST_LI, CONST_BD, CONST_DX_HI, CONST_DS, CONST_M1, CONST_SH, CONST_SH32, SPR);
     type input_reg_c_t is (NONE, RS);
     type output_reg_a_t is (NONE, RT, RA, SPR);
     type rc_t is (NONE, ONE, RC);

diff --git a/execute1.vhdl b/execute1.vhdl
index feb8581f8b4a845eaad02aa5e29d72f687ae2ed2..d8854aea6c6056886fb8cd4ff03220caf8a3a9ca 100644 (file)
--- a/execute1.vhdl
+++ b/execute1.vhdl
@@ -528,6 +528,9 @@ begin
                 end if;
            when OP_NOP =>
                -- Do nothing
+           when OP_ADDPCIS =>
+               result := ppc_adde(next_nia, b_in, '0')(63 downto 0);
+               result_en := '1';
            when OP_ADD | OP_CMP | OP_TRAP =>
                if e_in.invert_a = '0' then
                    a_inv := a_in;

diff --git a/insn_helpers.vhdl b/insn_helpers.vhdl
index 88120445484eec7c63b590f53d247df32c84e42b..acd2f729d54fbb85782e58ff3e7aee23bfc04a84 100644 (file)
--- a/insn_helpers.vhdl
+++ b/insn_helpers.vhdl
@@ -30,6 +30,7 @@ package insn_helpers is
     function insn_bh (insn_in : std_ulogic_vector) return std_ulogic_vector;
     function insn_d (insn_in : std_ulogic_vector) return std_ulogic_vector;
     function insn_ds (insn_in : std_ulogic_vector) return std_ulogic_vector;
+    function insn_dx (insn_in : std_ulogic_vector) return std_ulogic_vector;
     function insn_to (insn_in : std_ulogic_vector) return std_ulogic_vector;
     function insn_bc (insn_in : std_ulogic_vector) return std_ulogic_vector;
     function insn_sh (insn_in : std_ulogic_vector) return std_ulogic_vector;
@@ -178,6 +179,11 @@ package body insn_helpers is
         return insn_in(15 downto 2);
     end;
 
+    function insn_dx (insn_in : std_ulogic_vector) return std_ulogic_vector is
+    begin
+        return insn_in(15 downto 6) & insn_in(20 downto 16) & insn_in(0);
+    end;
+
     function insn_to (insn_in : std_ulogic_vector) return std_ulogic_vector is
     begin
         return insn_in(25 downto 21);