Fixed data width

diff --git a/techlibs/efinix/brams_map.v b/techlibs/efinix/brams_map.v
index 9ef01d0268aad9816c0bd51526fc16f168271d1b..3236f39a55c14699cf144545366db1281217ad27 100644 (file)
--- a/techlibs/efinix/brams_map.v
+++ b/techlibs/efinix/brams_map.v
@@ -22,8 +22,8 @@ module \$__EFINIX_5K (CLK2, CLK3, A1ADDR, A1DATA, A1EN, B1ADDR, B1DATA, B1EN);
        localparam WRITEMODE_A = TRANSP2 ? "WRITE_FIRST" : "READ_FIRST";
 
        EFX_RAM_5K #(
-               .READ_WIDTH(20),
-               .WRITE_WIDTH(20),
+               .READ_WIDTH(CFG_DBITS),
+               .WRITE_WIDTH(CFG_DBITS),
                .OUTPUT_REG(1'b0),
                .RCLK_POLARITY(1'b1),
                .RE_POLARITY(1'b1),