Merge remote-tracking branch 'origin/master' into xaig

diff --cc CHANGELOG
index 44e32c6a82bcb393bbc6b8aada33187059001ccf,4c38f6e6e917a5b6e01b6dbeff74cd6d3c8f8fd0..fd72d57028e2aae92ccce1cc3c587b982a0bfa51
--- 1/CHANGELOG
--- 2/CHANGELOG
+++ b/CHANGELOG
@@@ -17,11 -17,8 +17,11 @@@ Yosys 0.8 .. Yosys 0.8-de
      - Added "rename -src"
      - Added "equiv_opt" pass
      - Added "read_aiger" frontend
-     - "synth_xilinx" to now infer hard shift registers, using new "shregmap -tech xilinx"
 +    - Added "abc9" pass for timing-aware techmapping (experimental, FPGA only, no FFs)
 +    - Added "synth_xilinx -abc9" (experimental)
 +    - Added "synth_ice40 -abc9" (experimental)
 +    - Added "synth -abc9" (experimental)
 -    - "synth_xilinx" to now infer hard shift registers, using new "shregmap -tech xilinx"
+     - Extended "muxcover -mux{4,8,16}=<cost>"
  
  
  Yosys 0.7 .. Yosys 0.8

diff --cc backends/aiger/aiger.cc
Simple merge

diff --cc kernel/rtlil.cc
Simple merge