board/targets/sim: add identifier

diff --git a/litex/boards/targets/sim.py b/litex/boards/targets/sim.py
index 50cac545dca8cd459415cf944f6504d6598116c0..1624441fc86a1f2d9ab2060e72333a1e03449239 100755 (executable)
--- a/litex/boards/targets/sim.py
+++ b/litex/boards/targets/sim.py
@@ -28,6 +28,7 @@ class BaseSoC(SoCSDRAM):
         SoCSDRAM.__init__(self, platform,
             clk_freq=int((1/(platform.default_clk_period))*1000000000),
             integrated_rom_size=0x8000,
+            ident="LiteX simulation example design",
             with_uart=False,
             **kwargs)
         self.submodules.crg = CRG(platform.request(platform.default_clk_name))