warn: 5664849500: Instruction results do not match! (Values may not actually be integers) Inst: 0x36c4, checker: 0x36c8
warn: 5704830500: Instruction results do not match! (Values may not actually be integers) Inst: 0x3604, checker: 0x3608
warn: 5721485500: Instruction results do not match! (Values may not actually be integers) Inst: 0x35c4, checker: 0x35c8
+warn: 6170779000: Instruction results do not match! (Values may not actually be integers) Inst: 0x34f0, checker: 0x34f8
warn: LCD dual screen mode not supported
-warn: 53386624000: Instruction results do not match! (Values may not actually be integers) Inst: 0x19dc, checker: 0x1a04
-warn: Returning thumbEE disabled for now since we don't support CP14config registers and jumping to ThumbEE vectors
+warn: 53396857000: Instruction results do not match! (Values may not actually be integers) Inst: 0x19dc, checker: 0x1a04
+warn: 55147144000: Instruction results do not match! (Values may not actually be integers) Inst: 0x80d0, checker: 0xc71f6fc8
+warn: 55147144000: Instruction results do not match! (Values may not actually be integers) Inst: 0x71ef0, checker: 0x60000013
warn: Returning thumbEE disabled for now since we don't support CP14config registers and jumping to ThumbEE vectors
warn: Returning thumbEE disabled for now since we don't support CP14config registers and jumping to ThumbEE vectors
warn: instruction 'mcr icialluis' unimplemented
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
-gem5 compiled May 8 2012 15:17:37
-gem5 started May 8 2012 17:08:48
-gem5 executing on piton
+gem5 compiled May 10 2012 12:36:36
+gem5 started May 10 2012 12:41:59
+gem5 executing on u200540-lin
command line: build/ARM/gem5.opt -d build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview-o3-checker -re tests/run.py build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview-o3-checker
Global frequency set at 1000000000000 ticks per second
-info: kernel located at: /dist/m5/system/binaries/vmlinux.arm.smp.fb.2.6.38.8
+info: kernel located at: /projects/pd/randd/dist/binaries/vmlinux.arm.smp.fb.2.6.38.8
info: Using bootloader at address 0x80000000
info: Entering event queue @ 0. Starting simulation...
-Exiting @ tick 2501676293500 because m5_exit instruction encountered
+Exiting @ tick 2501685689500 because m5_exit instruction encountered
---------- Begin Simulation Statistics ----------
-sim_seconds 2.501676 # Number of seconds simulated
-sim_ticks 2501676293500 # Number of ticks simulated
-final_tick 2501676293500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_seconds 2.501686 # Number of seconds simulated
+sim_ticks 2501685689500 # Number of ticks simulated
+final_tick 2501685689500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 32851 # Simulator instruction rate (inst/s)
-host_op_rate 42433 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 1382341341 # Simulator tick rate (ticks/s)
-host_mem_usage 388632 # Number of bytes of host memory used
-host_seconds 1809.74 # Real time elapsed on the host
-sim_insts 59451291 # Number of instructions simulated
-sim_ops 76792341 # Number of ops (including micro ops) simulated
-system.physmem.bytes_read 129652968 # Number of bytes read from this memory
-system.physmem.bytes_inst_read 1121024 # Number of instructions bytes read from this memory
-system.physmem.bytes_written 9585096 # Number of bytes written to this memory
-system.physmem.num_reads 14979455 # Number of read requests responded to by this memory
-system.physmem.num_writes 856659 # Number of write requests responded to by this memory
+host_inst_rate 54158 # Simulator instruction rate (inst/s)
+host_op_rate 69928 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 2274069684 # Simulator tick rate (ticks/s)
+host_mem_usage 384504 # Number of bytes of host memory used
+host_seconds 1100.09 # Real time elapsed on the host
+sim_insts 59579009 # Number of instructions simulated
+sim_ops 76926775 # Number of ops (including micro ops) simulated
+system.physmem.bytes_read 129658608 # Number of bytes read from this memory
+system.physmem.bytes_inst_read 1119872 # Number of instructions bytes read from this memory
+system.physmem.bytes_written 9585736 # Number of bytes written to this memory
+system.physmem.num_reads 14980335 # Number of read requests responded to by this memory
+system.physmem.num_writes 856669 # Number of write requests responded to by this memory
system.physmem.num_other 0 # Number of other requests responded to by this memory
-system.physmem.bw_read 51826437 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read 448109 # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_write 3831469 # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_total 55657906 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_read 51828496 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read 447647 # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_write 3831711 # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_total 55660207 # Total bandwidth to/from this memory (bytes/s)
system.realview.nvmem.bytes_read 64 # Number of bytes read from this memory
system.realview.nvmem.bytes_inst_read 64 # Number of instructions bytes read from this memory
system.realview.nvmem.bytes_written 0 # Number of bytes written to this memory
system.realview.nvmem.bw_read 26 # Total read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_inst_read 26 # Instruction read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_total 26 # Total bandwidth to/from this memory (bytes/s)
-system.l2c.replacements 119784 # number of replacements
-system.l2c.tagsinuse 25999.615357 # Cycle average of tags in use
-system.l2c.total_refs 1826145 # Total number of references to valid blocks.
-system.l2c.sampled_refs 150763 # Sample count of references to valid blocks.
-system.l2c.avg_refs 12.112687 # Average number of references to valid blocks.
+system.l2c.replacements 119797 # number of replacements
+system.l2c.tagsinuse 26022.811009 # Cycle average of tags in use
+system.l2c.total_refs 1834134 # Total number of references to valid blocks.
+system.l2c.sampled_refs 150735 # Sample count of references to valid blocks.
+system.l2c.avg_refs 12.167937 # Average number of references to valid blocks.
system.l2c.warmup_cycle 0 # Cycle when the warmup percentage was hit.
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-system.l2c.occ_blocks::cpu.dtb.walker 65.344146 # Average occupied blocks per requestor
-system.l2c.occ_blocks::cpu.itb.walker 0.932012 # Average occupied blocks per requestor
-system.l2c.occ_blocks::cpu.inst 6169.201034 # Average occupied blocks per requestor
-system.l2c.occ_blocks::cpu.data 5491.716201 # Average occupied blocks per requestor
-system.l2c.occ_percent::writebacks 0.217780 # Average percentage of cache occupancy
-system.l2c.occ_percent::cpu.dtb.walker 0.000997 # Average percentage of cache occupancy
-system.l2c.occ_percent::cpu.itb.walker 0.000014 # Average percentage of cache occupancy
-system.l2c.occ_percent::cpu.inst 0.094135 # Average percentage of cache occupancy
-system.l2c.occ_percent::cpu.data 0.083797 # Average percentage of cache occupancy
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-system.l2c.ReadReq_hits::cpu.dtb.walker 141919 # number of ReadReq hits
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-system.l2c.ReadReq_hits::cpu.data 377927 # number of ReadReq hits
-system.l2c.ReadReq_hits::total 1527728 # number of ReadReq hits
-system.l2c.Writeback_hits::writebacks 634955 # number of Writeback hits
-system.l2c.Writeback_hits::total 634955 # number of Writeback hits
-system.l2c.UpgradeReq_hits::cpu.data 46 # number of UpgradeReq hits
-system.l2c.UpgradeReq_hits::total 46 # number of UpgradeReq hits
-system.l2c.SCUpgradeReq_hits::cpu.data 7 # number of SCUpgradeReq hits
-system.l2c.SCUpgradeReq_hits::total 7 # number of SCUpgradeReq hits
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-system.l2c.ReadExReq_hits::total 105770 # number of ReadExReq hits
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-system.l2c.overall_hits::total 1633498 # number of overall hits
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-system.l2c.UpgradeReq_misses::cpu.data 3302 # number of UpgradeReq misses
-system.l2c.UpgradeReq_misses::total 3302 # number of UpgradeReq misses
-system.l2c.SCUpgradeReq_misses::cpu.data 3 # number of SCUpgradeReq misses
-system.l2c.SCUpgradeReq_misses::total 3 # number of SCUpgradeReq misses
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-system.l2c.ReadExReq_misses::total 140335 # number of ReadExReq misses
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-system.l2c.demand_misses::total 177063 # number of demand (read+write) misses
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-system.l2c.overall_misses::cpu.data 159501 # number of overall misses
-system.l2c.overall_misses::total 177063 # number of overall misses
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-system.l2c.UpgradeReq_miss_latency::cpu.data 1203000 # number of UpgradeReq miss cycles
-system.l2c.UpgradeReq_miss_latency::total 1203000 # number of UpgradeReq miss cycles
-system.l2c.SCUpgradeReq_miss_latency::cpu.data 52000 # number of SCUpgradeReq miss cycles
-system.l2c.SCUpgradeReq_miss_latency::total 52000 # number of SCUpgradeReq miss cycles
-system.l2c.ReadExReq_miss_latency::cpu.data 7367598500 # number of ReadExReq miss cycles
-system.l2c.ReadExReq_miss_latency::total 7367598500 # number of ReadExReq miss cycles
-system.l2c.demand_miss_latency::cpu.dtb.walker 8196500 # number of demand (read+write) miss cycles
-system.l2c.demand_miss_latency::cpu.itb.walker 677000 # number of demand (read+write) miss cycles
-system.l2c.demand_miss_latency::cpu.inst 910933000 # number of demand (read+write) miss cycles
-system.l2c.demand_miss_latency::cpu.data 8369102000 # number of demand (read+write) miss cycles
-system.l2c.demand_miss_latency::total 9288908500 # number of demand (read+write) miss cycles
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-system.l2c.ReadReq_accesses::total 1564456 # number of ReadReq accesses(hits+misses)
-system.l2c.Writeback_accesses::writebacks 634955 # number of Writeback accesses(hits+misses)
-system.l2c.Writeback_accesses::total 634955 # number of Writeback accesses(hits+misses)
-system.l2c.UpgradeReq_accesses::cpu.data 3348 # number of UpgradeReq accesses(hits+misses)
-system.l2c.UpgradeReq_accesses::total 3348 # number of UpgradeReq accesses(hits+misses)
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-system.l2c.ReadReq_miss_rate::cpu.itb.walker 0.001072 # miss rate for ReadReq accesses
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-system.l2c.ReadReq_avg_miss_latency::cpu.itb.walker 52076.923077 # average ReadReq miss latency
-system.l2c.ReadReq_avg_miss_latency::cpu.inst 52376.552438 # average ReadReq miss latency
-system.l2c.ReadReq_avg_miss_latency::cpu.data 52254.174058 # average ReadReq miss latency
-system.l2c.UpgradeReq_avg_miss_latency::cpu.data 364.324652 # average UpgradeReq miss latency
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-system.l2c.overall_avg_mshr_miss_latency::cpu.inst 40166.292717 # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu.data 40075.476728 # average overall mshr miss latency
+system.l2c.ReadExReq_avg_mshr_miss_latency::cpu.data 40074.434038 # average ReadExReq mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu.dtb.walker 40063.829787 # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu.itb.walker 41714.285714 # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu.inst 40163.902327 # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu.data 40077.080170 # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu.dtb.walker 40063.829787 # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu.itb.walker 41714.285714 # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu.inst 40163.902327 # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu.data 40077.080170 # average overall mshr miss latency
system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu.inst inf # average ReadReq mshr uncacheable latency
system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency
system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu.data inf # average WriteReq mshr uncacheable latency
system.cf0.dma_write_txs 0 # Number of DMA write transactions.
system.cpu.checker.dtb.inst_hits 0 # ITB inst hits
system.cpu.checker.dtb.inst_misses 0 # ITB inst misses
-system.cpu.checker.dtb.read_hits 15017081 # DTB read hits
+system.cpu.checker.dtb.read_hits 15048343 # DTB read hits
system.cpu.checker.dtb.read_misses 7305 # DTB read misses
-system.cpu.checker.dtb.write_hits 11274838 # DTB write hits
+system.cpu.checker.dtb.write_hits 11293933 # DTB write hits
system.cpu.checker.dtb.write_misses 2191 # DTB write misses
system.cpu.checker.dtb.flush_tlb 4 # Number of times complete TLB was flushed
system.cpu.checker.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
system.cpu.checker.dtb.prefetch_faults 177 # Number of TLB faults due to prefetch
system.cpu.checker.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions
system.cpu.checker.dtb.perms_faults 452 # Number of TLB faults due to permissions restrictions
-system.cpu.checker.dtb.read_accesses 15024386 # DTB read accesses
-system.cpu.checker.dtb.write_accesses 11277029 # DTB write accesses
+system.cpu.checker.dtb.read_accesses 15055648 # DTB read accesses
+system.cpu.checker.dtb.write_accesses 11296124 # DTB write accesses
system.cpu.checker.dtb.inst_accesses 0 # ITB inst accesses
-system.cpu.checker.dtb.hits 26291919 # DTB hits
+system.cpu.checker.dtb.hits 26342276 # DTB hits
system.cpu.checker.dtb.misses 9496 # DTB misses
-system.cpu.checker.dtb.accesses 26301415 # DTB accesses
-system.cpu.checker.itb.inst_hits 60617853 # ITB inst hits
+system.cpu.checker.dtb.accesses 26351772 # DTB accesses
+system.cpu.checker.itb.inst_hits 60745631 # ITB inst hits
system.cpu.checker.itb.inst_misses 4471 # ITB inst misses
system.cpu.checker.itb.read_hits 0 # DTB read hits
system.cpu.checker.itb.read_misses 0 # DTB read misses
system.cpu.checker.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions
system.cpu.checker.itb.read_accesses 0 # DTB read accesses
system.cpu.checker.itb.write_accesses 0 # DTB write accesses
-system.cpu.checker.itb.inst_accesses 60622324 # ITB inst accesses
-system.cpu.checker.itb.hits 60617853 # DTB hits
+system.cpu.checker.itb.inst_accesses 60750102 # ITB inst accesses
+system.cpu.checker.itb.hits 60745631 # DTB hits
system.cpu.checker.itb.misses 4471 # DTB misses
-system.cpu.checker.itb.accesses 60622324 # DTB accesses
-system.cpu.checker.numCycles 77070710 # number of cpu cycles simulated
+system.cpu.checker.itb.accesses 60750102 # DTB accesses
+system.cpu.checker.numCycles 77205204 # number of cpu cycles simulated
system.cpu.checker.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.checker.numWorkItemsCompleted 0 # number of work items this cpu completed
system.cpu.dtb.inst_hits 0 # ITB inst hits
system.cpu.dtb.inst_misses 0 # ITB inst misses
-system.cpu.dtb.read_hits 52069399 # DTB read hits
-system.cpu.dtb.read_misses 92258 # DTB read misses
-system.cpu.dtb.write_hits 11926847 # DTB write hits
-system.cpu.dtb.write_misses 25023 # DTB write misses
+system.cpu.dtb.read_hits 52103903 # DTB read hits
+system.cpu.dtb.read_misses 93079 # DTB read misses
+system.cpu.dtb.write_hits 11946241 # DTB write hits
+system.cpu.dtb.write_misses 25022 # DTB write misses
system.cpu.dtb.flush_tlb 4 # Number of times complete TLB was flushed
system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
system.cpu.dtb.flush_tlb_mva_asid 2878 # Number of times TLB was flushed by MVA & ASID
system.cpu.dtb.flush_tlb_asid 126 # Number of times TLB was flushed by ASID
-system.cpu.dtb.flush_entries 8152 # Number of entries that have been flushed from TLB
-system.cpu.dtb.align_faults 5662 # Number of TLB faults due to alignment restrictions
-system.cpu.dtb.prefetch_faults 693 # Number of TLB faults due to prefetch
+system.cpu.dtb.flush_entries 8141 # Number of entries that have been flushed from TLB
+system.cpu.dtb.align_faults 5562 # Number of TLB faults due to alignment restrictions
+system.cpu.dtb.prefetch_faults 707 # Number of TLB faults due to prefetch
system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions
-system.cpu.dtb.perms_faults 2731 # Number of TLB faults due to permissions restrictions
-system.cpu.dtb.read_accesses 52161657 # DTB read accesses
-system.cpu.dtb.write_accesses 11951870 # DTB write accesses
+system.cpu.dtb.perms_faults 2799 # Number of TLB faults due to permissions restrictions
+system.cpu.dtb.read_accesses 52196982 # DTB read accesses
+system.cpu.dtb.write_accesses 11971263 # DTB write accesses
system.cpu.dtb.inst_accesses 0 # ITB inst accesses
-system.cpu.dtb.hits 63996246 # DTB hits
-system.cpu.dtb.misses 117281 # DTB misses
-system.cpu.dtb.accesses 64113527 # DTB accesses
-system.cpu.itb.inst_hits 13699541 # ITB inst hits
-system.cpu.itb.inst_misses 12131 # ITB inst misses
+system.cpu.dtb.hits 64050144 # DTB hits
+system.cpu.dtb.misses 118101 # DTB misses
+system.cpu.dtb.accesses 64168245 # DTB accesses
+system.cpu.itb.inst_hits 13717584 # ITB inst hits
+system.cpu.itb.inst_misses 12272 # ITB inst misses
system.cpu.itb.read_hits 0 # DTB read hits
system.cpu.itb.read_misses 0 # DTB read misses
system.cpu.itb.write_hits 0 # DTB write hits
system.cpu.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
system.cpu.itb.flush_tlb_mva_asid 2878 # Number of times TLB was flushed by MVA & ASID
system.cpu.itb.flush_tlb_asid 126 # Number of times TLB was flushed by ASID
-system.cpu.itb.flush_entries 5248 # Number of entries that have been flushed from TLB
+system.cpu.itb.flush_entries 5306 # Number of entries that have been flushed from TLB
system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions
system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch
system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions
-system.cpu.itb.perms_faults 6936 # Number of TLB faults due to permissions restrictions
+system.cpu.itb.perms_faults 6863 # Number of TLB faults due to permissions restrictions
system.cpu.itb.read_accesses 0 # DTB read accesses
system.cpu.itb.write_accesses 0 # DTB write accesses
-system.cpu.itb.inst_accesses 13711672 # ITB inst accesses
-system.cpu.itb.hits 13699541 # DTB hits
-system.cpu.itb.misses 12131 # DTB misses
-system.cpu.itb.accesses 13711672 # DTB accesses
-system.cpu.numCycles 411150559 # number of cpu cycles simulated
+system.cpu.itb.inst_accesses 13729856 # ITB inst accesses
+system.cpu.itb.hits 13717584 # DTB hits
+system.cpu.itb.misses 12272 # DTB misses
+system.cpu.itb.accesses 13729856 # DTB accesses
+system.cpu.numCycles 411352060 # number of cpu cycles simulated
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
-system.cpu.BPredUnit.lookups 15631672 # Number of BP lookups
-system.cpu.BPredUnit.condPredicted 12342234 # Number of conditional branches predicted
-system.cpu.BPredUnit.condIncorrect 929456 # Number of conditional branches incorrect
-system.cpu.BPredUnit.BTBLookups 10552810 # Number of BTB lookups
-system.cpu.BPredUnit.BTBHits 8288947 # Number of BTB hits
+system.cpu.BPredUnit.lookups 15654738 # Number of BP lookups
+system.cpu.BPredUnit.condPredicted 12362397 # Number of conditional branches predicted
+system.cpu.BPredUnit.condIncorrect 932839 # Number of conditional branches incorrect
+system.cpu.BPredUnit.BTBLookups 10530768 # Number of BTB lookups
+system.cpu.BPredUnit.BTBHits 8288874 # Number of BTB hits
system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
-system.cpu.BPredUnit.usedRAS 1323523 # Number of times the RAS was used to get a target.
-system.cpu.BPredUnit.RASInCorrect 194787 # Number of incorrect RAS predictions.
-system.cpu.fetch.icacheStallCycles 32982972 # Number of cycles fetch is stalled on an Icache miss
-system.cpu.fetch.Insts 102837345 # Number of instructions fetch has processed
-system.cpu.fetch.Branches 15631672 # Number of branches that fetch encountered
-system.cpu.fetch.predictedBranches 9612470 # Number of branches that fetch has predicted taken
-system.cpu.fetch.Cycles 22590084 # Number of cycles fetch has run and was not squashing or blocked
-system.cpu.fetch.SquashCycles 6692504 # Number of cycles fetch has spent squashing
-system.cpu.fetch.TlbCycles 158663 # Number of cycles fetch has spent waiting for tlb
-system.cpu.fetch.BlockedCycles 89850563 # Number of cycles fetch has spent blocked
-system.cpu.fetch.MiscStallCycles 2746 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
-system.cpu.fetch.PendingTrapStallCycles 143204 # Number of stall cycles due to pending traps
-system.cpu.fetch.PendingQuiesceStallCycles 218934 # Number of stall cycles due to pending quiesce instructions
-system.cpu.fetch.IcacheWaitRetryStallCycles 483 # Number of stall cycles due to full MSHR
-system.cpu.fetch.CacheLines 13691858 # Number of cache lines fetched
-system.cpu.fetch.IcacheSquashes 996334 # Number of outstanding Icache misses that were squashed
-system.cpu.fetch.ItlbSquashes 6838 # Number of outstanding ITLB misses that were squashed
-system.cpu.fetch.rateDist::samples 150553763 # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::mean 0.848436 # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::stdev 2.233477 # Number of instructions fetched each cycle (Total)
+system.cpu.BPredUnit.usedRAS 1329017 # Number of times the RAS was used to get a target.
+system.cpu.BPredUnit.RASInCorrect 195537 # Number of incorrect RAS predictions.
+system.cpu.fetch.icacheStallCycles 33116930 # Number of cycles fetch is stalled on an Icache miss
+system.cpu.fetch.Insts 103031700 # Number of instructions fetch has processed
+system.cpu.fetch.Branches 15654738 # Number of branches that fetch encountered
+system.cpu.fetch.predictedBranches 9617891 # Number of branches that fetch has predicted taken
+system.cpu.fetch.Cycles 22620194 # Number of cycles fetch has run and was not squashing or blocked
+system.cpu.fetch.SquashCycles 6706106 # Number of cycles fetch has spent squashing
+system.cpu.fetch.TlbCycles 163882 # Number of cycles fetch has spent waiting for tlb
+system.cpu.fetch.BlockedCycles 89861042 # Number of cycles fetch has spent blocked
+system.cpu.fetch.MiscStallCycles 2823 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
+system.cpu.fetch.PendingTrapStallCycles 147160 # Number of stall cycles due to pending traps
+system.cpu.fetch.PendingQuiesceStallCycles 218224 # Number of stall cycles due to pending quiesce instructions
+system.cpu.fetch.IcacheWaitRetryStallCycles 462 # Number of stall cycles due to full MSHR
+system.cpu.fetch.CacheLines 13709942 # Number of cache lines fetched
+system.cpu.fetch.IcacheSquashes 998560 # Number of outstanding Icache misses that were squashed
+system.cpu.fetch.ItlbSquashes 6868 # Number of outstanding ITLB misses that were squashed
+system.cpu.fetch.rateDist::samples 150746244 # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::mean 0.848897 # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::stdev 2.234280 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::0 127980574 85.01% 85.01% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::1 1480097 0.98% 85.99% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::2 1855620 1.23% 87.22% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::3 2694532 1.79% 89.01% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::4 1893570 1.26% 90.27% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::5 1188011 0.79% 91.06% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::6 2948135 1.96% 93.02% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::7 848652 0.56% 93.58% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::8 9664572 6.42% 100.00% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::0 128142810 85.01% 85.01% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::1 1478319 0.98% 85.99% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::2 1855018 1.23% 87.22% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::3 2695901 1.79% 89.01% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::4 1893540 1.26% 90.26% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::5 1191101 0.79% 91.05% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::6 2951659 1.96% 93.01% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::7 850848 0.56% 93.57% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::8 9687048 6.43% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::total 150553763 # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.branchRate 0.038019 # Number of branch fetches per cycle
-system.cpu.fetch.rate 0.250121 # Number of inst fetches per cycle
-system.cpu.decode.IdleCycles 35091688 # Number of cycles decode is idle
-system.cpu.decode.BlockedCycles 89690975 # Number of cycles decode is blocked
-system.cpu.decode.RunCycles 20321625 # Number of cycles decode is running
-system.cpu.decode.UnblockCycles 1025705 # Number of cycles decode is unblocking
-system.cpu.decode.SquashCycles 4423770 # Number of cycles decode is squashing
-system.cpu.decode.BranchResolved 2273029 # Number of times decode resolved a branch
-system.cpu.decode.BranchMispred 186320 # Number of times decode detected a branch misprediction
-system.cpu.decode.DecodedInsts 119828190 # Number of instructions handled by decode
-system.cpu.decode.SquashedInsts 605140 # Number of squashed instructions handled by decode
-system.cpu.rename.SquashCycles 4423770 # Number of cycles rename is squashing
-system.cpu.rename.IdleCycles 37165531 # Number of cycles rename is idle
-system.cpu.rename.BlockCycles 37166387 # Number of cycles rename is blocking
-system.cpu.rename.serializeStallCycles 46484492 # count of cycles rename stalled for serializing inst
-system.cpu.rename.RunCycles 19226681 # Number of cycles rename is running
-system.cpu.rename.UnblockCycles 6086902 # Number of cycles rename is unblocking
-system.cpu.rename.RenamedInsts 112339029 # Number of instructions processed by rename
-system.cpu.rename.ROBFullEvents 3754 # Number of times rename has blocked due to ROB full
-system.cpu.rename.IQFullEvents 1012932 # Number of times rename has blocked due to IQ full
-system.cpu.rename.LSQFullEvents 4107831 # Number of times rename has blocked due to LSQ full
-system.cpu.rename.FullRegisterEvents 44905 # Number of times there has been no free registers
-system.cpu.rename.RenamedOperands 116884712 # Number of destination operands rename has renamed
-system.cpu.rename.RenameLookups 516607430 # Number of register rename lookups that rename has made
-system.cpu.rename.int_rename_lookups 516512877 # Number of integer rename lookups
-system.cpu.rename.fp_rename_lookups 94553 # Number of floating rename lookups
-system.cpu.rename.CommittedMaps 77495227 # Number of HB maps that are committed
-system.cpu.rename.UndoneMaps 39389484 # Number of HB maps that are undone due to squashing
-system.cpu.rename.serializingInsts 939636 # count of serializing insts renamed
-system.cpu.rename.tempSerializingInsts 835400 # count of temporary serializing insts renamed
-system.cpu.rename.skidInsts 12435347 # count of insts added to the skid buffer
-system.cpu.memDep0.insertedLoads 21635443 # Number of loads inserted to the mem dependence unit.
-system.cpu.memDep0.insertedStores 14050113 # Number of stores inserted to the mem dependence unit.
-system.cpu.memDep0.conflictingLoads 1939177 # Number of conflicting loads.
-system.cpu.memDep0.conflictingStores 2494760 # Number of conflicting stores.
-system.cpu.iq.iqInstsAdded 102209700 # Number of instructions added to the IQ (excludes non-spec)
-system.cpu.iq.iqNonSpecInstsAdded 1618930 # Number of non-speculative instructions added to the IQ
-system.cpu.iq.iqInstsIssued 126189021 # Number of instructions issued
-system.cpu.iq.iqSquashedInstsIssued 231742 # Number of squashed instructions issued
-system.cpu.iq.iqSquashedInstsExamined 26205661 # Number of squashed instructions iterated over during squash; mainly for profiling
-system.cpu.iq.iqSquashedOperandsExamined 71388624 # Number of squashed operands that are examined and possibly removed from graph
-system.cpu.iq.iqSquashedNonSpecRemoved 331981 # Number of squashed non-spec instructions that were removed
-system.cpu.iq.issued_per_cycle::samples 150553763 # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::mean 0.838166 # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::stdev 1.542583 # Number of insts issued each cycle
+system.cpu.fetch.rateDist::total 150746244 # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.branchRate 0.038057 # Number of branch fetches per cycle
+system.cpu.fetch.rate 0.250471 # Number of inst fetches per cycle
+system.cpu.decode.IdleCycles 35228906 # Number of cycles decode is idle
+system.cpu.decode.BlockedCycles 89710063 # Number of cycles decode is blocked
+system.cpu.decode.RunCycles 20347806 # Number of cycles decode is running
+system.cpu.decode.UnblockCycles 1026685 # Number of cycles decode is unblocking
+system.cpu.decode.SquashCycles 4432784 # Number of cycles decode is squashing
+system.cpu.decode.BranchResolved 2275641 # Number of times decode resolved a branch
+system.cpu.decode.BranchMispred 186729 # Number of times decode detected a branch misprediction
+system.cpu.decode.DecodedInsts 120042439 # Number of instructions handled by decode
+system.cpu.decode.SquashedInsts 604390 # Number of squashed instructions handled by decode
+system.cpu.rename.SquashCycles 4432784 # Number of cycles rename is squashing
+system.cpu.rename.IdleCycles 37305734 # Number of cycles rename is idle
+system.cpu.rename.BlockCycles 37165628 # Number of cycles rename is blocking
+system.cpu.rename.serializeStallCycles 46502465 # count of cycles rename stalled for serializing inst
+system.cpu.rename.RunCycles 19251695 # Number of cycles rename is running
+system.cpu.rename.UnblockCycles 6087938 # Number of cycles rename is unblocking
+system.cpu.rename.RenamedInsts 112539597 # Number of instructions processed by rename
+system.cpu.rename.ROBFullEvents 3873 # Number of times rename has blocked due to ROB full
+system.cpu.rename.IQFullEvents 1013212 # Number of times rename has blocked due to IQ full
+system.cpu.rename.LSQFullEvents 4109157 # Number of times rename has blocked due to LSQ full
+system.cpu.rename.FullRegisterEvents 45575 # Number of times there has been no free registers
+system.cpu.rename.RenamedOperands 117156815 # Number of destination operands rename has renamed
+system.cpu.rename.RenameLookups 517555842 # Number of register rename lookups that rename has made
+system.cpu.rename.int_rename_lookups 517460811 # Number of integer rename lookups
+system.cpu.rename.fp_rename_lookups 95031 # Number of floating rename lookups
+system.cpu.rename.CommittedMaps 77687687 # Number of HB maps that are committed
+system.cpu.rename.UndoneMaps 39469127 # Number of HB maps that are undone due to squashing
+system.cpu.rename.serializingInsts 939790 # count of serializing insts renamed
+system.cpu.rename.tempSerializingInsts 835958 # count of temporary serializing insts renamed
+system.cpu.rename.skidInsts 12443241 # count of insts added to the skid buffer
+system.cpu.memDep0.insertedLoads 21685850 # Number of loads inserted to the mem dependence unit.
+system.cpu.memDep0.insertedStores 14072237 # Number of stores inserted to the mem dependence unit.
+system.cpu.memDep0.conflictingLoads 1938675 # Number of conflicting loads.
+system.cpu.memDep0.conflictingStores 2482763 # Number of conflicting stores.
+system.cpu.iq.iqInstsAdded 102391550 # Number of instructions added to the IQ (excludes non-spec)
+system.cpu.iq.iqNonSpecInstsAdded 1619583 # Number of non-speculative instructions added to the IQ
+system.cpu.iq.iqInstsIssued 126350622 # Number of instructions issued
+system.cpu.iq.iqSquashedInstsIssued 234593 # Number of squashed instructions issued
+system.cpu.iq.iqSquashedInstsExamined 26254924 # Number of squashed instructions iterated over during squash; mainly for profiling
+system.cpu.iq.iqSquashedOperandsExamined 71509700 # Number of squashed operands that are examined and possibly removed from graph
+system.cpu.iq.iqSquashedNonSpecRemoved 332277 # Number of squashed non-spec instructions that were removed
+system.cpu.iq.issued_per_cycle::samples 150746244 # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::mean 0.838168 # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::stdev 1.542455 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::0 105343416 69.97% 69.97% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::1 14065037 9.34% 79.31% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::2 7354541 4.88% 84.20% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::3 5909522 3.93% 88.12% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::4 12758140 8.47% 96.60% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::5 2807768 1.86% 98.46% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::6 1730475 1.15% 99.61% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::7 446826 0.30% 99.91% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::8 138038 0.09% 100.00% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::0 105470655 69.97% 69.97% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::1 14086510 9.34% 79.31% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::2 7371222 4.89% 84.20% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::3 5923402 3.93% 88.13% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::4 12762751 8.47% 96.60% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::5 2810704 1.86% 98.46% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::6 1735902 1.15% 99.61% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::7 449258 0.30% 99.91% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::8 135840 0.09% 100.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::total 150553763 # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::total 150746244 # Number of insts issued each cycle
system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntAlu 60599 0.68% 0.68% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntMult 2 0.00% 0.68% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntDiv 0 0.00% 0.68% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatAdd 0 0.00% 0.68% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatCmp 0 0.00% 0.68% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatCvt 0 0.00% 0.68% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatMult 0 0.00% 0.68% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatDiv 0 0.00% 0.68% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatSqrt 0 0.00% 0.68% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAdd 0 0.00% 0.68% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 0.68% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAlu 0 0.00% 0.68% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdCmp 0 0.00% 0.68% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdCvt 0 0.00% 0.68% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMisc 0 0.00% 0.68% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMult 0 0.00% 0.68% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 0.68% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdShift 0 0.00% 0.68% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 0.68% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdSqrt 0 0.00% 0.68% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 0.68% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 0.68% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 0.68% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 0.68% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 0.68% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 0.68% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 0.68% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 0.68% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 0.68% # attempts to use FU when none available
-system.cpu.iq.fu_full::MemRead 8416262 94.64% 95.32% # attempts to use FU when none available
-system.cpu.iq.fu_full::MemWrite 416317 4.68% 100.00% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntAlu 61043 0.69% 0.69% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntMult 4 0.00% 0.69% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntDiv 0 0.00% 0.69% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatAdd 0 0.00% 0.69% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatCmp 0 0.00% 0.69% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatCvt 0 0.00% 0.69% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatMult 0 0.00% 0.69% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatDiv 0 0.00% 0.69% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatSqrt 0 0.00% 0.69% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAdd 0 0.00% 0.69% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 0.69% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAlu 0 0.00% 0.69% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdCmp 0 0.00% 0.69% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdCvt 0 0.00% 0.69% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMisc 0 0.00% 0.69% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMult 0 0.00% 0.69% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 0.69% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdShift 0 0.00% 0.69% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 0.69% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdSqrt 0 0.00% 0.69% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 0.69% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 0.69% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 0.69% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 0.69% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 0.69% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 0.69% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 0.69% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 0.69% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 0.69% # attempts to use FU when none available
+system.cpu.iq.fu_full::MemRead 8421186 94.66% 95.34% # attempts to use FU when none available
+system.cpu.iq.fu_full::MemWrite 414230 4.66% 100.00% # attempts to use FU when none available
system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available
system.cpu.iq.FU_type_0::No_OpClass 106530 0.08% 0.08% # Type of FU issued
-system.cpu.iq.FU_type_0::IntAlu 59665616 47.28% 47.37% # Type of FU issued
-system.cpu.iq.FU_type_0::IntMult 95635 0.08% 47.44% # Type of FU issued
-system.cpu.iq.FU_type_0::IntDiv 0 0.00% 47.44% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 47.44% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 47.44% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 47.44% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatMult 0 0.00% 47.44% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 47.44% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 47.44% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 47.44% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 47.44% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 47.44% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 47.44% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 47.44% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdMisc 36 0.00% 47.44% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdMult 0 0.00% 47.44% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 47.44% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdShift 48 0.00% 47.44% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdShiftAcc 9 0.00% 47.44% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 47.44% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 47.44% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 47.44% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 47.44% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 47.44% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 47.44% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatMisc 2270 0.00% 47.44% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 47.44% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatMultAcc 9 0.00% 47.44% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 47.44% # Type of FU issued
-system.cpu.iq.FU_type_0::MemRead 53732100 42.58% 90.03% # Type of FU issued
-system.cpu.iq.FU_type_0::MemWrite 12586768 9.97% 100.00% # Type of FU issued
+system.cpu.iq.FU_type_0::IntAlu 59762768 47.30% 47.38% # Type of FU issued
+system.cpu.iq.FU_type_0::IntMult 95812 0.08% 47.46% # Type of FU issued
+system.cpu.iq.FU_type_0::IntDiv 0 0.00% 47.46% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 47.46% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 47.46% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 47.46% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatMult 0 0.00% 47.46% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 47.46% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 47.46% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 47.46% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 47.46% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 47.46% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 47.46% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 47.46% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdMisc 38 0.00% 47.46% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdMult 0 0.00% 47.46% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 47.46% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdShift 45 0.00% 47.46% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdShiftAcc 9 0.00% 47.46% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 47.46% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 47.46% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 47.46% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 47.46% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 47.46% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 47.46% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatMisc 2279 0.00% 47.46% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 47.46% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatMultAcc 9 0.00% 47.46% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 47.46% # Type of FU issued
+system.cpu.iq.FU_type_0::MemRead 53776494 42.56% 90.02% # Type of FU issued
+system.cpu.iq.FU_type_0::MemWrite 12606638 9.98% 100.00% # Type of FU issued
system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued
system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued
-system.cpu.iq.FU_type_0::total 126189021 # Type of FU issued
-system.cpu.iq.rate 0.306917 # Inst issue rate
-system.cpu.iq.fu_busy_cnt 8893180 # FU busy when requested
-system.cpu.iq.fu_busy_rate 0.070475 # FU busy rate (busy events/executed inst)
-system.cpu.iq.int_inst_queue_reads 412149363 # Number of integer instruction queue reads
-system.cpu.iq.int_inst_queue_writes 130053896 # Number of integer instruction queue writes
-system.cpu.iq.int_inst_queue_wakeup_accesses 86886822 # Number of integer instruction queue wakeup accesses
-system.cpu.iq.fp_inst_queue_reads 24048 # Number of floating instruction queue reads
-system.cpu.iq.fp_inst_queue_writes 13080 # Number of floating instruction queue writes
-system.cpu.iq.fp_inst_queue_wakeup_accesses 10409 # Number of floating instruction queue wakeup accesses
-system.cpu.iq.int_alu_accesses 134962848 # Number of integer alu accesses
-system.cpu.iq.fp_alu_accesses 12823 # Number of floating point alu accesses
-system.cpu.iew.lsq.thread0.forwLoads 636825 # Number of loads that had data forwarded from stores
+system.cpu.iq.FU_type_0::total 126350622 # Type of FU issued
+system.cpu.iq.rate 0.307159 # Inst issue rate
+system.cpu.iq.fu_busy_cnt 8896463 # FU busy when requested
+system.cpu.iq.fu_busy_rate 0.070411 # FU busy rate (busy events/executed inst)
+system.cpu.iq.int_inst_queue_reads 412671946 # Number of integer instruction queue reads
+system.cpu.iq.int_inst_queue_writes 130285978 # Number of integer instruction queue writes
+system.cpu.iq.int_inst_queue_wakeup_accesses 87040433 # Number of integer instruction queue wakeup accesses
+system.cpu.iq.fp_inst_queue_reads 24078 # Number of floating instruction queue reads
+system.cpu.iq.fp_inst_queue_writes 13182 # Number of floating instruction queue writes
+system.cpu.iq.fp_inst_queue_wakeup_accesses 10434 # Number of floating instruction queue wakeup accesses
+system.cpu.iq.int_alu_accesses 135127716 # Number of integer alu accesses
+system.cpu.iq.fp_alu_accesses 12839 # Number of floating point alu accesses
+system.cpu.iew.lsq.thread0.forwLoads 636069 # Number of loads that had data forwarded from stores
system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address
-system.cpu.iew.lsq.thread0.squashedLoads 5953964 # Number of loads squashed
-system.cpu.iew.lsq.thread0.ignoredResponses 11249 # Number of memory responses ignored because the instruction is squashed
-system.cpu.iew.lsq.thread0.memOrderViolation 33793 # Number of memory ordering violations
-system.cpu.iew.lsq.thread0.squashedStores 2270680 # Number of stores squashed
+system.cpu.iew.lsq.thread0.squashedLoads 5970496 # Number of loads squashed
+system.cpu.iew.lsq.thread0.ignoredResponses 11101 # Number of memory responses ignored because the instruction is squashed
+system.cpu.iew.lsq.thread0.memOrderViolation 34253 # Number of memory ordering violations
+system.cpu.iew.lsq.thread0.squashedStores 2273952 # Number of stores squashed
system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
-system.cpu.iew.lsq.thread0.rescheduledLoads 34115287 # Number of loads that were rescheduled
-system.cpu.iew.lsq.thread0.cacheBlocked 1151875 # Number of times an access to memory failed due to the cache being blocked
+system.cpu.iew.lsq.thread0.rescheduledLoads 34114355 # Number of loads that were rescheduled
+system.cpu.iew.lsq.thread0.cacheBlocked 1152098 # Number of times an access to memory failed due to the cache being blocked
system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle
-system.cpu.iew.iewSquashCycles 4423770 # Number of cycles IEW is squashing
-system.cpu.iew.iewBlockCycles 28606306 # Number of cycles IEW is blocking
-system.cpu.iew.iewUnblockCycles 435959 # Number of cycles IEW is unblocking
-system.cpu.iew.iewDispatchedInsts 104089793 # Number of instructions dispatched to IQ
-system.cpu.iew.iewDispSquashedInsts 334839 # Number of squashed instructions skipped by dispatch
-system.cpu.iew.iewDispLoadInsts 21635443 # Number of dispatched load instructions
-system.cpu.iew.iewDispStoreInsts 14050113 # Number of dispatched store instructions
-system.cpu.iew.iewDispNonSpecInsts 991881 # Number of dispatched non-speculative instructions
-system.cpu.iew.iewIQFullEvents 95881 # Number of times the IQ has become full, causing a stall
-system.cpu.iew.iewLSQFullEvents 11592 # Number of times the LSQ has become full, causing a stall
-system.cpu.iew.memOrderViolationEvents 33793 # Number of memory order violations
-system.cpu.iew.predictedTakenIncorrect 550966 # Number of branches that were predicted taken incorrectly
-system.cpu.iew.predictedNotTakenIncorrect 345374 # Number of branches that were predicted not taken incorrectly
-system.cpu.iew.branchMispredicts 896340 # Number of branch mispredicts detected at execute
-system.cpu.iew.iewExecutedInsts 122956903 # Number of executed instructions
-system.cpu.iew.iewExecLoadInsts 52760819 # Number of load instructions executed
-system.cpu.iew.iewExecSquashedInsts 3232118 # Number of squashed instructions skipped in execute
+system.cpu.iew.iewSquashCycles 4432784 # Number of cycles IEW is squashing
+system.cpu.iew.iewBlockCycles 28604721 # Number of cycles IEW is blocking
+system.cpu.iew.iewUnblockCycles 436722 # Number of cycles IEW is unblocking
+system.cpu.iew.iewDispatchedInsts 104273041 # Number of instructions dispatched to IQ
+system.cpu.iew.iewDispSquashedInsts 335924 # Number of squashed instructions skipped by dispatch
+system.cpu.iew.iewDispLoadInsts 21685850 # Number of dispatched load instructions
+system.cpu.iew.iewDispStoreInsts 14072237 # Number of dispatched store instructions
+system.cpu.iew.iewDispNonSpecInsts 992808 # Number of dispatched non-speculative instructions
+system.cpu.iew.iewIQFullEvents 95700 # Number of times the IQ has become full, causing a stall
+system.cpu.iew.iewLSQFullEvents 11591 # Number of times the LSQ has become full, causing a stall
+system.cpu.iew.memOrderViolationEvents 34253 # Number of memory order violations
+system.cpu.iew.predictedTakenIncorrect 552378 # Number of branches that were predicted taken incorrectly
+system.cpu.iew.predictedNotTakenIncorrect 346914 # Number of branches that were predicted not taken incorrectly
+system.cpu.iew.branchMispredicts 899292 # Number of branch mispredicts detected at execute
+system.cpu.iew.iewExecutedInsts 123108789 # Number of executed instructions
+system.cpu.iew.iewExecLoadInsts 52799372 # Number of load instructions executed
+system.cpu.iew.iewExecSquashedInsts 3241833 # Number of squashed instructions skipped in execute
system.cpu.iew.exec_swp 0 # number of swp insts executed
-system.cpu.iew.exec_nop 261163 # number of nop insts executed
-system.cpu.iew.exec_refs 65197273 # number of memory reference insts executed
-system.cpu.iew.exec_branches 11589071 # Number of branches executed
-system.cpu.iew.exec_stores 12436454 # Number of stores executed
-system.cpu.iew.exec_rate 0.299056 # Inst execution rate
-system.cpu.iew.wb_sent 121403477 # cumulative count of insts sent to commit
-system.cpu.iew.wb_count 86897231 # cumulative count of insts written-back
-system.cpu.iew.wb_producers 47438485 # num instructions producing a value
-system.cpu.iew.wb_consumers 88321921 # num instructions consuming a value
+system.cpu.iew.exec_nop 261908 # number of nop insts executed
+system.cpu.iew.exec_refs 65255060 # number of memory reference insts executed
+system.cpu.iew.exec_branches 11601340 # Number of branches executed
+system.cpu.iew.exec_stores 12455688 # Number of stores executed
+system.cpu.iew.exec_rate 0.299278 # Inst execution rate
+system.cpu.iew.wb_sent 121555618 # cumulative count of insts sent to commit
+system.cpu.iew.wb_count 87050867 # cumulative count of insts written-back
+system.cpu.iew.wb_producers 47546734 # num instructions producing a value
+system.cpu.iew.wb_consumers 88572059 # num instructions consuming a value
system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ
-system.cpu.iew.wb_rate 0.211351 # insts written-back per cycle
-system.cpu.iew.wb_fanout 0.537109 # average fanout of values written-back
+system.cpu.iew.wb_rate 0.211621 # insts written-back per cycle
+system.cpu.iew.wb_fanout 0.536814 # average fanout of values written-back
system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ
-system.cpu.commit.commitCommittedInsts 59601672 # The number of committed instructions
-system.cpu.commit.commitCommittedOps 76942722 # The number of committed instructions
-system.cpu.commit.commitSquashedInsts 26965943 # The number of squashed insts skipped by commit
-system.cpu.commit.commitNonSpecStalls 1286949 # The number of times commit has been forced to stall to communicate backwards
-system.cpu.commit.branchMispredicts 790517 # The number of times a branch was mispredicted
-system.cpu.commit.committed_per_cycle::samples 146212348 # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::mean 0.526240 # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::stdev 1.505087 # Number of insts commited each cycle
+system.cpu.commit.commitCommittedInsts 59729390 # The number of committed instructions
+system.cpu.commit.commitCommittedOps 77077156 # The number of committed instructions
+system.cpu.commit.commitSquashedInsts 27015439 # The number of squashed insts skipped by commit
+system.cpu.commit.commitNonSpecStalls 1287306 # The number of times commit has been forced to stall to communicate backwards
+system.cpu.commit.branchMispredicts 793496 # The number of times a branch was mispredicted
+system.cpu.commit.committed_per_cycle::samples 146395876 # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::mean 0.526498 # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::stdev 1.504904 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::0 118498573 81.05% 81.05% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::1 13699176 9.37% 90.41% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::2 3966547 2.71% 93.13% # Number of insts commited each cycle
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-system.cpu.dcache.overall_miss_latency::total 121373112764 # number of overall miss cycles
-system.cpu.dcache.ReadReq_accesses::cpu.data 14928261 # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.ReadReq_accesses::total 14928261 # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.WriteReq_accesses::cpu.data 10231545 # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.WriteReq_accesses::total 10231545 # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.LoadLockedReq_accesses::cpu.data 299609 # number of LoadLockedReq accesses(hits+misses)
-system.cpu.dcache.LoadLockedReq_accesses::total 299609 # number of LoadLockedReq accesses(hits+misses)
-system.cpu.dcache.StoreCondReq_accesses::cpu.data 285529 # number of StoreCondReq accesses(hits+misses)
-system.cpu.dcache.StoreCondReq_accesses::total 285529 # number of StoreCondReq accesses(hits+misses)
-system.cpu.dcache.demand_accesses::cpu.data 25159806 # number of demand (read+write) accesses
-system.cpu.dcache.demand_accesses::total 25159806 # number of demand (read+write) accesses
-system.cpu.dcache.overall_accesses::cpu.data 25159806 # number of overall (read+write) accesses
-system.cpu.dcache.overall_accesses::total 25159806 # number of overall (read+write) accesses
-system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.049968 # miss rate for ReadReq accesses
-system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.289869 # miss rate for WriteReq accesses
-system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.045920 # miss rate for LoadLockedReq accesses
-system.cpu.dcache.StoreCondReq_miss_rate::cpu.data 0.000035 # miss rate for StoreCondReq accesses
-system.cpu.dcache.demand_miss_rate::cpu.data 0.147527 # miss rate for demand accesses
-system.cpu.dcache.overall_miss_rate::cpu.data 0.147527 # miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 15056.128885 # average ReadReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 37137.389815 # average WriteReq miss latency
-system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 16312.218346 # average LoadLockedReq miss latency
-system.cpu.dcache.StoreCondReq_avg_miss_latency::cpu.data 26750 # average StoreCondReq miss latency
-system.cpu.dcache.demand_avg_miss_latency::cpu.data 32699.797255 # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::cpu.data 32699.797255 # average overall miss latency
-system.cpu.dcache.blocked_cycles::no_mshrs 16852944 # number of cycles access was blocked
-system.cpu.dcache.blocked_cycles::no_targets 7563500 # number of cycles access was blocked
-system.cpu.dcache.blocked::no_mshrs 2993 # number of cycles access was blocked
-system.cpu.dcache.blocked::no_targets 267 # number of cycles access was blocked
-system.cpu.dcache.avg_blocked_cycles::no_mshrs 5630.786502 # average number of cycles each access was blocked
-system.cpu.dcache.avg_blocked_cycles::no_targets 28327.715356 # average number of cycles each access was blocked
+system.cpu.dcache.ReadReq_hits::cpu.data 14216478 # number of ReadReq hits
+system.cpu.dcache.ReadReq_hits::total 14216478 # number of ReadReq hits
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+system.cpu.dcache.StoreCondReq_hits::total 285655 # number of StoreCondReq hits
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+system.cpu.dcache.demand_hits::total 21500114 # number of demand (read+write) hits
+system.cpu.dcache.overall_hits::cpu.data 21500114 # number of overall hits
+system.cpu.dcache.overall_hits::total 21500114 # number of overall hits
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+system.cpu.dcache.ReadReq_misses::total 747655 # number of ReadReq misses
+system.cpu.dcache.WriteReq_misses::cpu.data 2966865 # number of WriteReq misses
+system.cpu.dcache.WriteReq_misses::total 2966865 # number of WriteReq misses
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+system.cpu.dcache.StoreCondReq_misses::total 13 # number of StoreCondReq misses
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+system.cpu.dcache.demand_misses::total 3714520 # number of demand (read+write) misses
+system.cpu.dcache.overall_misses::cpu.data 3714520 # number of overall misses
+system.cpu.dcache.overall_misses::total 3714520 # number of overall misses
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+system.cpu.dcache.ReadReq_miss_latency::total 11237363500 # number of ReadReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::cpu.data 110154178240 # number of WriteReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::total 110154178240 # number of WriteReq miss cycles
+system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 224042000 # number of LoadLockedReq miss cycles
+system.cpu.dcache.LoadLockedReq_miss_latency::total 224042000 # number of LoadLockedReq miss cycles
+system.cpu.dcache.StoreCondReq_miss_latency::cpu.data 394000 # number of StoreCondReq miss cycles
+system.cpu.dcache.StoreCondReq_miss_latency::total 394000 # number of StoreCondReq miss cycles
+system.cpu.dcache.demand_miss_latency::cpu.data 121391541740 # number of demand (read+write) miss cycles
+system.cpu.dcache.demand_miss_latency::total 121391541740 # number of demand (read+write) miss cycles
+system.cpu.dcache.overall_miss_latency::cpu.data 121391541740 # number of overall miss cycles
+system.cpu.dcache.overall_miss_latency::total 121391541740 # number of overall miss cycles
+system.cpu.dcache.ReadReq_accesses::cpu.data 14964133 # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.ReadReq_accesses::total 14964133 # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.WriteReq_accesses::cpu.data 10250501 # number of WriteReq accesses(hits+misses)
+system.cpu.dcache.WriteReq_accesses::total 10250501 # number of WriteReq accesses(hits+misses)
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+system.cpu.dcache.LoadLockedReq_accesses::total 299839 # number of LoadLockedReq accesses(hits+misses)
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+system.cpu.dcache.StoreCondReq_accesses::total 285668 # number of StoreCondReq accesses(hits+misses)
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+system.cpu.dcache.demand_accesses::total 25214634 # number of demand (read+write) accesses
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+system.cpu.dcache.overall_accesses::total 25214634 # number of overall (read+write) accesses
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+system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.289436 # miss rate for WriteReq accesses
+system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.045848 # miss rate for LoadLockedReq accesses
+system.cpu.dcache.StoreCondReq_miss_rate::cpu.data 0.000046 # miss rate for StoreCondReq accesses
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+system.cpu.dcache.overall_miss_rate::cpu.data 0.147316 # miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 15030.145589 # average ReadReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 37128.139717 # average WriteReq miss latency
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+system.cpu.dcache.overall_avg_miss_latency::cpu.data 32680.276789 # average overall miss latency
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+system.cpu.dcache.blocked_cycles::no_targets 7607500 # number of cycles access was blocked
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+system.cpu.dcache.avg_blocked_cycles::no_targets 28386.194030 # average number of cycles each access was blocked
system.cpu.dcache.fast_writes 0 # number of fast writes performed
system.cpu.dcache.cache_copies 0 # number of cache copies performed
-system.cpu.dcache.writebacks::writebacks 575111 # number of writebacks
-system.cpu.dcache.writebacks::total 575111 # number of writebacks
-system.cpu.dcache.ReadReq_mshr_hits::cpu.data 358347 # number of ReadReq MSHR hits
-system.cpu.dcache.ReadReq_mshr_hits::total 358347 # number of ReadReq MSHR hits
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-system.cpu.dcache.WriteReq_mshr_hits::total 2716460 # number of WriteReq MSHR hits
-system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 1395 # number of LoadLockedReq MSHR hits
-system.cpu.dcache.LoadLockedReq_mshr_hits::total 1395 # number of LoadLockedReq MSHR hits
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-system.cpu.dcache.demand_mshr_hits::total 3074807 # number of demand (read+write) MSHR hits
-system.cpu.dcache.overall_mshr_hits::cpu.data 3074807 # number of overall MSHR hits
-system.cpu.dcache.overall_mshr_hits::total 3074807 # number of overall MSHR hits
-system.cpu.dcache.ReadReq_mshr_misses::cpu.data 387588 # number of ReadReq MSHR misses
-system.cpu.dcache.ReadReq_mshr_misses::total 387588 # number of ReadReq MSHR misses
-system.cpu.dcache.WriteReq_mshr_misses::cpu.data 249344 # number of WriteReq MSHR misses
-system.cpu.dcache.WriteReq_mshr_misses::total 249344 # number of WriteReq MSHR misses
-system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data 12363 # number of LoadLockedReq MSHR misses
-system.cpu.dcache.LoadLockedReq_mshr_misses::total 12363 # number of LoadLockedReq MSHR misses
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-system.cpu.dcache.StoreCondReq_mshr_misses::total 10 # number of StoreCondReq MSHR misses
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-system.cpu.dcache.demand_mshr_misses::total 636932 # number of demand (read+write) MSHR misses
-system.cpu.dcache.overall_mshr_misses::cpu.data 636932 # number of overall MSHR misses
-system.cpu.dcache.overall_mshr_misses::total 636932 # number of overall MSHR misses
-system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 5281773000 # number of ReadReq MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_latency::total 5281773000 # number of ReadReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 8909514444 # number of WriteReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::total 8909514444 # number of WriteReq MSHR miss cycles
-system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data 166180500 # number of LoadLockedReq MSHR miss cycles
-system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 166180500 # number of LoadLockedReq MSHR miss cycles
-system.cpu.dcache.StoreCondReq_mshr_miss_latency::cpu.data 235000 # number of StoreCondReq MSHR miss cycles
-system.cpu.dcache.StoreCondReq_mshr_miss_latency::total 235000 # number of StoreCondReq MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::cpu.data 14191287444 # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::total 14191287444 # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::cpu.data 14191287444 # number of overall MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::total 14191287444 # number of overall MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 147159264500 # number of ReadReq MSHR uncacheable cycles
-system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 147159264500 # number of ReadReq MSHR uncacheable cycles
-system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data 42252638495 # number of WriteReq MSHR uncacheable cycles
-system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total 42252638495 # number of WriteReq MSHR uncacheable cycles
-system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 189411902995 # number of overall MSHR uncacheable cycles
-system.cpu.dcache.overall_mshr_uncacheable_latency::total 189411902995 # number of overall MSHR uncacheable cycles
-system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.025963 # mshr miss rate for ReadReq accesses
-system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.024370 # mshr miss rate for WriteReq accesses
-system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.041264 # mshr miss rate for LoadLockedReq accesses
-system.cpu.dcache.StoreCondReq_mshr_miss_rate::cpu.data 0.000035 # mshr miss rate for StoreCondReq accesses
-system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.025315 # mshr miss rate for demand accesses
-system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.025315 # mshr miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 13627.287223 # average ReadReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 35731.818067 # average WriteReq mshr miss latency
-system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 13441.761708 # average LoadLockedReq mshr miss latency
-system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::cpu.data 23500 # average StoreCondReq mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 22280.694712 # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 22280.694712 # average overall mshr miss latency
+system.cpu.dcache.writebacks::writebacks 574932 # number of writebacks
+system.cpu.dcache.writebacks::total 574932 # number of writebacks
+system.cpu.dcache.ReadReq_mshr_hits::cpu.data 359686 # number of ReadReq MSHR hits
+system.cpu.dcache.ReadReq_mshr_hits::total 359686 # number of ReadReq MSHR hits
+system.cpu.dcache.WriteReq_mshr_hits::cpu.data 2717440 # number of WriteReq MSHR hits
+system.cpu.dcache.WriteReq_mshr_hits::total 2717440 # number of WriteReq MSHR hits
+system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 1386 # number of LoadLockedReq MSHR hits
+system.cpu.dcache.LoadLockedReq_mshr_hits::total 1386 # number of LoadLockedReq MSHR hits
+system.cpu.dcache.demand_mshr_hits::cpu.data 3077126 # number of demand (read+write) MSHR hits
+system.cpu.dcache.demand_mshr_hits::total 3077126 # number of demand (read+write) MSHR hits
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+system.cpu.dcache.overall_mshr_hits::total 3077126 # number of overall MSHR hits
+system.cpu.dcache.ReadReq_mshr_misses::cpu.data 387969 # number of ReadReq MSHR misses
+system.cpu.dcache.ReadReq_mshr_misses::total 387969 # number of ReadReq MSHR misses
+system.cpu.dcache.WriteReq_mshr_misses::cpu.data 249425 # number of WriteReq MSHR misses
+system.cpu.dcache.WriteReq_mshr_misses::total 249425 # number of WriteReq MSHR misses
+system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data 12361 # number of LoadLockedReq MSHR misses
+system.cpu.dcache.LoadLockedReq_mshr_misses::total 12361 # number of LoadLockedReq MSHR misses
+system.cpu.dcache.StoreCondReq_mshr_misses::cpu.data 13 # number of StoreCondReq MSHR misses
+system.cpu.dcache.StoreCondReq_mshr_misses::total 13 # number of StoreCondReq MSHR misses
+system.cpu.dcache.demand_mshr_misses::cpu.data 637394 # number of demand (read+write) MSHR misses
+system.cpu.dcache.demand_mshr_misses::total 637394 # number of demand (read+write) MSHR misses
+system.cpu.dcache.overall_mshr_misses::cpu.data 637394 # number of overall MSHR misses
+system.cpu.dcache.overall_mshr_misses::total 637394 # number of overall MSHR misses
+system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 5287973500 # number of ReadReq MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_latency::total 5287973500 # number of ReadReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 8908906437 # number of WriteReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::total 8908906437 # number of WriteReq MSHR miss cycles
+system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data 165672500 # number of LoadLockedReq MSHR miss cycles
+system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 165672500 # number of LoadLockedReq MSHR miss cycles
+system.cpu.dcache.StoreCondReq_mshr_miss_latency::cpu.data 351500 # number of StoreCondReq MSHR miss cycles
+system.cpu.dcache.StoreCondReq_mshr_miss_latency::total 351500 # number of StoreCondReq MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::cpu.data 14196879937 # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::total 14196879937 # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::cpu.data 14196879937 # number of overall MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::total 14196879937 # number of overall MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 147151877500 # number of ReadReq MSHR uncacheable cycles
+system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 147151877500 # number of ReadReq MSHR uncacheable cycles
+system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data 42255772015 # number of WriteReq MSHR uncacheable cycles
+system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total 42255772015 # number of WriteReq MSHR uncacheable cycles
+system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 189407649515 # number of overall MSHR uncacheable cycles
+system.cpu.dcache.overall_mshr_uncacheable_latency::total 189407649515 # number of overall MSHR uncacheable cycles
+system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.025927 # mshr miss rate for ReadReq accesses
+system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.024333 # mshr miss rate for WriteReq accesses
+system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.041225 # mshr miss rate for LoadLockedReq accesses
+system.cpu.dcache.StoreCondReq_mshr_miss_rate::cpu.data 0.000046 # mshr miss rate for StoreCondReq accesses
+system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.025279 # mshr miss rate for demand accesses
+system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.025279 # mshr miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 13629.886666 # average ReadReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 35717.776634 # average WriteReq mshr miss latency
+system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 13402.839576 # average LoadLockedReq mshr miss latency
+system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::cpu.data 27038.461538 # average StoreCondReq mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 22273.319073 # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 22273.319073 # average overall mshr miss latency
system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency
system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu.data inf # average WriteReq mshr uncacheable latency
system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data inf # average overall mshr uncacheable latency
system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.iocache.fast_writes 0 # number of fast writes performed
system.iocache.cache_copies 0 # number of cache copies performed
-system.iocache.ReadReq_mshr_uncacheable_latency::realview.clcd 1296055922339 # number of ReadReq MSHR uncacheable cycles
-system.iocache.ReadReq_mshr_uncacheable_latency::total 1296055922339 # number of ReadReq MSHR uncacheable cycles
-system.iocache.overall_mshr_uncacheable_latency::realview.clcd 1296055922339 # number of overall MSHR uncacheable cycles
-system.iocache.overall_mshr_uncacheable_latency::total 1296055922339 # number of overall MSHR uncacheable cycles
+system.iocache.ReadReq_mshr_uncacheable_latency::realview.clcd 1296131413558 # number of ReadReq MSHR uncacheable cycles
+system.iocache.ReadReq_mshr_uncacheable_latency::total 1296131413558 # number of ReadReq MSHR uncacheable cycles
+system.iocache.overall_mshr_uncacheable_latency::realview.clcd 1296131413558 # number of overall MSHR uncacheable cycles
+system.iocache.overall_mshr_uncacheable_latency::total 1296131413558 # number of overall MSHR uncacheable cycles
system.iocache.ReadReq_avg_mshr_uncacheable_latency::realview.clcd inf # average ReadReq mshr uncacheable latency
system.iocache.overall_avg_mshr_uncacheable_latency::realview.clcd inf # average overall mshr uncacheable latency
system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.kern.inst.arm 0 # number of arm instructions executed
-system.cpu.kern.inst.quiesce 87985 # number of quiesce instructions executed
+system.cpu.kern.inst.quiesce 88053 # number of quiesce instructions executed
---------- End Simulation Statistics ----------
warn: instruction 'mcr bpiallis' unimplemented
warn: LCD dual screen mode not supported
warn: Returning thumbEE disabled for now since we don't support CP14config registers and jumping to ThumbEE vectors
-warn: Returning thumbEE disabled for now since we don't support CP14config registers and jumping to ThumbEE vectors
warn: instruction 'mcr icialluis' unimplemented
warn: instruction 'mcr icialluis' unimplemented
hack: be nice to actually delete the event here
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
-gem5 compiled May 8 2012 15:17:37
-gem5 started May 8 2012 17:10:02
-gem5 executing on piton
+gem5 compiled May 10 2012 12:36:36
+gem5 started May 10 2012 12:41:59
+gem5 executing on u200540-lin
command line: build/ARM/gem5.opt -d build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview-o3-dual -re tests/run.py build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview-o3-dual
Global frequency set at 1000000000000 ticks per second
-info: kernel located at: /dist/m5/system/binaries/vmlinux.arm.smp.fb.2.6.38.8
+info: kernel located at: /projects/pd/randd/dist/binaries/vmlinux.arm.smp.fb.2.6.38.8
info: Using bootloader at address 0x80000000
info: Entering event queue @ 0. Starting simulation...
-Exiting @ tick 2570828403500 because m5_exit instruction encountered
+Exiting @ tick 2570833934500 because m5_exit instruction encountered
---------- Begin Simulation Statistics ----------
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sim_freq 1000000000000 # Frequency of simulated ticks
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system.physmem.num_other 0 # Number of other requests responded to by this memory
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system.realview.nvmem.bytes_read 384 # Number of bytes read from this memory
system.realview.nvmem.bytes_inst_read 384 # Number of instructions bytes read from this memory
system.realview.nvmem.bytes_written 0 # Number of bytes written to this memory
system.realview.nvmem.bw_read 149 # Total read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_inst_read 149 # Instruction read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_total 149 # Total bandwidth to/from this memory (bytes/s)
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system.l2c.warmup_cycle 0 # Cycle when the warmup percentage was hit.
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+system.l2c.overall_mshr_miss_rate::cpu1.inst 0.014285 # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::cpu1.data 0.240798 # mshr miss rate for overall accesses
+system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.dtb.walker 40047.619048 # average ReadReq mshr miss latency
system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.itb.walker 40200 # average ReadReq mshr miss latency
-system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.inst 40077.729833 # average ReadReq mshr miss latency
-system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.data 40064.624304 # average ReadReq mshr miss latency
-system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 40045.454545 # average ReadReq mshr miss latency
+system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.inst 40079.003941 # average ReadReq mshr miss latency
+system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.data 40057.319023 # average ReadReq mshr miss latency
+system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 40065.573770 # average ReadReq mshr miss latency
system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.itb.walker 40000 # average ReadReq mshr miss latency
-system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.inst 40114.904988 # average ReadReq mshr miss latency
-system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.data 40060.229670 # average ReadReq mshr miss latency
-system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 40056.563292 # average UpgradeReq mshr miss latency
-system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 40023.122912 # average UpgradeReq mshr miss latency
-system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 40025.590551 # average SCUpgradeReq mshr miss latency
-system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 40061.769616 # average SCUpgradeReq mshr miss latency
-system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 40032.251925 # average ReadExReq mshr miss latency
-system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 40097.565610 # average ReadExReq mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu0.dtb.walker 40049.382716 # average overall mshr miss latency
+system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.inst 40122.729504 # average ReadReq mshr miss latency
+system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.data 40062.314308 # average ReadReq mshr miss latency
+system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 40062.103442 # average UpgradeReq mshr miss latency
+system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 40030.245747 # average UpgradeReq mshr miss latency
+system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 40043.147208 # average SCUpgradeReq mshr miss latency
+system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 40061.666667 # average SCUpgradeReq mshr miss latency
+system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 40033.493643 # average ReadExReq mshr miss latency
+system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 40096.958338 # average ReadExReq mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu0.dtb.walker 40047.619048 # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu0.itb.walker 40200 # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 40077.729833 # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu0.data 40036.067405 # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu1.dtb.walker 40045.454545 # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 40079.003941 # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu0.data 40036.288257 # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu1.dtb.walker 40065.573770 # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu1.itb.walker 40000 # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 40114.904988 # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu1.data 40092.501748 # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu0.dtb.walker 40049.382716 # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 40122.729504 # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu1.data 40092.265656 # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu0.dtb.walker 40047.619048 # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu0.itb.walker 40200 # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 40077.729833 # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu0.data 40036.067405 # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu1.dtb.walker 40045.454545 # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 40079.003941 # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu0.data 40036.288257 # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu1.dtb.walker 40065.573770 # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu1.itb.walker 40000 # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 40114.904988 # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu1.data 40092.501748 # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 40122.729504 # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu1.data 40092.265656 # average overall mshr miss latency
system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst inf # average ReadReq mshr uncacheable latency
system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data inf # average ReadReq mshr uncacheable latency
system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst inf # average ReadReq mshr uncacheable latency
system.cf0.dma_write_txs 0 # Number of DMA write transactions.
system.cpu0.dtb.inst_hits 0 # ITB inst hits
system.cpu0.dtb.inst_misses 0 # ITB inst misses
-system.cpu0.dtb.read_hits 7527759 # DTB read hits
-system.cpu0.dtb.read_misses 31435 # DTB read misses
-system.cpu0.dtb.write_hits 4435696 # DTB write hits
-system.cpu0.dtb.write_misses 6033 # DTB write misses
+system.cpu0.dtb.read_hits 7530160 # DTB read hits
+system.cpu0.dtb.read_misses 32787 # DTB read misses
+system.cpu0.dtb.write_hits 4446652 # DTB write hits
+system.cpu0.dtb.write_misses 6213 # DTB write misses
system.cpu0.dtb.flush_tlb 4 # Number of times complete TLB was flushed
system.cpu0.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
system.cpu0.dtb.flush_tlb_mva_asid 1439 # Number of times TLB was flushed by MVA & ASID
system.cpu0.dtb.flush_tlb_asid 63 # Number of times TLB was flushed by ASID
-system.cpu0.dtb.flush_entries 2072 # Number of entries that have been flushed from TLB
-system.cpu0.dtb.align_faults 4328 # Number of TLB faults due to alignment restrictions
-system.cpu0.dtb.prefetch_faults 228 # Number of TLB faults due to prefetch
+system.cpu0.dtb.flush_entries 2035 # Number of entries that have been flushed from TLB
+system.cpu0.dtb.align_faults 4401 # Number of TLB faults due to alignment restrictions
+system.cpu0.dtb.prefetch_faults 226 # Number of TLB faults due to prefetch
system.cpu0.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions
-system.cpu0.dtb.perms_faults 803 # Number of TLB faults due to permissions restrictions
-system.cpu0.dtb.read_accesses 7559194 # DTB read accesses
-system.cpu0.dtb.write_accesses 4441729 # DTB write accesses
+system.cpu0.dtb.perms_faults 789 # Number of TLB faults due to permissions restrictions
+system.cpu0.dtb.read_accesses 7562947 # DTB read accesses
+system.cpu0.dtb.write_accesses 4452865 # DTB write accesses
system.cpu0.dtb.inst_accesses 0 # ITB inst accesses
-system.cpu0.dtb.hits 11963455 # DTB hits
-system.cpu0.dtb.misses 37468 # DTB misses
-system.cpu0.dtb.accesses 12000923 # DTB accesses
-system.cpu0.itb.inst_hits 3809486 # ITB inst hits
-system.cpu0.itb.inst_misses 6280 # ITB inst misses
+system.cpu0.dtb.hits 11976812 # DTB hits
+system.cpu0.dtb.misses 39000 # DTB misses
+system.cpu0.dtb.accesses 12015812 # DTB accesses
+system.cpu0.itb.inst_hits 3834120 # ITB inst hits
+system.cpu0.itb.inst_misses 4594 # ITB inst misses
system.cpu0.itb.read_hits 0 # DTB read hits
system.cpu0.itb.read_misses 0 # DTB read misses
system.cpu0.itb.write_hits 0 # DTB write hits
system.cpu0.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
system.cpu0.itb.flush_tlb_mva_asid 1439 # Number of times TLB was flushed by MVA & ASID
system.cpu0.itb.flush_tlb_asid 63 # Number of times TLB was flushed by ASID
-system.cpu0.itb.flush_entries 1380 # Number of entries that have been flushed from TLB
+system.cpu0.itb.flush_entries 1377 # Number of entries that have been flushed from TLB
system.cpu0.itb.align_faults 0 # Number of TLB faults due to alignment restrictions
system.cpu0.itb.prefetch_faults 0 # Number of TLB faults due to prefetch
system.cpu0.itb.domain_faults 0 # Number of TLB faults due to domain restrictions
-system.cpu0.itb.perms_faults 1824 # Number of TLB faults due to permissions restrictions
+system.cpu0.itb.perms_faults 1800 # Number of TLB faults due to permissions restrictions
system.cpu0.itb.read_accesses 0 # DTB read accesses
system.cpu0.itb.write_accesses 0 # DTB write accesses
-system.cpu0.itb.inst_accesses 3815766 # ITB inst accesses
-system.cpu0.itb.hits 3809486 # DTB hits
-system.cpu0.itb.misses 6280 # DTB misses
-system.cpu0.itb.accesses 3815766 # DTB accesses
-system.cpu0.numCycles 55441069 # number of cpu cycles simulated
+system.cpu0.itb.inst_accesses 3838714 # ITB inst accesses
+system.cpu0.itb.hits 3834120 # DTB hits
+system.cpu0.itb.misses 4594 # DTB misses
+system.cpu0.itb.accesses 3838714 # DTB accesses
+system.cpu0.numCycles 55537360 # number of cpu cycles simulated
system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed
-system.cpu0.BPredUnit.lookups 5212892 # Number of BP lookups
-system.cpu0.BPredUnit.condPredicted 3951494 # Number of conditional branches predicted
-system.cpu0.BPredUnit.condIncorrect 295394 # Number of conditional branches incorrect
-system.cpu0.BPredUnit.BTBLookups 3415998 # Number of BTB lookups
-system.cpu0.BPredUnit.BTBHits 2549557 # Number of BTB hits
+system.cpu0.BPredUnit.lookups 5204671 # Number of BP lookups
+system.cpu0.BPredUnit.condPredicted 3944570 # Number of conditional branches predicted
+system.cpu0.BPredUnit.condIncorrect 296840 # Number of conditional branches incorrect
+system.cpu0.BPredUnit.BTBLookups 3413720 # Number of BTB lookups
+system.cpu0.BPredUnit.BTBHits 2557176 # Number of BTB hits
system.cpu0.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
-system.cpu0.BPredUnit.usedRAS 460779 # Number of times the RAS was used to get a target.
-system.cpu0.BPredUnit.RASInCorrect 62243 # Number of incorrect RAS predictions.
-system.cpu0.fetch.icacheStallCycles 10453565 # Number of cycles fetch is stalled on an Icache miss
-system.cpu0.fetch.Insts 27421447 # Number of instructions fetch has processed
-system.cpu0.fetch.Branches 5212892 # Number of branches that fetch encountered
-system.cpu0.fetch.predictedBranches 3010336 # Number of branches that fetch has predicted taken
-system.cpu0.fetch.Cycles 6440117 # Number of cycles fetch has run and was not squashing or blocked
-system.cpu0.fetch.SquashCycles 1388454 # Number of cycles fetch has spent squashing
-system.cpu0.fetch.TlbCycles 65669 # Number of cycles fetch has spent waiting for tlb
-system.cpu0.fetch.BlockedCycles 17512846 # Number of cycles fetch has spent blocked
-system.cpu0.fetch.MiscStallCycles 6544 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
-system.cpu0.fetch.PendingTrapStallCycles 31892 # Number of stall cycles due to pending traps
-system.cpu0.fetch.PendingQuiesceStallCycles 74131 # Number of stall cycles due to pending quiesce instructions
-system.cpu0.fetch.IcacheWaitRetryStallCycles 256 # Number of stall cycles due to full MSHR
-system.cpu0.fetch.CacheLines 3807333 # Number of cache lines fetched
-system.cpu0.fetch.IcacheSquashes 161414 # Number of outstanding Icache misses that were squashed
-system.cpu0.fetch.ItlbSquashes 4002 # Number of outstanding ITLB misses that were squashed
-system.cpu0.fetch.rateDist::samples 35574590 # Number of instructions fetched each cycle (Total)
-system.cpu0.fetch.rateDist::mean 1.004938 # Number of instructions fetched each cycle (Total)
-system.cpu0.fetch.rateDist::stdev 2.398361 # Number of instructions fetched each cycle (Total)
+system.cpu0.BPredUnit.usedRAS 459948 # Number of times the RAS was used to get a target.
+system.cpu0.BPredUnit.RASInCorrect 62294 # Number of incorrect RAS predictions.
+system.cpu0.fetch.icacheStallCycles 10542481 # Number of cycles fetch is stalled on an Icache miss
+system.cpu0.fetch.Insts 27454720 # Number of instructions fetch has processed
+system.cpu0.fetch.Branches 5204671 # Number of branches that fetch encountered
+system.cpu0.fetch.predictedBranches 3017124 # Number of branches that fetch has predicted taken
+system.cpu0.fetch.Cycles 6462624 # Number of cycles fetch has run and was not squashing or blocked
+system.cpu0.fetch.SquashCycles 1388283 # Number of cycles fetch has spent squashing
+system.cpu0.fetch.TlbCycles 64249 # Number of cycles fetch has spent waiting for tlb
+system.cpu0.fetch.BlockedCycles 17511747 # Number of cycles fetch has spent blocked
+system.cpu0.fetch.MiscStallCycles 6585 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
+system.cpu0.fetch.PendingTrapStallCycles 32170 # Number of stall cycles due to pending traps
+system.cpu0.fetch.PendingQuiesceStallCycles 74952 # Number of stall cycles due to pending quiesce instructions
+system.cpu0.fetch.IcacheWaitRetryStallCycles 276 # Number of stall cycles due to full MSHR
+system.cpu0.fetch.CacheLines 3831976 # Number of cache lines fetched
+system.cpu0.fetch.IcacheSquashes 163321 # Number of outstanding Icache misses that were squashed
+system.cpu0.fetch.ItlbSquashes 3020 # Number of outstanding ITLB misses that were squashed
+system.cpu0.fetch.rateDist::samples 35682594 # Number of instructions fetched each cycle (Total)
+system.cpu0.fetch.rateDist::mean 1.003010 # Number of instructions fetched each cycle (Total)
+system.cpu0.fetch.rateDist::stdev 2.394306 # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)
-system.cpu0.fetch.rateDist::0 29140690 81.91% 81.91% # Number of instructions fetched each cycle (Total)
-system.cpu0.fetch.rateDist::1 530074 1.49% 83.40% # Number of instructions fetched each cycle (Total)
-system.cpu0.fetch.rateDist::2 686036 1.93% 85.33% # Number of instructions fetched each cycle (Total)
-system.cpu0.fetch.rateDist::3 575113 1.62% 86.95% # Number of instructions fetched each cycle (Total)
-system.cpu0.fetch.rateDist::4 516761 1.45% 88.40% # Number of instructions fetched each cycle (Total)
-system.cpu0.fetch.rateDist::5 484002 1.36% 89.76% # Number of instructions fetched each cycle (Total)
-system.cpu0.fetch.rateDist::6 574923 1.62% 91.38% # Number of instructions fetched each cycle (Total)
-system.cpu0.fetch.rateDist::7 349762 0.98% 92.36% # Number of instructions fetched each cycle (Total)
-system.cpu0.fetch.rateDist::8 2717229 7.64% 100.00% # Number of instructions fetched each cycle (Total)
+system.cpu0.fetch.rateDist::0 29226357 81.91% 81.91% # Number of instructions fetched each cycle (Total)
+system.cpu0.fetch.rateDist::1 522599 1.46% 83.37% # Number of instructions fetched each cycle (Total)
+system.cpu0.fetch.rateDist::2 706764 1.98% 85.35% # Number of instructions fetched each cycle (Total)
+system.cpu0.fetch.rateDist::3 578503 1.62% 86.97% # Number of instructions fetched each cycle (Total)
+system.cpu0.fetch.rateDist::4 534782 1.50% 88.47% # Number of instructions fetched each cycle (Total)
+system.cpu0.fetch.rateDist::5 477839 1.34% 89.81% # Number of instructions fetched each cycle (Total)
+system.cpu0.fetch.rateDist::6 574033 1.61% 91.42% # Number of instructions fetched each cycle (Total)
+system.cpu0.fetch.rateDist::7 347894 0.97% 92.39% # Number of instructions fetched each cycle (Total)
+system.cpu0.fetch.rateDist::8 2713823 7.61% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total)
-system.cpu0.fetch.rateDist::total 35574590 # Number of instructions fetched each cycle (Total)
-system.cpu0.fetch.branchRate 0.094026 # Number of branch fetches per cycle
-system.cpu0.fetch.rate 0.494605 # Number of inst fetches per cycle
-system.cpu0.decode.IdleCycles 10814757 # Number of cycles decode is idle
-system.cpu0.decode.BlockedCycles 17563508 # Number of cycles decode is blocked
-system.cpu0.decode.RunCycles 5782354 # Number of cycles decode is running
-system.cpu0.decode.UnblockCycles 479006 # Number of cycles decode is unblocking
-system.cpu0.decode.SquashCycles 934965 # Number of cycles decode is squashing
-system.cpu0.decode.BranchResolved 835529 # Number of times decode resolved a branch
-system.cpu0.decode.BranchMispred 55823 # Number of times decode detected a branch misprediction
-system.cpu0.decode.DecodedInsts 34470555 # Number of instructions handled by decode
-system.cpu0.decode.SquashedInsts 179479 # Number of squashed instructions handled by decode
-system.cpu0.rename.SquashCycles 934965 # Number of cycles rename is squashing
-system.cpu0.rename.IdleCycles 11326555 # Number of cycles rename is idle
-system.cpu0.rename.BlockCycles 4595002 # Number of cycles rename is blocking
-system.cpu0.rename.serializeStallCycles 11316835 # count of cycles rename stalled for serializing inst
-system.cpu0.rename.RunCycles 5729017 # Number of cycles rename is running
-system.cpu0.rename.UnblockCycles 1672216 # Number of cycles rename is unblocking
-system.cpu0.rename.RenamedInsts 33303546 # Number of instructions processed by rename
-system.cpu0.rename.ROBFullEvents 955 # Number of times rename has blocked due to ROB full
-system.cpu0.rename.IQFullEvents 363738 # Number of times rename has blocked due to IQ full
-system.cpu0.rename.LSQFullEvents 882856 # Number of times rename has blocked due to LSQ full
-system.cpu0.rename.FullRegisterEvents 34 # Number of times there has been no free registers
-system.cpu0.rename.RenamedOperands 33389165 # Number of destination operands rename has renamed
-system.cpu0.rename.RenameLookups 151283000 # Number of register rename lookups that rename has made
-system.cpu0.rename.int_rename_lookups 151242578 # Number of integer rename lookups
-system.cpu0.rename.fp_rename_lookups 40422 # Number of floating rename lookups
-system.cpu0.rename.CommittedMaps 25698465 # Number of HB maps that are committed
-system.cpu0.rename.UndoneMaps 7690700 # Number of HB maps that are undone due to squashing
-system.cpu0.rename.serializingInsts 390539 # count of serializing insts renamed
-system.cpu0.rename.tempSerializingInsts 354252 # count of temporary serializing insts renamed
-system.cpu0.rename.skidInsts 4298434 # count of insts added to the skid buffer
-system.cpu0.memDep0.insertedLoads 6455423 # Number of loads inserted to the mem dependence unit.
-system.cpu0.memDep0.insertedStores 4976732 # Number of stores inserted to the mem dependence unit.
-system.cpu0.memDep0.conflictingLoads 849969 # Number of conflicting loads.
-system.cpu0.memDep0.conflictingStores 853540 # Number of conflicting stores.
-system.cpu0.iq.iqInstsAdded 31433505 # Number of instructions added to the IQ (excludes non-spec)
-system.cpu0.iq.iqNonSpecInstsAdded 659467 # Number of non-speculative instructions added to the IQ
-system.cpu0.iq.iqInstsIssued 31580110 # Number of instructions issued
-system.cpu0.iq.iqSquashedInstsIssued 81056 # Number of squashed instructions issued
-system.cpu0.iq.iqSquashedInstsExamined 5706071 # Number of squashed instructions iterated over during squash; mainly for profiling
-system.cpu0.iq.iqSquashedOperandsExamined 12925708 # Number of squashed operands that are examined and possibly removed from graph
-system.cpu0.iq.iqSquashedNonSpecRemoved 117932 # Number of squashed non-spec instructions that were removed
-system.cpu0.iq.issued_per_cycle::samples 35574590 # Number of insts issued each cycle
-system.cpu0.iq.issued_per_cycle::mean 0.887715 # Number of insts issued each cycle
-system.cpu0.iq.issued_per_cycle::stdev 1.519071 # Number of insts issued each cycle
+system.cpu0.fetch.rateDist::total 35682594 # Number of instructions fetched each cycle (Total)
+system.cpu0.fetch.branchRate 0.093715 # Number of branch fetches per cycle
+system.cpu0.fetch.rate 0.494347 # Number of inst fetches per cycle
+system.cpu0.decode.IdleCycles 10901751 # Number of cycles decode is idle
+system.cpu0.decode.BlockedCycles 17564449 # Number of cycles decode is blocked
+system.cpu0.decode.RunCycles 5807943 # Number of cycles decode is running
+system.cpu0.decode.UnblockCycles 476099 # Number of cycles decode is unblocking
+system.cpu0.decode.SquashCycles 932352 # Number of cycles decode is squashing
+system.cpu0.decode.BranchResolved 836954 # Number of times decode resolved a branch
+system.cpu0.decode.BranchMispred 56324 # Number of times decode detected a branch misprediction
+system.cpu0.decode.DecodedInsts 34505102 # Number of instructions handled by decode
+system.cpu0.decode.SquashedInsts 181228 # Number of squashed instructions handled by decode
+system.cpu0.rename.SquashCycles 932352 # Number of cycles rename is squashing
+system.cpu0.rename.IdleCycles 11416627 # Number of cycles rename is idle
+system.cpu0.rename.BlockCycles 4596309 # Number of cycles rename is blocking
+system.cpu0.rename.serializeStallCycles 11321409 # count of cycles rename stalled for serializing inst
+system.cpu0.rename.RunCycles 5748941 # Number of cycles rename is running
+system.cpu0.rename.UnblockCycles 1666956 # Number of cycles rename is unblocking
+system.cpu0.rename.RenamedInsts 33335658 # Number of instructions processed by rename
+system.cpu0.rename.ROBFullEvents 999 # Number of times rename has blocked due to ROB full
+system.cpu0.rename.IQFullEvents 358087 # Number of times rename has blocked due to IQ full
+system.cpu0.rename.LSQFullEvents 883877 # Number of times rename has blocked due to LSQ full
+system.cpu0.rename.FullRegisterEvents 110 # Number of times there has been no free registers
+system.cpu0.rename.RenamedOperands 33439844 # Number of destination operands rename has renamed
+system.cpu0.rename.RenameLookups 151572898 # Number of register rename lookups that rename has made
+system.cpu0.rename.int_rename_lookups 151532196 # Number of integer rename lookups
+system.cpu0.rename.fp_rename_lookups 40702 # Number of floating rename lookups
+system.cpu0.rename.CommittedMaps 25794881 # Number of HB maps that are committed
+system.cpu0.rename.UndoneMaps 7644963 # Number of HB maps that are undone due to squashing
+system.cpu0.rename.serializingInsts 390853 # count of serializing insts renamed
+system.cpu0.rename.tempSerializingInsts 354451 # count of temporary serializing insts renamed
+system.cpu0.rename.skidInsts 4284069 # count of insts added to the skid buffer
+system.cpu0.memDep0.insertedLoads 6465672 # Number of loads inserted to the mem dependence unit.
+system.cpu0.memDep0.insertedStores 4994701 # Number of stores inserted to the mem dependence unit.
+system.cpu0.memDep0.conflictingLoads 841470 # Number of conflicting loads.
+system.cpu0.memDep0.conflictingStores 890235 # Number of conflicting stores.
+system.cpu0.iq.iqInstsAdded 31482040 # Number of instructions added to the IQ (excludes non-spec)
+system.cpu0.iq.iqNonSpecInstsAdded 658671 # Number of non-speculative instructions added to the IQ
+system.cpu0.iq.iqInstsIssued 31606585 # Number of instructions issued
+system.cpu0.iq.iqSquashedInstsIssued 78774 # Number of squashed instructions issued
+system.cpu0.iq.iqSquashedInstsExamined 5676384 # Number of squashed instructions iterated over during squash; mainly for profiling
+system.cpu0.iq.iqSquashedOperandsExamined 13082280 # Number of squashed operands that are examined and possibly removed from graph
+system.cpu0.iq.iqSquashedNonSpecRemoved 117406 # Number of squashed non-spec instructions that were removed
+system.cpu0.iq.issued_per_cycle::samples 35682594 # Number of insts issued each cycle
+system.cpu0.iq.issued_per_cycle::mean 0.885770 # Number of insts issued each cycle
+system.cpu0.iq.issued_per_cycle::stdev 1.514582 # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
-system.cpu0.iq.issued_per_cycle::0 22796169 64.08% 64.08% # Number of insts issued each cycle
-system.cpu0.iq.issued_per_cycle::1 4955890 13.93% 78.01% # Number of insts issued each cycle
-system.cpu0.iq.issued_per_cycle::2 2593205 7.29% 85.30% # Number of insts issued each cycle
-system.cpu0.iq.issued_per_cycle::3 1941493 5.46% 90.76% # Number of insts issued each cycle
-system.cpu0.iq.issued_per_cycle::4 1799462 5.06% 95.82% # Number of insts issued each cycle
-system.cpu0.iq.issued_per_cycle::5 771833 2.17% 97.99% # Number of insts issued each cycle
-system.cpu0.iq.issued_per_cycle::6 508602 1.43% 99.42% # Number of insts issued each cycle
-system.cpu0.iq.issued_per_cycle::7 158782 0.45% 99.86% # Number of insts issued each cycle
-system.cpu0.iq.issued_per_cycle::8 49154 0.14% 100.00% # Number of insts issued each cycle
+system.cpu0.iq.issued_per_cycle::0 22866556 64.08% 64.08% # Number of insts issued each cycle
+system.cpu0.iq.issued_per_cycle::1 4972769 13.94% 78.02% # Number of insts issued each cycle
+system.cpu0.iq.issued_per_cycle::2 2602679 7.29% 85.31% # Number of insts issued each cycle
+system.cpu0.iq.issued_per_cycle::3 1960706 5.49% 90.81% # Number of insts issued each cycle
+system.cpu0.iq.issued_per_cycle::4 1807368 5.07% 95.87% # Number of insts issued each cycle
+system.cpu0.iq.issued_per_cycle::5 768762 2.15% 98.03% # Number of insts issued each cycle
+system.cpu0.iq.issued_per_cycle::6 499053 1.40% 99.43% # Number of insts issued each cycle
+system.cpu0.iq.issued_per_cycle::7 158868 0.45% 99.87% # Number of insts issued each cycle
+system.cpu0.iq.issued_per_cycle::8 45833 0.13% 100.00% # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle
-system.cpu0.iq.issued_per_cycle::total 35574590 # Number of insts issued each cycle
+system.cpu0.iq.issued_per_cycle::total 35682594 # Number of insts issued each cycle
system.cpu0.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available
-system.cpu0.iq.fu_full::IntAlu 35384 3.74% 3.74% # attempts to use FU when none available
-system.cpu0.iq.fu_full::IntMult 453 0.05% 3.79% # attempts to use FU when none available
-system.cpu0.iq.fu_full::IntDiv 0 0.00% 3.79% # attempts to use FU when none available
-system.cpu0.iq.fu_full::FloatAdd 0 0.00% 3.79% # attempts to use FU when none available
-system.cpu0.iq.fu_full::FloatCmp 0 0.00% 3.79% # attempts to use FU when none available
-system.cpu0.iq.fu_full::FloatCvt 0 0.00% 3.79% # attempts to use FU when none available
-system.cpu0.iq.fu_full::FloatMult 0 0.00% 3.79% # attempts to use FU when none available
-system.cpu0.iq.fu_full::FloatDiv 0 0.00% 3.79% # attempts to use FU when none available
-system.cpu0.iq.fu_full::FloatSqrt 0 0.00% 3.79% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdAdd 0 0.00% 3.79% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdAddAcc 0 0.00% 3.79% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdAlu 0 0.00% 3.79% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdCmp 0 0.00% 3.79% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdCvt 0 0.00% 3.79% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdMisc 0 0.00% 3.79% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdMult 0 0.00% 3.79% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdMultAcc 0 0.00% 3.79% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdShift 0 0.00% 3.79% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdShiftAcc 0 0.00% 3.79% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdSqrt 0 0.00% 3.79% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdFloatAdd 0 0.00% 3.79% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdFloatAlu 0 0.00% 3.79% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdFloatCmp 0 0.00% 3.79% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdFloatCvt 0 0.00% 3.79% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdFloatDiv 0 0.00% 3.79% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdFloatMisc 0 0.00% 3.79% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdFloatMult 0 0.00% 3.79% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdFloatMultAcc 0 0.00% 3.79% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdFloatSqrt 0 0.00% 3.79% # attempts to use FU when none available
-system.cpu0.iq.fu_full::MemRead 728574 76.99% 80.78% # attempts to use FU when none available
-system.cpu0.iq.fu_full::MemWrite 181906 19.22% 100.00% # attempts to use FU when none available
+system.cpu0.iq.fu_full::IntAlu 26479 2.83% 2.83% # attempts to use FU when none available
+system.cpu0.iq.fu_full::IntMult 454 0.05% 2.88% # attempts to use FU when none available
+system.cpu0.iq.fu_full::IntDiv 0 0.00% 2.88% # attempts to use FU when none available
+system.cpu0.iq.fu_full::FloatAdd 0 0.00% 2.88% # attempts to use FU when none available
+system.cpu0.iq.fu_full::FloatCmp 0 0.00% 2.88% # attempts to use FU when none available
+system.cpu0.iq.fu_full::FloatCvt 0 0.00% 2.88% # attempts to use FU when none available
+system.cpu0.iq.fu_full::FloatMult 0 0.00% 2.88% # attempts to use FU when none available
+system.cpu0.iq.fu_full::FloatDiv 0 0.00% 2.88% # attempts to use FU when none available
+system.cpu0.iq.fu_full::FloatSqrt 0 0.00% 2.88% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdAdd 0 0.00% 2.88% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdAddAcc 0 0.00% 2.88% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdAlu 0 0.00% 2.88% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdCmp 0 0.00% 2.88% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdCvt 0 0.00% 2.88% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdMisc 0 0.00% 2.88% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdMult 0 0.00% 2.88% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdMultAcc 0 0.00% 2.88% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdShift 0 0.00% 2.88% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdShiftAcc 0 0.00% 2.88% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdSqrt 0 0.00% 2.88% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdFloatAdd 0 0.00% 2.88% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdFloatAlu 0 0.00% 2.88% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdFloatCmp 0 0.00% 2.88% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdFloatCvt 0 0.00% 2.88% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdFloatDiv 0 0.00% 2.88% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdFloatMisc 0 0.00% 2.88% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdFloatMult 0 0.00% 2.88% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdFloatMultAcc 0 0.00% 2.88% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdFloatSqrt 0 0.00% 2.88% # attempts to use FU when none available
+system.cpu0.iq.fu_full::MemRead 724595 77.49% 80.37% # attempts to use FU when none available
+system.cpu0.iq.fu_full::MemWrite 183504 19.63% 100.00% # attempts to use FU when none available
system.cpu0.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
system.cpu0.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available
system.cpu0.iq.FU_type_0::No_OpClass 14281 0.05% 0.05% # Type of FU issued
-system.cpu0.iq.FU_type_0::IntAlu 18843805 59.67% 59.72% # Type of FU issued
-system.cpu0.iq.FU_type_0::IntMult 42255 0.13% 59.85% # Type of FU issued
-system.cpu0.iq.FU_type_0::IntDiv 0 0.00% 59.85% # Type of FU issued
-system.cpu0.iq.FU_type_0::FloatAdd 0 0.00% 59.85% # Type of FU issued
-system.cpu0.iq.FU_type_0::FloatCmp 0 0.00% 59.85% # Type of FU issued
-system.cpu0.iq.FU_type_0::FloatCvt 0 0.00% 59.85% # Type of FU issued
-system.cpu0.iq.FU_type_0::FloatMult 0 0.00% 59.85% # Type of FU issued
-system.cpu0.iq.FU_type_0::FloatDiv 0 0.00% 59.85% # Type of FU issued
-system.cpu0.iq.FU_type_0::FloatSqrt 0 0.00% 59.85% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdAdd 0 0.00% 59.85% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdAddAcc 0 0.00% 59.85% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdAlu 0 0.00% 59.85% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdCmp 0 0.00% 59.85% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdCvt 0 0.00% 59.85% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdMisc 10 0.00% 59.85% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdMult 0 0.00% 59.85% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdMultAcc 0 0.00% 59.85% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdShift 7 0.00% 59.85% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdShiftAcc 5 0.00% 59.85% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdSqrt 0 0.00% 59.85% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdFloatAdd 0 0.00% 59.85% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdFloatAlu 0 0.00% 59.85% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdFloatCmp 0 0.00% 59.85% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdFloatCvt 0 0.00% 59.85% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdFloatDiv 0 0.00% 59.85% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdFloatMisc 650 0.00% 59.85% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdFloatMult 0 0.00% 59.85% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdFloatMultAcc 5 0.00% 59.85% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdFloatSqrt 0 0.00% 59.85% # Type of FU issued
-system.cpu0.iq.FU_type_0::MemRead 7938571 25.14% 84.99% # Type of FU issued
-system.cpu0.iq.FU_type_0::MemWrite 4740521 15.01% 100.00% # Type of FU issued
+system.cpu0.iq.FU_type_0::IntAlu 18849345 59.64% 59.68% # Type of FU issued
+system.cpu0.iq.FU_type_0::IntMult 42325 0.13% 59.82% # Type of FU issued
+system.cpu0.iq.FU_type_0::IntDiv 0 0.00% 59.82% # Type of FU issued
+system.cpu0.iq.FU_type_0::FloatAdd 0 0.00% 59.82% # Type of FU issued
+system.cpu0.iq.FU_type_0::FloatCmp 0 0.00% 59.82% # Type of FU issued
+system.cpu0.iq.FU_type_0::FloatCvt 0 0.00% 59.82% # Type of FU issued
+system.cpu0.iq.FU_type_0::FloatMult 0 0.00% 59.82% # Type of FU issued
+system.cpu0.iq.FU_type_0::FloatDiv 0 0.00% 59.82% # Type of FU issued
+system.cpu0.iq.FU_type_0::FloatSqrt 0 0.00% 59.82% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdAdd 0 0.00% 59.82% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdAddAcc 0 0.00% 59.82% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdAlu 0 0.00% 59.82% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdCmp 0 0.00% 59.82% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdCvt 0 0.00% 59.82% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdMisc 8 0.00% 59.82% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdMult 0 0.00% 59.82% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdMultAcc 0 0.00% 59.82% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdShift 8 0.00% 59.82% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdShiftAcc 3 0.00% 59.82% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdSqrt 0 0.00% 59.82% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdFloatAdd 0 0.00% 59.82% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdFloatAlu 0 0.00% 59.82% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdFloatCmp 0 0.00% 59.82% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdFloatCvt 0 0.00% 59.82% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdFloatDiv 0 0.00% 59.82% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdFloatMisc 650 0.00% 59.82% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdFloatMult 0 0.00% 59.82% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdFloatMultAcc 3 0.00% 59.82% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdFloatSqrt 0 0.00% 59.82% # Type of FU issued
+system.cpu0.iq.FU_type_0::MemRead 7946092 25.14% 84.96% # Type of FU issued
+system.cpu0.iq.FU_type_0::MemWrite 4753870 15.04% 100.00% # Type of FU issued
system.cpu0.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued
system.cpu0.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued
-system.cpu0.iq.FU_type_0::total 31580110 # Type of FU issued
-system.cpu0.iq.rate 0.569616 # Inst issue rate
-system.cpu0.iq.fu_busy_cnt 946317 # FU busy when requested
-system.cpu0.iq.fu_busy_rate 0.029966 # FU busy rate (busy events/executed inst)
-system.cpu0.iq.int_inst_queue_reads 99788129 # Number of integer instruction queue reads
-system.cpu0.iq.int_inst_queue_writes 37802639 # Number of integer instruction queue writes
-system.cpu0.iq.int_inst_queue_wakeup_accesses 28957807 # Number of integer instruction queue wakeup accesses
-system.cpu0.iq.fp_inst_queue_reads 10678 # Number of floating instruction queue reads
-system.cpu0.iq.fp_inst_queue_writes 5536 # Number of floating instruction queue writes
-system.cpu0.iq.fp_inst_queue_wakeup_accesses 4399 # Number of floating instruction queue wakeup accesses
-system.cpu0.iq.int_alu_accesses 32506335 # Number of integer alu accesses
-system.cpu0.iq.fp_alu_accesses 5811 # Number of floating point alu accesses
-system.cpu0.iew.lsq.thread0.forwLoads 253441 # Number of loads that had data forwarded from stores
+system.cpu0.iq.FU_type_0::total 31606585 # Type of FU issued
+system.cpu0.iq.rate 0.569105 # Inst issue rate
+system.cpu0.iq.fu_busy_cnt 935032 # FU busy when requested
+system.cpu0.iq.fu_busy_rate 0.029583 # FU busy rate (busy events/executed inst)
+system.cpu0.iq.int_inst_queue_reads 99937037 # Number of integer instruction queue reads
+system.cpu0.iq.int_inst_queue_writes 37821084 # Number of integer instruction queue writes
+system.cpu0.iq.int_inst_queue_wakeup_accesses 28987180 # Number of integer instruction queue wakeup accesses
+system.cpu0.iq.fp_inst_queue_reads 10596 # Number of floating instruction queue reads
+system.cpu0.iq.fp_inst_queue_writes 5532 # Number of floating instruction queue writes
+system.cpu0.iq.fp_inst_queue_wakeup_accesses 4395 # Number of floating instruction queue wakeup accesses
+system.cpu0.iq.int_alu_accesses 32521589 # Number of integer alu accesses
+system.cpu0.iq.fp_alu_accesses 5747 # Number of floating point alu accesses
+system.cpu0.iew.lsq.thread0.forwLoads 248744 # Number of loads that had data forwarded from stores
system.cpu0.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address
-system.cpu0.iew.lsq.thread0.squashedLoads 1254358 # Number of loads squashed
-system.cpu0.iew.lsq.thread0.ignoredResponses 3684 # Number of memory responses ignored because the instruction is squashed
-system.cpu0.iew.lsq.thread0.memOrderViolation 9621 # Number of memory ordering violations
-system.cpu0.iew.lsq.thread0.squashedStores 525059 # Number of stores squashed
+system.cpu0.iew.lsq.thread0.squashedLoads 1245744 # Number of loads squashed
+system.cpu0.iew.lsq.thread0.ignoredResponses 3732 # Number of memory responses ignored because the instruction is squashed
+system.cpu0.iew.lsq.thread0.memOrderViolation 10021 # Number of memory ordering violations
+system.cpu0.iew.lsq.thread0.squashedStores 530307 # Number of stores squashed
system.cpu0.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
system.cpu0.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
-system.cpu0.iew.lsq.thread0.rescheduledLoads 1901492 # Number of loads that were rescheduled
-system.cpu0.iew.lsq.thread0.cacheBlocked 5043 # Number of times an access to memory failed due to the cache being blocked
+system.cpu0.iew.lsq.thread0.rescheduledLoads 1901421 # Number of loads that were rescheduled
+system.cpu0.iew.lsq.thread0.cacheBlocked 5034 # Number of times an access to memory failed due to the cache being blocked
system.cpu0.iew.iewIdleCycles 0 # Number of cycles IEW is idle
-system.cpu0.iew.iewSquashCycles 934965 # Number of cycles IEW is squashing
-system.cpu0.iew.iewBlockCycles 3498549 # Number of cycles IEW is blocking
-system.cpu0.iew.iewUnblockCycles 78984 # Number of cycles IEW is unblocking
-system.cpu0.iew.iewDispatchedInsts 32152208 # Number of instructions dispatched to IQ
-system.cpu0.iew.iewDispSquashedInsts 119958 # Number of squashed instructions skipped by dispatch
-system.cpu0.iew.iewDispLoadInsts 6455423 # Number of dispatched load instructions
-system.cpu0.iew.iewDispStoreInsts 4976732 # Number of dispatched store instructions
-system.cpu0.iew.iewDispNonSpecInsts 398786 # Number of dispatched non-speculative instructions
-system.cpu0.iew.iewIQFullEvents 38665 # Number of times the IQ has become full, causing a stall
-system.cpu0.iew.iewLSQFullEvents 4398 # Number of times the LSQ has become full, causing a stall
-system.cpu0.iew.memOrderViolationEvents 9621 # Number of memory order violations
-system.cpu0.iew.predictedTakenIncorrect 177464 # Number of branches that were predicted taken incorrectly
-system.cpu0.iew.predictedNotTakenIncorrect 119524 # Number of branches that were predicted not taken incorrectly
-system.cpu0.iew.branchMispredicts 296988 # Number of branch mispredicts detected at execute
-system.cpu0.iew.iewExecutedInsts 31195619 # Number of executed instructions
-system.cpu0.iew.iewExecLoadInsts 7789216 # Number of load instructions executed
-system.cpu0.iew.iewExecSquashedInsts 384491 # Number of squashed instructions skipped in execute
+system.cpu0.iew.iewSquashCycles 932352 # Number of cycles IEW is squashing
+system.cpu0.iew.iewBlockCycles 3503280 # Number of cycles IEW is blocking
+system.cpu0.iew.iewUnblockCycles 78441 # Number of cycles IEW is unblocking
+system.cpu0.iew.iewDispatchedInsts 32200235 # Number of instructions dispatched to IQ
+system.cpu0.iew.iewDispSquashedInsts 121893 # Number of squashed instructions skipped by dispatch
+system.cpu0.iew.iewDispLoadInsts 6465672 # Number of dispatched load instructions
+system.cpu0.iew.iewDispStoreInsts 4994701 # Number of dispatched store instructions
+system.cpu0.iew.iewDispNonSpecInsts 398658 # Number of dispatched non-speculative instructions
+system.cpu0.iew.iewIQFullEvents 37609 # Number of times the IQ has become full, causing a stall
+system.cpu0.iew.iewLSQFullEvents 4704 # Number of times the LSQ has become full, causing a stall
+system.cpu0.iew.memOrderViolationEvents 10021 # Number of memory order violations
+system.cpu0.iew.predictedTakenIncorrect 177778 # Number of branches that were predicted taken incorrectly
+system.cpu0.iew.predictedNotTakenIncorrect 116282 # Number of branches that were predicted not taken incorrectly
+system.cpu0.iew.branchMispredicts 294060 # Number of branch mispredicts detected at execute
+system.cpu0.iew.iewExecutedInsts 31219910 # Number of executed instructions
+system.cpu0.iew.iewExecLoadInsts 7794602 # Number of load instructions executed
+system.cpu0.iew.iewExecSquashedInsts 386675 # Number of squashed instructions skipped in execute
system.cpu0.iew.exec_swp 0 # number of swp insts executed
-system.cpu0.iew.exec_nop 59236 # number of nop insts executed
-system.cpu0.iew.exec_refs 12477007 # number of memory reference insts executed
-system.cpu0.iew.exec_branches 4073990 # Number of branches executed
-system.cpu0.iew.exec_stores 4687791 # Number of stores executed
-system.cpu0.iew.exec_rate 0.562681 # Inst execution rate
-system.cpu0.iew.wb_sent 30989414 # cumulative count of insts sent to commit
-system.cpu0.iew.wb_count 28962206 # cumulative count of insts written-back
-system.cpu0.iew.wb_producers 15536163 # num instructions producing a value
-system.cpu0.iew.wb_consumers 30480637 # num instructions consuming a value
+system.cpu0.iew.exec_nop 59524 # number of nop insts executed
+system.cpu0.iew.exec_refs 12495671 # number of memory reference insts executed
+system.cpu0.iew.exec_branches 4074655 # Number of branches executed
+system.cpu0.iew.exec_stores 4701069 # Number of stores executed
+system.cpu0.iew.exec_rate 0.562142 # Inst execution rate
+system.cpu0.iew.wb_sent 31018630 # cumulative count of insts sent to commit
+system.cpu0.iew.wb_count 28991575 # cumulative count of insts written-back
+system.cpu0.iew.wb_producers 15563441 # num instructions producing a value
+system.cpu0.iew.wb_consumers 30561631 # num instructions consuming a value
system.cpu0.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ
-system.cpu0.iew.wb_rate 0.522396 # insts written-back per cycle
-system.cpu0.iew.wb_fanout 0.509706 # average fanout of values written-back
+system.cpu0.iew.wb_rate 0.522019 # insts written-back per cycle
+system.cpu0.iew.wb_fanout 0.509248 # average fanout of values written-back
system.cpu0.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ
-system.cpu0.commit.commitCommittedInsts 19711221 # The number of committed instructions
-system.cpu0.commit.commitCommittedOps 26183930 # The number of committed instructions
-system.cpu0.commit.commitSquashedInsts 5818378 # The number of squashed insts skipped by commit
-system.cpu0.commit.commitNonSpecStalls 541535 # The number of times commit has been forced to stall to communicate backwards
-system.cpu0.commit.branchMispredicts 256688 # The number of times a branch was mispredicted
-system.cpu0.commit.committed_per_cycle::samples 34668404 # Number of insts commited each cycle
-system.cpu0.commit.committed_per_cycle::mean 0.755268 # Number of insts commited each cycle
-system.cpu0.commit.committed_per_cycle::stdev 1.722296 # Number of insts commited each cycle
+system.cpu0.commit.commitCommittedInsts 19778635 # The number of committed instructions
+system.cpu0.commit.commitCommittedOps 26259365 # The number of committed instructions
+system.cpu0.commit.commitSquashedInsts 5789320 # The number of squashed insts skipped by commit
+system.cpu0.commit.commitNonSpecStalls 541265 # The number of times commit has been forced to stall to communicate backwards
+system.cpu0.commit.branchMispredicts 257580 # The number of times a branch was mispredicted
+system.cpu0.commit.committed_per_cycle::samples 34779040 # Number of insts commited each cycle
+system.cpu0.commit.committed_per_cycle::mean 0.755034 # Number of insts commited each cycle
+system.cpu0.commit.committed_per_cycle::stdev 1.721723 # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle
-system.cpu0.commit.committed_per_cycle::0 24842291 71.66% 71.66% # Number of insts commited each cycle
-system.cpu0.commit.committed_per_cycle::1 4903680 14.14% 85.80% # Number of insts commited each cycle
-system.cpu0.commit.committed_per_cycle::2 1598724 4.61% 90.41% # Number of insts commited each cycle
-system.cpu0.commit.committed_per_cycle::3 790644 2.28% 92.69% # Number of insts commited each cycle
-system.cpu0.commit.committed_per_cycle::4 613460 1.77% 94.46% # Number of insts commited each cycle
-system.cpu0.commit.committed_per_cycle::5 370313 1.07% 95.53% # Number of insts commited each cycle
-system.cpu0.commit.committed_per_cycle::6 401864 1.16% 96.69% # Number of insts commited each cycle
-system.cpu0.commit.committed_per_cycle::7 185143 0.53% 97.22% # Number of insts commited each cycle
-system.cpu0.commit.committed_per_cycle::8 962285 2.78% 100.00% # Number of insts commited each cycle
+system.cpu0.commit.committed_per_cycle::0 24914736 71.64% 71.64% # Number of insts commited each cycle
+system.cpu0.commit.committed_per_cycle::1 4928764 14.17% 85.81% # Number of insts commited each cycle
+system.cpu0.commit.committed_per_cycle::2 1604217 4.61% 90.42% # Number of insts commited each cycle
+system.cpu0.commit.committed_per_cycle::3 793137 2.28% 92.70% # Number of insts commited each cycle
+system.cpu0.commit.committed_per_cycle::4 618967 1.78% 94.48% # Number of insts commited each cycle
+system.cpu0.commit.committed_per_cycle::5 369015 1.06% 95.54% # Number of insts commited each cycle
+system.cpu0.commit.committed_per_cycle::6 397376 1.14% 96.69% # Number of insts commited each cycle
+system.cpu0.commit.committed_per_cycle::7 185067 0.53% 97.22% # Number of insts commited each cycle
+system.cpu0.commit.committed_per_cycle::8 967761 2.78% 100.00% # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle
-system.cpu0.commit.committed_per_cycle::total 34668404 # Number of insts commited each cycle
-system.cpu0.commit.committedInsts 19711221 # Number of instructions committed
-system.cpu0.commit.committedOps 26183930 # Number of ops (including micro ops) committed
+system.cpu0.commit.committed_per_cycle::total 34779040 # Number of insts commited each cycle
+system.cpu0.commit.committedInsts 19778635 # Number of instructions committed
+system.cpu0.commit.committedOps 26259365 # Number of ops (including micro ops) committed
system.cpu0.commit.swp_count 0 # Number of s/w prefetches committed
-system.cpu0.commit.refs 9652738 # Number of memory references committed
-system.cpu0.commit.loads 5201065 # Number of loads committed
-system.cpu0.commit.membars 194494 # Number of memory barriers committed
-system.cpu0.commit.branches 3582933 # Number of branches committed
+system.cpu0.commit.refs 9684322 # Number of memory references committed
+system.cpu0.commit.loads 5219928 # Number of loads committed
+system.cpu0.commit.membars 194188 # Number of memory barriers committed
+system.cpu0.commit.branches 3591028 # Number of branches committed
system.cpu0.commit.fp_insts 4336 # Number of committed floating point instructions.
-system.cpu0.commit.int_insts 23269679 # Number of committed integer instructions.
-system.cpu0.commit.function_calls 421897 # Number of function calls committed.
-system.cpu0.commit.bw_lim_events 962285 # number cycles where commit BW limit reached
+system.cpu0.commit.int_insts 23338580 # Number of committed integer instructions.
+system.cpu0.commit.function_calls 422336 # Number of function calls committed.
+system.cpu0.commit.bw_lim_events 967761 # number cycles where commit BW limit reached
system.cpu0.commit.bw_limited 0 # number of insts not committed due to BW limits
-system.cpu0.rob.rob_reads 65094034 # The number of ROB reads
-system.cpu0.rob.rob_writes 64941259 # The number of ROB writes
-system.cpu0.timesIdled 360737 # Number of times that the entire CPU went into an idle state and unscheduled itself
-system.cpu0.idleCycles 19866479 # Total number of cycles that the CPU has spent unscheduled due to idling
-system.cpu0.quiesceCycles 5085563503 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
-system.cpu0.committedInsts 19686667 # Number of Instructions Simulated
-system.cpu0.committedOps 26159376 # Number of Ops (including micro ops) Simulated
-system.cpu0.committedInsts_total 19686667 # Number of Instructions Simulated
-system.cpu0.cpi 2.816173 # CPI: Cycles Per Instruction
-system.cpu0.cpi_total 2.816173 # CPI: Total CPI of All Threads
-system.cpu0.ipc 0.355092 # IPC: Instructions Per Cycle
-system.cpu0.ipc_total 0.355092 # IPC: Total IPC of All Threads
-system.cpu0.int_regfile_reads 145393582 # number of integer regfile reads
-system.cpu0.int_regfile_writes 28417758 # number of integer regfile writes
-system.cpu0.fp_regfile_reads 4580 # number of floating regfile reads
-system.cpu0.fp_regfile_writes 450 # number of floating regfile writes
-system.cpu0.misc_regfile_reads 38939704 # number of misc regfile reads
-system.cpu0.misc_regfile_writes 443716 # number of misc regfile writes
-system.cpu0.icache.replacements 341473 # number of replacements
-system.cpu0.icache.tagsinuse 511.631456 # Cycle average of tags in use
-system.cpu0.icache.total_refs 3435816 # Total number of references to valid blocks.
-system.cpu0.icache.sampled_refs 341985 # Sample count of references to valid blocks.
-system.cpu0.icache.avg_refs 10.046686 # Average number of references to valid blocks.
-system.cpu0.icache.warmup_cycle 6333594000 # Cycle when the warmup percentage was hit.
-system.cpu0.icache.occ_blocks::cpu0.inst 511.631456 # Average occupied blocks per requestor
+system.cpu0.rob.rob_reads 65245448 # The number of ROB reads
+system.cpu0.rob.rob_writes 65031517 # The number of ROB writes
+system.cpu0.timesIdled 363170 # Number of times that the entire CPU went into an idle state and unscheduled itself
+system.cpu0.idleCycles 19854766 # Total number of cycles that the CPU has spent unscheduled due to idling
+system.cpu0.quiesceCycles 5085481268 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
+system.cpu0.committedInsts 19754081 # Number of Instructions Simulated
+system.cpu0.committedOps 26234811 # Number of Ops (including micro ops) Simulated
+system.cpu0.committedInsts_total 19754081 # Number of Instructions Simulated
+system.cpu0.cpi 2.811437 # CPI: Cycles Per Instruction
+system.cpu0.cpi_total 2.811437 # CPI: Total CPI of All Threads
+system.cpu0.ipc 0.355690 # IPC: Instructions Per Cycle
+system.cpu0.ipc_total 0.355690 # IPC: Total IPC of All Threads
+system.cpu0.int_regfile_reads 145547438 # number of integer regfile reads
+system.cpu0.int_regfile_writes 28450023 # number of integer regfile writes
+system.cpu0.fp_regfile_reads 4554 # number of floating regfile reads
+system.cpu0.fp_regfile_writes 434 # number of floating regfile writes
+system.cpu0.misc_regfile_reads 38991088 # number of misc regfile reads
+system.cpu0.misc_regfile_writes 443778 # number of misc regfile writes
+system.cpu0.icache.replacements 345092 # number of replacements
+system.cpu0.icache.tagsinuse 511.631515 # Cycle average of tags in use
+system.cpu0.icache.total_refs 3456613 # Total number of references to valid blocks.
+system.cpu0.icache.sampled_refs 345604 # Sample count of references to valid blocks.
+system.cpu0.icache.avg_refs 10.001658 # Average number of references to valid blocks.
+system.cpu0.icache.warmup_cycle 6336390000 # Cycle when the warmup percentage was hit.
+system.cpu0.icache.occ_blocks::cpu0.inst 511.631515 # Average occupied blocks per requestor
system.cpu0.icache.occ_percent::cpu0.inst 0.999280 # Average percentage of cache occupancy
system.cpu0.icache.occ_percent::total 0.999280 # Average percentage of cache occupancy
-system.cpu0.icache.ReadReq_hits::cpu0.inst 3435816 # number of ReadReq hits
-system.cpu0.icache.ReadReq_hits::total 3435816 # number of ReadReq hits
-system.cpu0.icache.demand_hits::cpu0.inst 3435816 # number of demand (read+write) hits
-system.cpu0.icache.demand_hits::total 3435816 # number of demand (read+write) hits
-system.cpu0.icache.overall_hits::cpu0.inst 3435816 # number of overall hits
-system.cpu0.icache.overall_hits::total 3435816 # number of overall hits
-system.cpu0.icache.ReadReq_misses::cpu0.inst 371369 # number of ReadReq misses
-system.cpu0.icache.ReadReq_misses::total 371369 # number of ReadReq misses
-system.cpu0.icache.demand_misses::cpu0.inst 371369 # number of demand (read+write) misses
-system.cpu0.icache.demand_misses::total 371369 # number of demand (read+write) misses
-system.cpu0.icache.overall_misses::cpu0.inst 371369 # number of overall misses
-system.cpu0.icache.overall_misses::total 371369 # number of overall misses
-system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 5641865987 # number of ReadReq miss cycles
-system.cpu0.icache.ReadReq_miss_latency::total 5641865987 # number of ReadReq miss cycles
-system.cpu0.icache.demand_miss_latency::cpu0.inst 5641865987 # number of demand (read+write) miss cycles
-system.cpu0.icache.demand_miss_latency::total 5641865987 # number of demand (read+write) miss cycles
-system.cpu0.icache.overall_miss_latency::cpu0.inst 5641865987 # number of overall miss cycles
-system.cpu0.icache.overall_miss_latency::total 5641865987 # number of overall miss cycles
-system.cpu0.icache.ReadReq_accesses::cpu0.inst 3807185 # number of ReadReq accesses(hits+misses)
-system.cpu0.icache.ReadReq_accesses::total 3807185 # number of ReadReq accesses(hits+misses)
-system.cpu0.icache.demand_accesses::cpu0.inst 3807185 # number of demand (read+write) accesses
-system.cpu0.icache.demand_accesses::total 3807185 # number of demand (read+write) accesses
-system.cpu0.icache.overall_accesses::cpu0.inst 3807185 # number of overall (read+write) accesses
-system.cpu0.icache.overall_accesses::total 3807185 # number of overall (read+write) accesses
-system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.097544 # miss rate for ReadReq accesses
-system.cpu0.icache.demand_miss_rate::cpu0.inst 0.097544 # miss rate for demand accesses
-system.cpu0.icache.overall_miss_rate::cpu0.inst 0.097544 # miss rate for overall accesses
-system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 15192.075771 # average ReadReq miss latency
-system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 15192.075771 # average overall miss latency
-system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 15192.075771 # average overall miss latency
-system.cpu0.icache.blocked_cycles::no_mshrs 1691991 # number of cycles access was blocked
+system.cpu0.icache.ReadReq_hits::cpu0.inst 3456613 # number of ReadReq hits
+system.cpu0.icache.ReadReq_hits::total 3456613 # number of ReadReq hits
+system.cpu0.icache.demand_hits::cpu0.inst 3456613 # number of demand (read+write) hits
+system.cpu0.icache.demand_hits::total 3456613 # number of demand (read+write) hits
+system.cpu0.icache.overall_hits::cpu0.inst 3456613 # number of overall hits
+system.cpu0.icache.overall_hits::total 3456613 # number of overall hits
+system.cpu0.icache.ReadReq_misses::cpu0.inst 375216 # number of ReadReq misses
+system.cpu0.icache.ReadReq_misses::total 375216 # number of ReadReq misses
+system.cpu0.icache.demand_misses::cpu0.inst 375216 # number of demand (read+write) misses
+system.cpu0.icache.demand_misses::total 375216 # number of demand (read+write) misses
+system.cpu0.icache.overall_misses::cpu0.inst 375216 # number of overall misses
+system.cpu0.icache.overall_misses::total 375216 # number of overall misses
+system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 5700257984 # number of ReadReq miss cycles
+system.cpu0.icache.ReadReq_miss_latency::total 5700257984 # number of ReadReq miss cycles
+system.cpu0.icache.demand_miss_latency::cpu0.inst 5700257984 # number of demand (read+write) miss cycles
+system.cpu0.icache.demand_miss_latency::total 5700257984 # number of demand (read+write) miss cycles
+system.cpu0.icache.overall_miss_latency::cpu0.inst 5700257984 # number of overall miss cycles
+system.cpu0.icache.overall_miss_latency::total 5700257984 # number of overall miss cycles
+system.cpu0.icache.ReadReq_accesses::cpu0.inst 3831829 # number of ReadReq accesses(hits+misses)
+system.cpu0.icache.ReadReq_accesses::total 3831829 # number of ReadReq accesses(hits+misses)
+system.cpu0.icache.demand_accesses::cpu0.inst 3831829 # number of demand (read+write) accesses
+system.cpu0.icache.demand_accesses::total 3831829 # number of demand (read+write) accesses
+system.cpu0.icache.overall_accesses::cpu0.inst 3831829 # number of overall (read+write) accesses
+system.cpu0.icache.overall_accesses::total 3831829 # number of overall (read+write) accesses
+system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.097921 # miss rate for ReadReq accesses
+system.cpu0.icache.demand_miss_rate::cpu0.inst 0.097921 # miss rate for demand accesses
+system.cpu0.icache.overall_miss_rate::cpu0.inst 0.097921 # miss rate for overall accesses
+system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 15191.937401 # average ReadReq miss latency
+system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 15191.937401 # average overall miss latency
+system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 15191.937401 # average overall miss latency
+system.cpu0.icache.blocked_cycles::no_mshrs 1854487 # number of cycles access was blocked
system.cpu0.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
-system.cpu0.icache.blocked::no_mshrs 206 # number of cycles access was blocked
+system.cpu0.icache.blocked::no_mshrs 217 # number of cycles access was blocked
system.cpu0.icache.blocked::no_targets 0 # number of cycles access was blocked
-system.cpu0.icache.avg_blocked_cycles::no_mshrs 8213.548544 # average number of cycles each access was blocked
+system.cpu0.icache.avg_blocked_cycles::no_mshrs 8546.023041 # average number of cycles each access was blocked
system.cpu0.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu0.icache.fast_writes 0 # number of fast writes performed
system.cpu0.icache.cache_copies 0 # number of cache copies performed
-system.cpu0.icache.writebacks::writebacks 19233 # number of writebacks
-system.cpu0.icache.writebacks::total 19233 # number of writebacks
-system.cpu0.icache.ReadReq_mshr_hits::cpu0.inst 29370 # number of ReadReq MSHR hits
-system.cpu0.icache.ReadReq_mshr_hits::total 29370 # number of ReadReq MSHR hits
-system.cpu0.icache.demand_mshr_hits::cpu0.inst 29370 # number of demand (read+write) MSHR hits
-system.cpu0.icache.demand_mshr_hits::total 29370 # number of demand (read+write) MSHR hits
-system.cpu0.icache.overall_mshr_hits::cpu0.inst 29370 # number of overall MSHR hits
-system.cpu0.icache.overall_mshr_hits::total 29370 # number of overall MSHR hits
-system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 341999 # number of ReadReq MSHR misses
-system.cpu0.icache.ReadReq_mshr_misses::total 341999 # number of ReadReq MSHR misses
-system.cpu0.icache.demand_mshr_misses::cpu0.inst 341999 # number of demand (read+write) MSHR misses
-system.cpu0.icache.demand_mshr_misses::total 341999 # number of demand (read+write) MSHR misses
-system.cpu0.icache.overall_mshr_misses::cpu0.inst 341999 # number of overall MSHR misses
-system.cpu0.icache.overall_mshr_misses::total 341999 # number of overall MSHR misses
-system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 4224982491 # number of ReadReq MSHR miss cycles
-system.cpu0.icache.ReadReq_mshr_miss_latency::total 4224982491 # number of ReadReq MSHR miss cycles
-system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 4224982491 # number of demand (read+write) MSHR miss cycles
-system.cpu0.icache.demand_mshr_miss_latency::total 4224982491 # number of demand (read+write) MSHR miss cycles
-system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 4224982491 # number of overall MSHR miss cycles
-system.cpu0.icache.overall_mshr_miss_latency::total 4224982491 # number of overall MSHR miss cycles
+system.cpu0.icache.writebacks::writebacks 19422 # number of writebacks
+system.cpu0.icache.writebacks::total 19422 # number of writebacks
+system.cpu0.icache.ReadReq_mshr_hits::cpu0.inst 29600 # number of ReadReq MSHR hits
+system.cpu0.icache.ReadReq_mshr_hits::total 29600 # number of ReadReq MSHR hits
+system.cpu0.icache.demand_mshr_hits::cpu0.inst 29600 # number of demand (read+write) MSHR hits
+system.cpu0.icache.demand_mshr_hits::total 29600 # number of demand (read+write) MSHR hits
+system.cpu0.icache.overall_mshr_hits::cpu0.inst 29600 # number of overall MSHR hits
+system.cpu0.icache.overall_mshr_hits::total 29600 # number of overall MSHR hits
+system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 345616 # number of ReadReq MSHR misses
+system.cpu0.icache.ReadReq_mshr_misses::total 345616 # number of ReadReq MSHR misses
+system.cpu0.icache.demand_mshr_misses::cpu0.inst 345616 # number of demand (read+write) MSHR misses
+system.cpu0.icache.demand_mshr_misses::total 345616 # number of demand (read+write) MSHR misses
+system.cpu0.icache.overall_mshr_misses::cpu0.inst 345616 # number of overall MSHR misses
+system.cpu0.icache.overall_mshr_misses::total 345616 # number of overall MSHR misses
+system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 4268453987 # number of ReadReq MSHR miss cycles
+system.cpu0.icache.ReadReq_mshr_miss_latency::total 4268453987 # number of ReadReq MSHR miss cycles
+system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 4268453987 # number of demand (read+write) MSHR miss cycles
+system.cpu0.icache.demand_mshr_miss_latency::total 4268453987 # number of demand (read+write) MSHR miss cycles
+system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 4268453987 # number of overall MSHR miss cycles
+system.cpu0.icache.overall_mshr_miss_latency::total 4268453987 # number of overall MSHR miss cycles
system.cpu0.icache.ReadReq_mshr_uncacheable_latency::cpu0.inst 7615500 # number of ReadReq MSHR uncacheable cycles
system.cpu0.icache.ReadReq_mshr_uncacheable_latency::total 7615500 # number of ReadReq MSHR uncacheable cycles
system.cpu0.icache.overall_mshr_uncacheable_latency::cpu0.inst 7615500 # number of overall MSHR uncacheable cycles
system.cpu0.icache.overall_mshr_uncacheable_latency::total 7615500 # number of overall MSHR uncacheable cycles
-system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.089830 # mshr miss rate for ReadReq accesses
-system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.089830 # mshr miss rate for demand accesses
-system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.089830 # mshr miss rate for overall accesses
-system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 12353.786096 # average ReadReq mshr miss latency
-system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 12353.786096 # average overall mshr miss latency
-system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 12353.786096 # average overall mshr miss latency
+system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.090196 # mshr miss rate for ReadReq accesses
+system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.090196 # mshr miss rate for demand accesses
+system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.090196 # mshr miss rate for overall accesses
+system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 12350.278885 # average ReadReq mshr miss latency
+system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 12350.278885 # average overall mshr miss latency
+system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 12350.278885 # average overall mshr miss latency
system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst inf # average ReadReq mshr uncacheable latency
system.cpu0.icache.overall_avg_mshr_uncacheable_latency::cpu0.inst inf # average overall mshr uncacheable latency
system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate
-system.cpu0.dcache.replacements 231957 # number of replacements
-system.cpu0.dcache.tagsinuse 430.483417 # Cycle average of tags in use
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-system.cpu0.dcache.sampled_refs 232325 # Sample count of references to valid blocks.
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+system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 6305406989 # number of overall MSHR miss cycles
+system.cpu0.dcache.overall_mshr_miss_latency::total 6305406989 # number of overall MSHR miss cycles
+system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 9221981000 # number of ReadReq MSHR uncacheable cycles
+system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 9221981000 # number of ReadReq MSHR uncacheable cycles
+system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data 843217391 # number of WriteReq MSHR uncacheable cycles
+system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 843217391 # number of WriteReq MSHR uncacheable cycles
+system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 10065198391 # number of overall MSHR uncacheable cycles
+system.cpu0.dcache.overall_mshr_uncacheable_latency::total 10065198391 # number of overall MSHR uncacheable cycles
+system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.030818 # mshr miss rate for ReadReq accesses
+system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.029328 # mshr miss rate for WriteReq accesses
+system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.050038 # mshr miss rate for LoadLockedReq accesses
+system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.049461 # mshr miss rate for StoreCondReq accesses
+system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.030161 # mshr miss rate for demand accesses
+system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.030161 # mshr miss rate for overall accesses
+system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 12858.383693 # average ReadReq mshr miss latency
+system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 35977.924229 # average WriteReq mshr miss latency
+system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 8140.422673 # average LoadLockedReq mshr miss latency
+system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 7779.977304 # average StoreCondReq mshr miss latency
+system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 22761.476527 # average overall mshr miss latency
+system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 22761.476527 # average overall mshr miss latency
system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data inf # average ReadReq mshr uncacheable latency
system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data inf # average WriteReq mshr uncacheable latency
system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data inf # average overall mshr uncacheable latency
system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu1.dtb.inst_hits 0 # ITB inst hits
system.cpu1.dtb.inst_misses 0 # ITB inst misses
-system.cpu1.dtb.read_hits 45296976 # DTB read hits
-system.cpu1.dtb.read_misses 68040 # DTB read misses
-system.cpu1.dtb.write_hits 7958541 # DTB write hits
-system.cpu1.dtb.write_misses 20787 # DTB write misses
+system.cpu1.dtb.read_hits 45335988 # DTB read hits
+system.cpu1.dtb.read_misses 67766 # DTB read misses
+system.cpu1.dtb.write_hits 7974825 # DTB write hits
+system.cpu1.dtb.write_misses 20571 # DTB write misses
system.cpu1.dtb.flush_tlb 4 # Number of times complete TLB was flushed
system.cpu1.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
system.cpu1.dtb.flush_tlb_mva_asid 1439 # Number of times TLB was flushed by MVA & ASID
system.cpu1.dtb.flush_tlb_asid 63 # Number of times TLB was flushed by ASID
-system.cpu1.dtb.flush_entries 2725 # Number of entries that have been flushed from TLB
-system.cpu1.dtb.align_faults 7868 # Number of TLB faults due to alignment restrictions
-system.cpu1.dtb.prefetch_faults 603 # Number of TLB faults due to prefetch
+system.cpu1.dtb.flush_entries 2707 # Number of entries that have been flushed from TLB
+system.cpu1.dtb.align_faults 7654 # Number of TLB faults due to alignment restrictions
+system.cpu1.dtb.prefetch_faults 597 # Number of TLB faults due to prefetch
system.cpu1.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions
-system.cpu1.dtb.perms_faults 1726 # Number of TLB faults due to permissions restrictions
-system.cpu1.dtb.read_accesses 45365016 # DTB read accesses
-system.cpu1.dtb.write_accesses 7979328 # DTB write accesses
+system.cpu1.dtb.perms_faults 1825 # Number of TLB faults due to permissions restrictions
+system.cpu1.dtb.read_accesses 45403754 # DTB read accesses
+system.cpu1.dtb.write_accesses 7995396 # DTB write accesses
system.cpu1.dtb.inst_accesses 0 # ITB inst accesses
-system.cpu1.dtb.hits 53255517 # DTB hits
-system.cpu1.dtb.misses 88827 # DTB misses
-system.cpu1.dtb.accesses 53344344 # DTB accesses
-system.cpu1.itb.inst_hits 10421118 # ITB inst hits
-system.cpu1.itb.inst_misses 7923 # ITB inst misses
+system.cpu1.dtb.hits 53310813 # DTB hits
+system.cpu1.dtb.misses 88337 # DTB misses
+system.cpu1.dtb.accesses 53399150 # DTB accesses
+system.cpu1.itb.inst_hits 10447082 # ITB inst hits
+system.cpu1.itb.inst_misses 7775 # ITB inst misses
system.cpu1.itb.read_hits 0 # DTB read hits
system.cpu1.itb.read_misses 0 # DTB read misses
system.cpu1.itb.write_hits 0 # DTB write hits
system.cpu1.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
system.cpu1.itb.flush_tlb_mva_asid 1439 # Number of times TLB was flushed by MVA & ASID
system.cpu1.itb.flush_tlb_asid 63 # Number of times TLB was flushed by ASID
-system.cpu1.itb.flush_entries 1559 # Number of entries that have been flushed from TLB
+system.cpu1.itb.flush_entries 1562 # Number of entries that have been flushed from TLB
system.cpu1.itb.align_faults 0 # Number of TLB faults due to alignment restrictions
system.cpu1.itb.prefetch_faults 0 # Number of TLB faults due to prefetch
system.cpu1.itb.domain_faults 0 # Number of TLB faults due to domain restrictions
-system.cpu1.itb.perms_faults 4993 # Number of TLB faults due to permissions restrictions
+system.cpu1.itb.perms_faults 5028 # Number of TLB faults due to permissions restrictions
system.cpu1.itb.read_accesses 0 # DTB read accesses
system.cpu1.itb.write_accesses 0 # DTB write accesses
-system.cpu1.itb.inst_accesses 10429041 # ITB inst accesses
-system.cpu1.itb.hits 10421118 # DTB hits
-system.cpu1.itb.misses 7923 # DTB misses
-system.cpu1.itb.accesses 10429041 # DTB accesses
-system.cpu1.numCycles 361284565 # number of cpu cycles simulated
+system.cpu1.itb.inst_accesses 10454857 # ITB inst accesses
+system.cpu1.itb.hits 10447082 # DTB hits
+system.cpu1.itb.misses 7775 # DTB misses
+system.cpu1.itb.accesses 10454857 # DTB accesses
+system.cpu1.numCycles 361402922 # number of cpu cycles simulated
system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed
-system.cpu1.BPredUnit.lookups 11160075 # Number of BP lookups
-system.cpu1.BPredUnit.condPredicted 8957573 # Number of conditional branches predicted
-system.cpu1.BPredUnit.condIncorrect 655963 # Number of conditional branches incorrect
-system.cpu1.BPredUnit.BTBLookups 7602711 # Number of BTB lookups
-system.cpu1.BPredUnit.BTBHits 6100291 # Number of BTB hits
+system.cpu1.BPredUnit.lookups 11186826 # Number of BP lookups
+system.cpu1.BPredUnit.condPredicted 8978228 # Number of conditional branches predicted
+system.cpu1.BPredUnit.condIncorrect 659649 # Number of conditional branches incorrect
+system.cpu1.BPredUnit.BTBLookups 7702930 # Number of BTB lookups
+system.cpu1.BPredUnit.BTBHits 6115228 # Number of BTB hits
system.cpu1.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
-system.cpu1.BPredUnit.usedRAS 909624 # Number of times the RAS was used to get a target.
-system.cpu1.BPredUnit.RASInCorrect 143125 # Number of incorrect RAS predictions.
-system.cpu1.fetch.icacheStallCycles 24152579 # Number of cycles fetch is stalled on an Icache miss
-system.cpu1.fetch.Insts 79243321 # Number of instructions fetch has processed
-system.cpu1.fetch.Branches 11160075 # Number of branches that fetch encountered
-system.cpu1.fetch.predictedBranches 7009915 # Number of branches that fetch has predicted taken
-system.cpu1.fetch.Cycles 17005367 # Number of cycles fetch has run and was not squashing or blocked
-system.cpu1.fetch.SquashCycles 5503080 # Number of cycles fetch has spent squashing
-system.cpu1.fetch.TlbCycles 106407 # Number of cycles fetch has spent waiting for tlb
-system.cpu1.fetch.BlockedCycles 74478012 # Number of cycles fetch has spent blocked
-system.cpu1.fetch.MiscStallCycles 5575 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
-system.cpu1.fetch.PendingTrapStallCycles 116210 # Number of stall cycles due to pending traps
-system.cpu1.fetch.PendingQuiesceStallCycles 165404 # Number of stall cycles due to pending quiesce instructions
-system.cpu1.fetch.IcacheWaitRetryStallCycles 287 # Number of stall cycles due to full MSHR
-system.cpu1.fetch.CacheLines 10415863 # Number of cache lines fetched
-system.cpu1.fetch.IcacheSquashes 850791 # Number of outstanding Icache misses that were squashed
-system.cpu1.fetch.ItlbSquashes 4371 # Number of outstanding ITLB misses that were squashed
-system.cpu1.fetch.rateDist::samples 119805091 # Number of instructions fetched each cycle (Total)
-system.cpu1.fetch.rateDist::mean 0.807068 # Number of instructions fetched each cycle (Total)
-system.cpu1.fetch.rateDist::stdev 2.185605 # Number of instructions fetched each cycle (Total)
+system.cpu1.BPredUnit.usedRAS 914050 # Number of times the RAS was used to get a target.
+system.cpu1.BPredUnit.RASInCorrect 143881 # Number of incorrect RAS predictions.
+system.cpu1.fetch.icacheStallCycles 24238168 # Number of cycles fetch is stalled on an Icache miss
+system.cpu1.fetch.Insts 79362685 # Number of instructions fetch has processed
+system.cpu1.fetch.Branches 11186826 # Number of branches that fetch encountered
+system.cpu1.fetch.predictedBranches 7029278 # Number of branches that fetch has predicted taken
+system.cpu1.fetch.Cycles 17037334 # Number of cycles fetch has run and was not squashing or blocked
+system.cpu1.fetch.SquashCycles 5514806 # Number of cycles fetch has spent squashing
+system.cpu1.fetch.TlbCycles 104106 # Number of cycles fetch has spent waiting for tlb
+system.cpu1.fetch.BlockedCycles 74528918 # Number of cycles fetch has spent blocked
+system.cpu1.fetch.MiscStallCycles 5814 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
+system.cpu1.fetch.PendingTrapStallCycles 113982 # Number of stall cycles due to pending traps
+system.cpu1.fetch.PendingQuiesceStallCycles 165536 # Number of stall cycles due to pending quiesce instructions
+system.cpu1.fetch.IcacheWaitRetryStallCycles 353 # Number of stall cycles due to full MSHR
+system.cpu1.fetch.CacheLines 10441784 # Number of cache lines fetched
+system.cpu1.fetch.IcacheSquashes 854309 # Number of outstanding Icache misses that were squashed
+system.cpu1.fetch.ItlbSquashes 4213 # Number of outstanding ITLB misses that were squashed
+system.cpu1.fetch.rateDist::samples 119977470 # Number of instructions fetched each cycle (Total)
+system.cpu1.fetch.rateDist::mean 0.807329 # Number of instructions fetched each cycle (Total)
+system.cpu1.fetch.rateDist::stdev 2.185858 # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)
-system.cpu1.fetch.rateDist::0 102809911 85.81% 85.81% # Number of instructions fetched each cycle (Total)
-system.cpu1.fetch.rateDist::1 1026487 0.86% 86.67% # Number of instructions fetched each cycle (Total)
-system.cpu1.fetch.rateDist::2 1244623 1.04% 87.71% # Number of instructions fetched each cycle (Total)
-system.cpu1.fetch.rateDist::3 2220450 1.85% 89.56% # Number of instructions fetched each cycle (Total)
-system.cpu1.fetch.rateDist::4 1447523 1.21% 90.77% # Number of instructions fetched each cycle (Total)
-system.cpu1.fetch.rateDist::5 762352 0.64% 91.41% # Number of instructions fetched each cycle (Total)
-system.cpu1.fetch.rateDist::6 2446430 2.04% 93.45% # Number of instructions fetched each cycle (Total)
-system.cpu1.fetch.rateDist::7 545220 0.46% 93.91% # Number of instructions fetched each cycle (Total)
-system.cpu1.fetch.rateDist::8 7302095 6.09% 100.00% # Number of instructions fetched each cycle (Total)
+system.cpu1.fetch.rateDist::0 102950411 85.81% 85.81% # Number of instructions fetched each cycle (Total)
+system.cpu1.fetch.rateDist::1 1027065 0.86% 86.66% # Number of instructions fetched each cycle (Total)
+system.cpu1.fetch.rateDist::2 1252290 1.04% 87.71% # Number of instructions fetched each cycle (Total)
+system.cpu1.fetch.rateDist::3 2222542 1.85% 89.56% # Number of instructions fetched each cycle (Total)
+system.cpu1.fetch.rateDist::4 1450508 1.21% 90.77% # Number of instructions fetched each cycle (Total)
+system.cpu1.fetch.rateDist::5 763655 0.64% 91.41% # Number of instructions fetched each cycle (Total)
+system.cpu1.fetch.rateDist::6 2450140 2.04% 93.45% # Number of instructions fetched each cycle (Total)
+system.cpu1.fetch.rateDist::7 546027 0.46% 93.90% # Number of instructions fetched each cycle (Total)
+system.cpu1.fetch.rateDist::8 7314832 6.10% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total)
-system.cpu1.fetch.rateDist::total 119805091 # Number of instructions fetched each cycle (Total)
-system.cpu1.fetch.branchRate 0.030890 # Number of branch fetches per cycle
-system.cpu1.fetch.rate 0.219338 # Number of inst fetches per cycle
-system.cpu1.decode.IdleCycles 25854345 # Number of cycles decode is idle
-system.cpu1.decode.BlockedCycles 74385490 # Number of cycles decode is blocked
-system.cpu1.decode.RunCycles 15310008 # Number of cycles decode is running
-system.cpu1.decode.UnblockCycles 600331 # Number of cycles decode is unblocking
-system.cpu1.decode.SquashCycles 3654917 # Number of cycles decode is squashing
-system.cpu1.decode.BranchResolved 1553748 # Number of times decode resolved a branch
-system.cpu1.decode.BranchMispred 123029 # Number of times decode detected a branch misprediction
-system.cpu1.decode.DecodedInsts 89962683 # Number of instructions handled by decode
-system.cpu1.decode.SquashedInsts 400925 # Number of squashed instructions handled by decode
-system.cpu1.rename.SquashCycles 3654917 # Number of cycles rename is squashing
-system.cpu1.rename.IdleCycles 27463225 # Number of cycles rename is idle
-system.cpu1.rename.BlockCycles 32802291 # Number of cycles rename is blocking
-system.cpu1.rename.serializeStallCycles 37038310 # count of cycles rename stalled for serializing inst
-system.cpu1.rename.RunCycles 14280523 # Number of cycles rename is running
-system.cpu1.rename.UnblockCycles 4565825 # Number of cycles rename is unblocking
-system.cpu1.rename.RenamedInsts 83469542 # Number of instructions processed by rename
-system.cpu1.rename.ROBFullEvents 3103 # Number of times rename has blocked due to ROB full
-system.cpu1.rename.IQFullEvents 679234 # Number of times rename has blocked due to IQ full
-system.cpu1.rename.LSQFullEvents 3297923 # Number of times rename has blocked due to LSQ full
-system.cpu1.rename.FullRegisterEvents 45820 # Number of times there has been no free registers
-system.cpu1.rename.RenamedOperands 88189114 # Number of destination operands rename has renamed
-system.cpu1.rename.RenameLookups 385593776 # Number of register rename lookups that rename has made
-system.cpu1.rename.int_rename_lookups 385544391 # Number of integer rename lookups
-system.cpu1.rename.fp_rename_lookups 49385 # Number of floating rename lookups
-system.cpu1.rename.CommittedMaps 54868386 # Number of HB maps that are committed
-system.cpu1.rename.UndoneMaps 33320727 # Number of HB maps that are undone due to squashing
-system.cpu1.rename.serializingInsts 602216 # count of serializing insts renamed
-system.cpu1.rename.tempSerializingInsts 524905 # count of temporary serializing insts renamed
-system.cpu1.rename.skidInsts 8650801 # count of insts added to the skid buffer
-system.cpu1.memDep0.insertedLoads 16023709 # Number of loads inserted to the mem dependence unit.
-system.cpu1.memDep0.insertedStores 9632090 # Number of stores inserted to the mem dependence unit.
-system.cpu1.memDep0.conflictingLoads 1276299 # Number of conflicting loads.
-system.cpu1.memDep0.conflictingStores 1729146 # Number of conflicting stores.
-system.cpu1.iq.iqInstsAdded 74907136 # Number of instructions added to the IQ (excludes non-spec)
-system.cpu1.iq.iqNonSpecInstsAdded 1031599 # Number of non-speculative instructions added to the IQ
-system.cpu1.iq.iqInstsIssued 98321113 # Number of instructions issued
-system.cpu1.iq.iqSquashedInstsIssued 155877 # Number of squashed instructions issued
-system.cpu1.iq.iqSquashedInstsExamined 21592981 # Number of squashed instructions iterated over during squash; mainly for profiling
-system.cpu1.iq.iqSquashedOperandsExamined 61005208 # Number of squashed operands that are examined and possibly removed from graph
-system.cpu1.iq.iqSquashedNonSpecRemoved 224170 # Number of squashed non-spec instructions that were removed
-system.cpu1.iq.issued_per_cycle::samples 119805091 # Number of insts issued each cycle
-system.cpu1.iq.issued_per_cycle::mean 0.820676 # Number of insts issued each cycle
-system.cpu1.iq.issued_per_cycle::stdev 1.545860 # Number of insts issued each cycle
+system.cpu1.fetch.rateDist::total 119977470 # Number of instructions fetched each cycle (Total)
+system.cpu1.fetch.branchRate 0.030954 # Number of branch fetches per cycle
+system.cpu1.fetch.rate 0.219596 # Number of inst fetches per cycle
+system.cpu1.decode.IdleCycles 25932861 # Number of cycles decode is idle
+system.cpu1.decode.BlockedCycles 74439661 # Number of cycles decode is blocked
+system.cpu1.decode.RunCycles 15341871 # Number of cycles decode is running
+system.cpu1.decode.UnblockCycles 600655 # Number of cycles decode is unblocking
+system.cpu1.decode.SquashCycles 3662422 # Number of cycles decode is squashing
+system.cpu1.decode.BranchResolved 1558576 # Number of times decode resolved a branch
+system.cpu1.decode.BranchMispred 123600 # Number of times decode detected a branch misprediction
+system.cpu1.decode.DecodedInsts 90136794 # Number of instructions handled by decode
+system.cpu1.decode.SquashedInsts 402223 # Number of squashed instructions handled by decode
+system.cpu1.rename.SquashCycles 3662422 # Number of cycles rename is squashing
+system.cpu1.rename.IdleCycles 27545183 # Number of cycles rename is idle
+system.cpu1.rename.BlockCycles 32824542 # Number of cycles rename is blocking
+system.cpu1.rename.serializeStallCycles 37049772 # count of cycles rename stalled for serializing inst
+system.cpu1.rename.RunCycles 14316379 # Number of cycles rename is running
+system.cpu1.rename.UnblockCycles 4579172 # Number of cycles rename is unblocking
+system.cpu1.rename.RenamedInsts 83629464 # Number of instructions processed by rename
+system.cpu1.rename.ROBFullEvents 2956 # Number of times rename has blocked due to ROB full
+system.cpu1.rename.IQFullEvents 679775 # Number of times rename has blocked due to IQ full
+system.cpu1.rename.LSQFullEvents 3317472 # Number of times rename has blocked due to LSQ full
+system.cpu1.rename.FullRegisterEvents 46248 # Number of times there has been no free registers
+system.cpu1.rename.RenamedOperands 88354418 # Number of destination operands rename has renamed
+system.cpu1.rename.RenameLookups 386338466 # Number of register rename lookups that rename has made
+system.cpu1.rename.int_rename_lookups 386288470 # Number of integer rename lookups
+system.cpu1.rename.fp_rename_lookups 49996 # Number of floating rename lookups
+system.cpu1.rename.CommittedMaps 54988347 # Number of HB maps that are committed
+system.cpu1.rename.UndoneMaps 33366070 # Number of HB maps that are undone due to squashing
+system.cpu1.rename.serializingInsts 602019 # count of serializing insts renamed
+system.cpu1.rename.tempSerializingInsts 524737 # count of temporary serializing insts renamed
+system.cpu1.rename.skidInsts 8626692 # count of insts added to the skid buffer
+system.cpu1.memDep0.insertedLoads 16066963 # Number of loads inserted to the mem dependence unit.
+system.cpu1.memDep0.insertedStores 9656417 # Number of stores inserted to the mem dependence unit.
+system.cpu1.memDep0.conflictingLoads 1282659 # Number of conflicting loads.
+system.cpu1.memDep0.conflictingStores 1811239 # Number of conflicting stores.
+system.cpu1.iq.iqInstsAdded 75062782 # Number of instructions added to the IQ (excludes non-spec)
+system.cpu1.iq.iqNonSpecInstsAdded 1031692 # Number of non-speculative instructions added to the IQ
+system.cpu1.iq.iqInstsIssued 98462898 # Number of instructions issued
+system.cpu1.iq.iqSquashedInstsIssued 155624 # Number of squashed instructions issued
+system.cpu1.iq.iqSquashedInstsExamined 21632122 # Number of squashed instructions iterated over during squash; mainly for profiling
+system.cpu1.iq.iqSquashedOperandsExamined 61142717 # Number of squashed operands that are examined and possibly removed from graph
+system.cpu1.iq.iqSquashedNonSpecRemoved 223849 # Number of squashed non-spec instructions that were removed
+system.cpu1.iq.issued_per_cycle::samples 119977470 # Number of insts issued each cycle
+system.cpu1.iq.issued_per_cycle::mean 0.820678 # Number of insts issued each cycle
+system.cpu1.iq.issued_per_cycle::stdev 1.544702 # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
-system.cpu1.iq.issued_per_cycle::0 85906342 71.71% 71.71% # Number of insts issued each cycle
-system.cpu1.iq.issued_per_cycle::1 9617362 8.03% 79.73% # Number of insts issued each cycle
-system.cpu1.iq.issued_per_cycle::2 5105765 4.26% 83.99% # Number of insts issued each cycle
-system.cpu1.iq.issued_per_cycle::3 4221138 3.52% 87.52% # Number of insts issued each cycle
-system.cpu1.iq.issued_per_cycle::4 11132119 9.29% 96.81% # Number of insts issued each cycle
-system.cpu1.iq.issued_per_cycle::5 2139642 1.79% 98.60% # Number of insts issued each cycle
-system.cpu1.iq.issued_per_cycle::6 1275484 1.06% 99.66% # Number of insts issued each cycle
-system.cpu1.iq.issued_per_cycle::7 308695 0.26% 99.92% # Number of insts issued each cycle
-system.cpu1.iq.issued_per_cycle::8 98544 0.08% 100.00% # Number of insts issued each cycle
+system.cpu1.iq.issued_per_cycle::0 85994383 71.68% 71.68% # Number of insts issued each cycle
+system.cpu1.iq.issued_per_cycle::1 9640016 8.03% 79.71% # Number of insts issued each cycle
+system.cpu1.iq.issued_per_cycle::2 5133014 4.28% 83.99% # Number of insts issued each cycle
+system.cpu1.iq.issued_per_cycle::3 4263453 3.55% 87.54% # Number of insts issued each cycle
+system.cpu1.iq.issued_per_cycle::4 11149849 9.29% 96.84% # Number of insts issued each cycle
+system.cpu1.iq.issued_per_cycle::5 2119505 1.77% 98.60% # Number of insts issued each cycle
+system.cpu1.iq.issued_per_cycle::6 1269612 1.06% 99.66% # Number of insts issued each cycle
+system.cpu1.iq.issued_per_cycle::7 309202 0.26% 99.92% # Number of insts issued each cycle
+system.cpu1.iq.issued_per_cycle::8 98436 0.08% 100.00% # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle
-system.cpu1.iq.issued_per_cycle::total 119805091 # Number of insts issued each cycle
+system.cpu1.iq.issued_per_cycle::total 119977470 # Number of insts issued each cycle
system.cpu1.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available
-system.cpu1.iq.fu_full::IntAlu 44454 0.55% 0.55% # attempts to use FU when none available
-system.cpu1.iq.fu_full::IntMult 993 0.01% 0.56% # attempts to use FU when none available
+system.cpu1.iq.fu_full::IntAlu 44202 0.54% 0.54% # attempts to use FU when none available
+system.cpu1.iq.fu_full::IntMult 979 0.01% 0.56% # attempts to use FU when none available
system.cpu1.iq.fu_full::IntDiv 0 0.00% 0.56% # attempts to use FU when none available
system.cpu1.iq.fu_full::FloatAdd 0 0.00% 0.56% # attempts to use FU when none available
system.cpu1.iq.fu_full::FloatCmp 0 0.00% 0.56% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdFloatMult 0 0.00% 0.56% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdFloatMultAcc 0 0.00% 0.56% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdFloatSqrt 0 0.00% 0.56% # attempts to use FU when none available
-system.cpu1.iq.fu_full::MemRead 7729676 95.36% 95.92% # attempts to use FU when none available
-system.cpu1.iq.fu_full::MemWrite 330610 4.08% 100.00% # attempts to use FU when none available
+system.cpu1.iq.fu_full::MemRead 7732056 95.26% 95.82% # attempts to use FU when none available
+system.cpu1.iq.fu_full::MemWrite 339451 4.18% 100.00% # attempts to use FU when none available
system.cpu1.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
system.cpu1.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available
system.cpu1.iq.FU_type_0::No_OpClass 92819 0.09% 0.09% # Type of FU issued
-system.cpu1.iq.FU_type_0::IntAlu 43197176 43.93% 44.03% # Type of FU issued
-system.cpu1.iq.FU_type_0::IntMult 69729 0.07% 44.10% # Type of FU issued
-system.cpu1.iq.FU_type_0::IntDiv 0 0.00% 44.10% # Type of FU issued
-system.cpu1.iq.FU_type_0::FloatAdd 0 0.00% 44.10% # Type of FU issued
-system.cpu1.iq.FU_type_0::FloatCmp 0 0.00% 44.10% # Type of FU issued
-system.cpu1.iq.FU_type_0::FloatCvt 0 0.00% 44.10% # Type of FU issued
-system.cpu1.iq.FU_type_0::FloatMult 0 0.00% 44.10% # Type of FU issued
-system.cpu1.iq.FU_type_0::FloatDiv 0 0.00% 44.10% # Type of FU issued
-system.cpu1.iq.FU_type_0::FloatSqrt 0 0.00% 44.10% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdAdd 0 0.00% 44.10% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdAddAcc 0 0.00% 44.10% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdAlu 0 0.00% 44.10% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdCmp 0 0.00% 44.10% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdCvt 0 0.00% 44.10% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdMisc 31 0.00% 44.10% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdMult 0 0.00% 44.10% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdMultAcc 0 0.00% 44.10% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdShift 38 0.00% 44.10% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdShiftAcc 4 0.00% 44.10% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdSqrt 0 0.00% 44.10% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdFloatAdd 0 0.00% 44.10% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdFloatAlu 0 0.00% 44.10% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdFloatCmp 0 0.00% 44.10% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdFloatCvt 0 0.00% 44.10% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdFloatDiv 0 0.00% 44.10% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdFloatMisc 1798 0.00% 44.10% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdFloatMult 0 0.00% 44.10% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdFloatMultAcc 4 0.00% 44.10% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdFloatSqrt 0 0.00% 44.10% # Type of FU issued
-system.cpu1.iq.FU_type_0::MemRead 46580491 47.38% 91.48% # Type of FU issued
-system.cpu1.iq.FU_type_0::MemWrite 8379023 8.52% 100.00% # Type of FU issued
+system.cpu1.iq.FU_type_0::IntAlu 43271411 43.95% 44.04% # Type of FU issued
+system.cpu1.iq.FU_type_0::IntMult 69911 0.07% 44.11% # Type of FU issued
+system.cpu1.iq.FU_type_0::IntDiv 0 0.00% 44.11% # Type of FU issued
+system.cpu1.iq.FU_type_0::FloatAdd 0 0.00% 44.11% # Type of FU issued
+system.cpu1.iq.FU_type_0::FloatCmp 0 0.00% 44.11% # Type of FU issued
+system.cpu1.iq.FU_type_0::FloatCvt 0 0.00% 44.11% # Type of FU issued
+system.cpu1.iq.FU_type_0::FloatMult 0 0.00% 44.11% # Type of FU issued
+system.cpu1.iq.FU_type_0::FloatDiv 0 0.00% 44.11% # Type of FU issued
+system.cpu1.iq.FU_type_0::FloatSqrt 0 0.00% 44.11% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdAdd 0 0.00% 44.11% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdAddAcc 0 0.00% 44.11% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdAlu 0 0.00% 44.11% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdCmp 0 0.00% 44.11% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdCvt 0 0.00% 44.11% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdMisc 29 0.00% 44.11% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdMult 0 0.00% 44.11% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdMultAcc 0 0.00% 44.11% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdShift 39 0.00% 44.11% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdShiftAcc 10 0.00% 44.11% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdSqrt 0 0.00% 44.11% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdFloatAdd 0 0.00% 44.11% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdFloatAlu 0 0.00% 44.11% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdFloatCmp 0 0.00% 44.11% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdFloatCvt 0 0.00% 44.11% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdFloatDiv 0 0.00% 44.11% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdFloatMisc 1782 0.00% 44.11% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdFloatMult 0 0.00% 44.11% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdFloatMultAcc 10 0.00% 44.11% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdFloatSqrt 0 0.00% 44.11% # Type of FU issued
+system.cpu1.iq.FU_type_0::MemRead 46626317 47.35% 91.47% # Type of FU issued
+system.cpu1.iq.FU_type_0::MemWrite 8400570 8.53% 100.00% # Type of FU issued
system.cpu1.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued
system.cpu1.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued
-system.cpu1.iq.FU_type_0::total 98321113 # Type of FU issued
-system.cpu1.iq.rate 0.272143 # Inst issue rate
-system.cpu1.iq.fu_busy_cnt 8105733 # FU busy when requested
-system.cpu1.iq.fu_busy_rate 0.082441 # FU busy rate (busy events/executed inst)
-system.cpu1.iq.int_inst_queue_reads 324785513 # Number of integer instruction queue reads
-system.cpu1.iq.int_inst_queue_writes 97548571 # Number of integer instruction queue writes
-system.cpu1.iq.int_inst_queue_wakeup_accesses 61562518 # Number of integer instruction queue wakeup accesses
-system.cpu1.iq.fp_inst_queue_reads 11987 # Number of floating instruction queue reads
-system.cpu1.iq.fp_inst_queue_writes 6778 # Number of floating instruction queue writes
-system.cpu1.iq.fp_inst_queue_wakeup_accesses 5521 # Number of floating instruction queue wakeup accesses
-system.cpu1.iq.int_alu_accesses 106327792 # Number of integer alu accesses
-system.cpu1.iq.fp_alu_accesses 6235 # Number of floating point alu accesses
-system.cpu1.iew.lsq.thread0.forwLoads 430499 # Number of loads that had data forwarded from stores
+system.cpu1.iq.FU_type_0::total 98462898 # Type of FU issued
+system.cpu1.iq.rate 0.272446 # Inst issue rate
+system.cpu1.iq.fu_busy_cnt 8116688 # FU busy when requested
+system.cpu1.iq.fu_busy_rate 0.082434 # FU busy rate (busy events/executed inst)
+system.cpu1.iq.int_inst_queue_reads 325251459 # Number of integer instruction queue reads
+system.cpu1.iq.int_inst_queue_writes 97743765 # Number of integer instruction queue writes
+system.cpu1.iq.int_inst_queue_wakeup_accesses 61686980 # Number of integer instruction queue wakeup accesses
+system.cpu1.iq.fp_inst_queue_reads 12182 # Number of floating instruction queue reads
+system.cpu1.iq.fp_inst_queue_writes 6832 # Number of floating instruction queue writes
+system.cpu1.iq.fp_inst_queue_wakeup_accesses 5554 # Number of floating instruction queue wakeup accesses
+system.cpu1.iq.int_alu_accesses 106480420 # Number of integer alu accesses
+system.cpu1.iq.fp_alu_accesses 6347 # Number of floating point alu accesses
+system.cpu1.iew.lsq.thread0.forwLoads 431690 # Number of loads that had data forwarded from stores
system.cpu1.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address
-system.cpu1.iew.lsq.thread0.squashedLoads 4865573 # Number of loads squashed
-system.cpu1.iew.lsq.thread0.ignoredResponses 7656 # Number of memory responses ignored because the instruction is squashed
-system.cpu1.iew.lsq.thread0.memOrderViolation 24407 # Number of memory ordering violations
-system.cpu1.iew.lsq.thread0.squashedStores 1834498 # Number of stores squashed
+system.cpu1.iew.lsq.thread0.squashedLoads 4883583 # Number of loads squashed
+system.cpu1.iew.lsq.thread0.ignoredResponses 7497 # Number of memory responses ignored because the instruction is squashed
+system.cpu1.iew.lsq.thread0.memOrderViolation 24780 # Number of memory ordering violations
+system.cpu1.iew.lsq.thread0.squashedStores 1835710 # Number of stores squashed
system.cpu1.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
system.cpu1.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
-system.cpu1.iew.lsq.thread0.rescheduledLoads 32207869 # Number of loads that were rescheduled
-system.cpu1.iew.lsq.thread0.cacheBlocked 1151172 # Number of times an access to memory failed due to the cache being blocked
+system.cpu1.iew.lsq.thread0.rescheduledLoads 32214526 # Number of loads that were rescheduled
+system.cpu1.iew.lsq.thread0.cacheBlocked 1149867 # Number of times an access to memory failed due to the cache being blocked
system.cpu1.iew.iewIdleCycles 0 # Number of cycles IEW is idle
-system.cpu1.iew.iewSquashCycles 3654917 # Number of cycles IEW is squashing
-system.cpu1.iew.iewBlockCycles 25274079 # Number of cycles IEW is blocking
-system.cpu1.iew.iewUnblockCycles 368524 # Number of cycles IEW is unblocking
-system.cpu1.iew.iewDispatchedInsts 76147540 # Number of instructions dispatched to IQ
-system.cpu1.iew.iewDispSquashedInsts 230680 # Number of squashed instructions skipped by dispatch
-system.cpu1.iew.iewDispLoadInsts 16023709 # Number of dispatched load instructions
-system.cpu1.iew.iewDispStoreInsts 9632090 # Number of dispatched store instructions
-system.cpu1.iew.iewDispNonSpecInsts 636792 # Number of dispatched non-speculative instructions
-system.cpu1.iew.iewIQFullEvents 64221 # Number of times the IQ has become full, causing a stall
-system.cpu1.iew.iewLSQFullEvents 8659 # Number of times the LSQ has become full, causing a stall
-system.cpu1.iew.memOrderViolationEvents 24407 # Number of memory order violations
-system.cpu1.iew.predictedTakenIncorrect 397735 # Number of branches that were predicted taken incorrectly
-system.cpu1.iew.predictedNotTakenIncorrect 243587 # Number of branches that were predicted not taken incorrectly
-system.cpu1.iew.branchMispredicts 641322 # Number of branch mispredicts detected at execute
-system.cpu1.iew.iewExecutedInsts 95426692 # Number of executed instructions
-system.cpu1.iew.iewExecLoadInsts 45740593 # Number of load instructions executed
-system.cpu1.iew.iewExecSquashedInsts 2894421 # Number of squashed instructions skipped in execute
+system.cpu1.iew.iewSquashCycles 3662422 # Number of cycles IEW is squashing
+system.cpu1.iew.iewBlockCycles 25277331 # Number of cycles IEW is blocking
+system.cpu1.iew.iewUnblockCycles 367624 # Number of cycles IEW is unblocking
+system.cpu1.iew.iewDispatchedInsts 76304263 # Number of instructions dispatched to IQ
+system.cpu1.iew.iewDispSquashedInsts 229674 # Number of squashed instructions skipped by dispatch
+system.cpu1.iew.iewDispLoadInsts 16066963 # Number of dispatched load instructions
+system.cpu1.iew.iewDispStoreInsts 9656417 # Number of dispatched store instructions
+system.cpu1.iew.iewDispNonSpecInsts 636963 # Number of dispatched non-speculative instructions
+system.cpu1.iew.iewIQFullEvents 63488 # Number of times the IQ has become full, causing a stall
+system.cpu1.iew.iewLSQFullEvents 8504 # Number of times the LSQ has become full, causing a stall
+system.cpu1.iew.memOrderViolationEvents 24780 # Number of memory order violations
+system.cpu1.iew.predictedTakenIncorrect 400468 # Number of branches that were predicted taken incorrectly
+system.cpu1.iew.predictedNotTakenIncorrect 244624 # Number of branches that were predicted not taken incorrectly
+system.cpu1.iew.branchMispredicts 645092 # Number of branch mispredicts detected at execute
+system.cpu1.iew.iewExecutedInsts 95561838 # Number of executed instructions
+system.cpu1.iew.iewExecLoadInsts 45782046 # Number of load instructions executed
+system.cpu1.iew.iewExecSquashedInsts 2901060 # Number of squashed instructions skipped in execute
system.cpu1.iew.exec_swp 0 # number of swp insts executed
-system.cpu1.iew.exec_nop 208805 # number of nop insts executed
-system.cpu1.iew.exec_refs 54014697 # number of memory reference insts executed
-system.cpu1.iew.exec_branches 8051531 # Number of branches executed
-system.cpu1.iew.exec_stores 8274104 # Number of stores executed
-system.cpu1.iew.exec_rate 0.264132 # Inst execution rate
-system.cpu1.iew.wb_sent 94059839 # cumulative count of insts sent to commit
-system.cpu1.iew.wb_count 61568039 # cumulative count of insts written-back
-system.cpu1.iew.wb_producers 33920997 # num instructions producing a value
-system.cpu1.iew.wb_consumers 61750617 # num instructions consuming a value
+system.cpu1.iew.exec_nop 209789 # number of nop insts executed
+system.cpu1.iew.exec_refs 54078244 # number of memory reference insts executed
+system.cpu1.iew.exec_branches 8068913 # Number of branches executed
+system.cpu1.iew.exec_stores 8296198 # Number of stores executed
+system.cpu1.iew.exec_rate 0.264419 # Inst execution rate
+system.cpu1.iew.wb_sent 94191755 # cumulative count of insts sent to commit
+system.cpu1.iew.wb_count 61692534 # cumulative count of insts written-back
+system.cpu1.iew.wb_producers 33977338 # num instructions producing a value
+system.cpu1.iew.wb_consumers 61891561 # num instructions consuming a value
system.cpu1.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ
-system.cpu1.iew.wb_rate 0.170414 # insts written-back per cycle
-system.cpu1.iew.wb_fanout 0.549322 # average fanout of values written-back
+system.cpu1.iew.wb_rate 0.170703 # insts written-back per cycle
+system.cpu1.iew.wb_fanout 0.548982 # average fanout of values written-back
system.cpu1.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ
-system.cpu1.commit.commitCommittedInsts 42291661 # The number of committed instructions
-system.cpu1.commit.commitCommittedOps 53866202 # The number of committed instructions
-system.cpu1.commit.commitSquashedInsts 22216320 # The number of squashed insts skipped by commit
-system.cpu1.commit.commitNonSpecStalls 807429 # The number of times commit has been forced to stall to communicate backwards
-system.cpu1.commit.branchMispredicts 565831 # The number of times a branch was mispredicted
-system.cpu1.commit.committed_per_cycle::samples 116206088 # Number of insts commited each cycle
-system.cpu1.commit.committed_per_cycle::mean 0.463540 # Number of insts commited each cycle
-system.cpu1.commit.committed_per_cycle::stdev 1.434749 # Number of insts commited each cycle
+system.cpu1.commit.commitCommittedInsts 42383808 # The number of committed instructions
+system.cpu1.commit.commitCommittedOps 53979911 # The number of committed instructions
+system.cpu1.commit.commitSquashedInsts 22261112 # The number of squashed insts skipped by commit
+system.cpu1.commit.commitNonSpecStalls 807843 # The number of times commit has been forced to stall to communicate backwards
+system.cpu1.commit.branchMispredicts 569017 # The number of times a branch was mispredicted
+system.cpu1.commit.committed_per_cycle::samples 116371049 # Number of insts commited each cycle
+system.cpu1.commit.committed_per_cycle::mean 0.463860 # Number of insts commited each cycle
+system.cpu1.commit.committed_per_cycle::stdev 1.434767 # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle
-system.cpu1.commit.committed_per_cycle::0 97183761 83.63% 83.63% # Number of insts commited each cycle
-system.cpu1.commit.committed_per_cycle::1 9338835 8.04% 91.67% # Number of insts commited each cycle
-system.cpu1.commit.committed_per_cycle::2 2558958 2.20% 93.87% # Number of insts commited each cycle
-system.cpu1.commit.committed_per_cycle::3 1577703 1.36% 95.23% # Number of insts commited each cycle
-system.cpu1.commit.committed_per_cycle::4 1195507 1.03% 96.26% # Number of insts commited each cycle
-system.cpu1.commit.committed_per_cycle::5 711645 0.61% 96.87% # Number of insts commited each cycle
-system.cpu1.commit.committed_per_cycle::6 1133703 0.98% 97.84% # Number of insts commited each cycle
-system.cpu1.commit.committed_per_cycle::7 513937 0.44% 98.29% # Number of insts commited each cycle
-system.cpu1.commit.committed_per_cycle::8 1992039 1.71% 100.00% # Number of insts commited each cycle
+system.cpu1.commit.committed_per_cycle::0 97273421 83.59% 83.59% # Number of insts commited each cycle
+system.cpu1.commit.committed_per_cycle::1 9394437 8.07% 91.66% # Number of insts commited each cycle
+system.cpu1.commit.committed_per_cycle::2 2575050 2.21% 93.87% # Number of insts commited each cycle
+system.cpu1.commit.committed_per_cycle::3 1580988 1.36% 95.23% # Number of insts commited each cycle
+system.cpu1.commit.committed_per_cycle::4 1207821 1.04% 96.27% # Number of insts commited each cycle
+system.cpu1.commit.committed_per_cycle::5 698590 0.60% 96.87% # Number of insts commited each cycle
+system.cpu1.commit.committed_per_cycle::6 1120414 0.96% 97.83% # Number of insts commited each cycle
+system.cpu1.commit.committed_per_cycle::7 516932 0.44% 98.28% # Number of insts commited each cycle
+system.cpu1.commit.committed_per_cycle::8 2003396 1.72% 100.00% # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle
-system.cpu1.commit.committed_per_cycle::total 116206088 # Number of insts commited each cycle
-system.cpu1.commit.committedInsts 42291661 # Number of instructions committed
-system.cpu1.commit.committedOps 53866202 # Number of ops (including micro ops) committed
+system.cpu1.commit.committed_per_cycle::total 116371049 # Number of insts commited each cycle
+system.cpu1.commit.committedInsts 42383808 # Number of instructions committed
+system.cpu1.commit.committedOps 53979911 # Number of ops (including micro ops) committed
system.cpu1.commit.swp_count 0 # Number of s/w prefetches committed
-system.cpu1.commit.refs 18955728 # Number of memory references committed
-system.cpu1.commit.loads 11158136 # Number of loads committed
-system.cpu1.commit.membars 242500 # Number of memory barriers committed
-system.cpu1.commit.branches 6770430 # Number of branches committed
+system.cpu1.commit.refs 19004087 # Number of memory references committed
+system.cpu1.commit.loads 11183380 # Number of loads committed
+system.cpu1.commit.membars 242516 # Number of memory barriers committed
+system.cpu1.commit.branches 6784179 # Number of branches committed
system.cpu1.commit.fp_insts 5428 # Number of committed floating point instructions.
-system.cpu1.commit.int_insts 47963823 # Number of committed integer instructions.
-system.cpu1.commit.function_calls 631876 # Number of function calls committed.
-system.cpu1.commit.bw_lim_events 1992039 # number cycles where commit BW limit reached
+system.cpu1.commit.int_insts 48067133 # Number of committed integer instructions.
+system.cpu1.commit.function_calls 633379 # Number of function calls committed.
+system.cpu1.commit.bw_lim_events 2003396 # number cycles where commit BW limit reached
system.cpu1.commit.bw_limited 0 # number of insts not committed due to BW limits
-system.cpu1.rob.rob_reads 189074073 # The number of ROB reads
-system.cpu1.rob.rob_writes 155943577 # The number of ROB writes
-system.cpu1.timesIdled 1562911 # Number of times that the entire CPU went into an idle state and unscheduled itself
-system.cpu1.idleCycles 241479474 # Total number of cycles that the CPU has spent unscheduled due to idling
-system.cpu1.quiesceCycles 4780310719 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
-system.cpu1.committedInsts 42165834 # Number of Instructions Simulated
-system.cpu1.committedOps 53740375 # Number of Ops (including micro ops) Simulated
-system.cpu1.committedInsts_total 42165834 # Number of Instructions Simulated
-system.cpu1.cpi 8.568183 # CPI: Cycles Per Instruction
-system.cpu1.cpi_total 8.568183 # CPI: Total CPI of All Threads
-system.cpu1.ipc 0.116711 # IPC: Instructions Per Cycle
-system.cpu1.ipc_total 0.116711 # IPC: Total IPC of All Threads
-system.cpu1.int_regfile_reads 429426444 # number of integer regfile reads
-system.cpu1.int_regfile_writes 64384425 # number of integer regfile writes
-system.cpu1.fp_regfile_reads 4325 # number of floating regfile reads
-system.cpu1.fp_regfile_writes 2046 # number of floating regfile writes
-system.cpu1.misc_regfile_reads 102104658 # number of misc regfile reads
-system.cpu1.misc_regfile_writes 512737 # number of misc regfile writes
-system.cpu1.icache.replacements 711552 # number of replacements
-system.cpu1.icache.tagsinuse 498.766119 # Cycle average of tags in use
-system.cpu1.icache.total_refs 9643450 # Total number of references to valid blocks.
-system.cpu1.icache.sampled_refs 712064 # Sample count of references to valid blocks.
-system.cpu1.icache.avg_refs 13.542954 # Average number of references to valid blocks.
-system.cpu1.icache.warmup_cycle 74281042000 # Cycle when the warmup percentage was hit.
-system.cpu1.icache.occ_blocks::cpu1.inst 498.766119 # Average occupied blocks per requestor
-system.cpu1.icache.occ_percent::cpu1.inst 0.974153 # Average percentage of cache occupancy
-system.cpu1.icache.occ_percent::total 0.974153 # Average percentage of cache occupancy
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system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst inf # average ReadReq mshr uncacheable latency
system.cpu1.icache.overall_avg_mshr_uncacheable_latency::cpu1.inst inf # average overall mshr uncacheable latency
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+system.cpu1.dcache.StoreCondReq_hits::total 120021 # number of StoreCondReq hits
+system.cpu1.dcache.demand_hits::cpu1.data 14946486 # number of demand (read+write) hits
+system.cpu1.dcache.demand_hits::total 14946486 # number of demand (read+write) hits
+system.cpu1.dcache.overall_hits::cpu1.data 14946486 # number of overall hits
+system.cpu1.dcache.overall_hits::total 14946486 # number of overall hits
+system.cpu1.dcache.ReadReq_misses::cpu1.data 473003 # number of ReadReq misses
+system.cpu1.dcache.ReadReq_misses::total 473003 # number of ReadReq misses
+system.cpu1.dcache.WriteReq_misses::cpu1.data 1726377 # number of WriteReq misses
+system.cpu1.dcache.WriteReq_misses::total 1726377 # number of WriteReq misses
+system.cpu1.dcache.LoadLockedReq_misses::cpu1.data 14767 # number of LoadLockedReq misses
+system.cpu1.dcache.LoadLockedReq_misses::total 14767 # number of LoadLockedReq misses
+system.cpu1.dcache.StoreCondReq_misses::cpu1.data 10580 # number of StoreCondReq misses
+system.cpu1.dcache.StoreCondReq_misses::total 10580 # number of StoreCondReq misses
+system.cpu1.dcache.demand_misses::cpu1.data 2199380 # number of demand (read+write) misses
+system.cpu1.dcache.demand_misses::total 2199380 # number of demand (read+write) misses
+system.cpu1.dcache.overall_misses::cpu1.data 2199380 # number of overall misses
+system.cpu1.dcache.overall_misses::total 2199380 # number of overall misses
+system.cpu1.dcache.ReadReq_miss_latency::cpu1.data 7143574500 # number of ReadReq miss cycles
+system.cpu1.dcache.ReadReq_miss_latency::total 7143574500 # number of ReadReq miss cycles
+system.cpu1.dcache.WriteReq_miss_latency::cpu1.data 57173185397 # number of WriteReq miss cycles
+system.cpu1.dcache.WriteReq_miss_latency::total 57173185397 # number of WriteReq miss cycles
+system.cpu1.dcache.LoadLockedReq_miss_latency::cpu1.data 177446500 # number of LoadLockedReq miss cycles
+system.cpu1.dcache.LoadLockedReq_miss_latency::total 177446500 # number of LoadLockedReq miss cycles
+system.cpu1.dcache.StoreCondReq_miss_latency::cpu1.data 91928500 # number of StoreCondReq miss cycles
+system.cpu1.dcache.StoreCondReq_miss_latency::total 91928500 # number of StoreCondReq miss cycles
+system.cpu1.dcache.demand_miss_latency::cpu1.data 64316759897 # number of demand (read+write) miss cycles
+system.cpu1.dcache.demand_miss_latency::total 64316759897 # number of demand (read+write) miss cycles
+system.cpu1.dcache.overall_miss_latency::cpu1.data 64316759897 # number of overall miss cycles
+system.cpu1.dcache.overall_miss_latency::total 64316759897 # number of overall miss cycles
+system.cpu1.dcache.ReadReq_accesses::cpu1.data 10530495 # number of ReadReq accesses(hits+misses)
+system.cpu1.dcache.ReadReq_accesses::total 10530495 # number of ReadReq accesses(hits+misses)
+system.cpu1.dcache.WriteReq_accesses::cpu1.data 6615371 # number of WriteReq accesses(hits+misses)
+system.cpu1.dcache.WriteReq_accesses::total 6615371 # number of WriteReq accesses(hits+misses)
+system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data 141213 # number of LoadLockedReq accesses(hits+misses)
+system.cpu1.dcache.LoadLockedReq_accesses::total 141213 # number of LoadLockedReq accesses(hits+misses)
+system.cpu1.dcache.StoreCondReq_accesses::cpu1.data 130601 # number of StoreCondReq accesses(hits+misses)
+system.cpu1.dcache.StoreCondReq_accesses::total 130601 # number of StoreCondReq accesses(hits+misses)
+system.cpu1.dcache.demand_accesses::cpu1.data 17145866 # number of demand (read+write) accesses
+system.cpu1.dcache.demand_accesses::total 17145866 # number of demand (read+write) accesses
+system.cpu1.dcache.overall_accesses::cpu1.data 17145866 # number of overall (read+write) accesses
+system.cpu1.dcache.overall_accesses::total 17145866 # number of overall (read+write) accesses
+system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.044917 # miss rate for ReadReq accesses
+system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.260965 # miss rate for WriteReq accesses
+system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data 0.104573 # miss rate for LoadLockedReq accesses
+system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data 0.081010 # miss rate for StoreCondReq accesses
+system.cpu1.dcache.demand_miss_rate::cpu1.data 0.128275 # miss rate for demand accesses
+system.cpu1.dcache.overall_miss_rate::cpu1.data 0.128275 # miss rate for overall accesses
+system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 15102.598715 # average ReadReq miss latency
+system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 33117.439237 # average WriteReq miss latency
+system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 12016.421751 # average LoadLockedReq miss latency
+system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.data 8688.894140 # average StoreCondReq miss latency
+system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 29243.132109 # average overall miss latency
+system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 29243.132109 # average overall miss latency
+system.cpu1.dcache.blocked_cycles::no_mshrs 15169067 # number of cycles access was blocked
+system.cpu1.dcache.blocked_cycles::no_targets 5303000 # number of cycles access was blocked
+system.cpu1.dcache.blocked::no_mshrs 3226 # number of cycles access was blocked
+system.cpu1.dcache.blocked::no_targets 149 # number of cycles access was blocked
+system.cpu1.dcache.avg_blocked_cycles::no_mshrs 4702.128642 # average number of cycles each access was blocked
+system.cpu1.dcache.avg_blocked_cycles::no_targets 35590.604027 # average number of cycles each access was blocked
system.cpu1.dcache.fast_writes 0 # number of fast writes performed
system.cpu1.dcache.cache_copies 0 # number of cache copies performed
-system.cpu1.dcache.writebacks::writebacks 345826 # number of writebacks
-system.cpu1.dcache.writebacks::total 345826 # number of writebacks
-system.cpu1.dcache.ReadReq_mshr_hits::cpu1.data 203766 # number of ReadReq MSHR hits
-system.cpu1.dcache.ReadReq_mshr_hits::total 203766 # number of ReadReq MSHR hits
-system.cpu1.dcache.WriteReq_mshr_hits::cpu1.data 1549585 # number of WriteReq MSHR hits
-system.cpu1.dcache.WriteReq_mshr_hits::total 1549585 # number of WriteReq MSHR hits
-system.cpu1.dcache.LoadLockedReq_mshr_hits::cpu1.data 1246 # number of LoadLockedReq MSHR hits
-system.cpu1.dcache.LoadLockedReq_mshr_hits::total 1246 # number of LoadLockedReq MSHR hits
-system.cpu1.dcache.demand_mshr_hits::cpu1.data 1753351 # number of demand (read+write) MSHR hits
-system.cpu1.dcache.demand_mshr_hits::total 1753351 # number of demand (read+write) MSHR hits
-system.cpu1.dcache.overall_mshr_hits::cpu1.data 1753351 # number of overall MSHR hits
-system.cpu1.dcache.overall_mshr_hits::total 1753351 # number of overall MSHR hits
-system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data 270190 # number of ReadReq MSHR misses
-system.cpu1.dcache.ReadReq_mshr_misses::total 270190 # number of ReadReq MSHR misses
-system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data 177184 # number of WriteReq MSHR misses
-system.cpu1.dcache.WriteReq_mshr_misses::total 177184 # number of WriteReq MSHR misses
-system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.data 13416 # number of LoadLockedReq MSHR misses
-system.cpu1.dcache.LoadLockedReq_mshr_misses::total 13416 # number of LoadLockedReq MSHR misses
-system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.data 10560 # number of StoreCondReq MSHR misses
-system.cpu1.dcache.StoreCondReq_mshr_misses::total 10560 # number of StoreCondReq MSHR misses
-system.cpu1.dcache.demand_mshr_misses::cpu1.data 447374 # number of demand (read+write) MSHR misses
-system.cpu1.dcache.demand_mshr_misses::total 447374 # number of demand (read+write) MSHR misses
-system.cpu1.dcache.overall_mshr_misses::cpu1.data 447374 # number of overall MSHR misses
-system.cpu1.dcache.overall_mshr_misses::total 447374 # number of overall MSHR misses
-system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 3410102500 # number of ReadReq MSHR miss cycles
-system.cpu1.dcache.ReadReq_mshr_miss_latency::total 3410102500 # number of ReadReq MSHR miss cycles
-system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 5540518545 # number of WriteReq MSHR miss cycles
-system.cpu1.dcache.WriteReq_mshr_miss_latency::total 5540518545 # number of WriteReq MSHR miss cycles
-system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 120430000 # number of LoadLockedReq MSHR miss cycles
-system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total 120430000 # number of LoadLockedReq MSHR miss cycles
-system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data 60079000 # number of StoreCondReq MSHR miss cycles
-system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total 60079000 # number of StoreCondReq MSHR miss cycles
+system.cpu1.dcache.writebacks::writebacks 346093 # number of writebacks
+system.cpu1.dcache.writebacks::total 346093 # number of writebacks
+system.cpu1.dcache.ReadReq_mshr_hits::cpu1.data 202550 # number of ReadReq MSHR hits
+system.cpu1.dcache.ReadReq_mshr_hits::total 202550 # number of ReadReq MSHR hits
+system.cpu1.dcache.WriteReq_mshr_hits::cpu1.data 1548902 # number of WriteReq MSHR hits
+system.cpu1.dcache.WriteReq_mshr_hits::total 1548902 # number of WriteReq MSHR hits
+system.cpu1.dcache.LoadLockedReq_mshr_hits::cpu1.data 1254 # number of LoadLockedReq MSHR hits
+system.cpu1.dcache.LoadLockedReq_mshr_hits::total 1254 # number of LoadLockedReq MSHR hits
+system.cpu1.dcache.demand_mshr_hits::cpu1.data 1751452 # number of demand (read+write) MSHR hits
+system.cpu1.dcache.demand_mshr_hits::total 1751452 # number of demand (read+write) MSHR hits
+system.cpu1.dcache.overall_mshr_hits::cpu1.data 1751452 # number of overall MSHR hits
+system.cpu1.dcache.overall_mshr_hits::total 1751452 # number of overall MSHR hits
+system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data 270453 # number of ReadReq MSHR misses
+system.cpu1.dcache.ReadReq_mshr_misses::total 270453 # number of ReadReq MSHR misses
+system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data 177475 # number of WriteReq MSHR misses
+system.cpu1.dcache.WriteReq_mshr_misses::total 177475 # number of WriteReq MSHR misses
+system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.data 13513 # number of LoadLockedReq MSHR misses
+system.cpu1.dcache.LoadLockedReq_mshr_misses::total 13513 # number of LoadLockedReq MSHR misses
+system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.data 10575 # number of StoreCondReq MSHR misses
+system.cpu1.dcache.StoreCondReq_mshr_misses::total 10575 # number of StoreCondReq MSHR misses
+system.cpu1.dcache.demand_mshr_misses::cpu1.data 447928 # number of demand (read+write) MSHR misses
+system.cpu1.dcache.demand_mshr_misses::total 447928 # number of demand (read+write) MSHR misses
+system.cpu1.dcache.overall_mshr_misses::cpu1.data 447928 # number of overall MSHR misses
+system.cpu1.dcache.overall_mshr_misses::total 447928 # number of overall MSHR misses
+system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 3409672000 # number of ReadReq MSHR miss cycles
+system.cpu1.dcache.ReadReq_mshr_miss_latency::total 3409672000 # number of ReadReq MSHR miss cycles
+system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 5551338067 # number of WriteReq MSHR miss cycles
+system.cpu1.dcache.WriteReq_mshr_miss_latency::total 5551338067 # number of WriteReq MSHR miss cycles
+system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 121446000 # number of LoadLockedReq MSHR miss cycles
+system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total 121446000 # number of LoadLockedReq MSHR miss cycles
+system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data 60146500 # number of StoreCondReq MSHR miss cycles
+system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total 60146500 # number of StoreCondReq MSHR miss cycles
system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::cpu1.data 1000 # number of StoreCondFailReq MSHR miss cycles
system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::total 1000 # number of StoreCondFailReq MSHR miss cycles
-system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 8950621045 # number of demand (read+write) MSHR miss cycles
-system.cpu1.dcache.demand_mshr_miss_latency::total 8950621045 # number of demand (read+write) MSHR miss cycles
-system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 8950621045 # number of overall MSHR miss cycles
-system.cpu1.dcache.overall_mshr_miss_latency::total 8950621045 # number of overall MSHR miss cycles
-system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 138186102000 # number of ReadReq MSHR uncacheable cycles
-system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total 138186102000 # number of ReadReq MSHR uncacheable cycles
-system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 41660941677 # number of WriteReq MSHR uncacheable cycles
-system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::total 41660941677 # number of WriteReq MSHR uncacheable cycles
-system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data 179847043677 # number of overall MSHR uncacheable cycles
-system.cpu1.dcache.overall_mshr_uncacheable_latency::total 179847043677 # number of overall MSHR uncacheable cycles
-system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.025735 # mshr miss rate for ReadReq accesses
-system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.026852 # mshr miss rate for WriteReq accesses
-system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.094886 # mshr miss rate for LoadLockedReq accesses
-system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.080939 # mshr miss rate for StoreCondReq accesses
-system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.026166 # mshr miss rate for demand accesses
-system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.026166 # mshr miss rate for overall accesses
-system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 12621.127725 # average ReadReq mshr miss latency
-system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 31269.858142 # average WriteReq mshr miss latency
-system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 8976.595110 # average LoadLockedReq mshr miss latency
-system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 5689.299242 # average StoreCondReq mshr miss latency
+system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 8961010067 # number of demand (read+write) MSHR miss cycles
+system.cpu1.dcache.demand_mshr_miss_latency::total 8961010067 # number of demand (read+write) MSHR miss cycles
+system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 8961010067 # number of overall MSHR miss cycles
+system.cpu1.dcache.overall_mshr_miss_latency::total 8961010067 # number of overall MSHR miss cycles
+system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 138179503000 # number of ReadReq MSHR uncacheable cycles
+system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total 138179503000 # number of ReadReq MSHR uncacheable cycles
+system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 41662340533 # number of WriteReq MSHR uncacheable cycles
+system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::total 41662340533 # number of WriteReq MSHR uncacheable cycles
+system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data 179841843533 # number of overall MSHR uncacheable cycles
+system.cpu1.dcache.overall_mshr_uncacheable_latency::total 179841843533 # number of overall MSHR uncacheable cycles
+system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.025683 # mshr miss rate for ReadReq accesses
+system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.026828 # mshr miss rate for WriteReq accesses
+system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.095692 # mshr miss rate for LoadLockedReq accesses
+system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.080972 # mshr miss rate for StoreCondReq accesses
+system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.026125 # mshr miss rate for demand accesses
+system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.026125 # mshr miss rate for overall accesses
+system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 12607.262630 # average ReadReq mshr miss latency
+system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 31279.549610 # average WriteReq mshr miss latency
+system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 8987.345519 # average LoadLockedReq mshr miss latency
+system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 5687.612293 # average StoreCondReq mshr miss latency
system.cpu1.dcache.StoreCondFailReq_avg_mshr_miss_latency::cpu1.data inf # average StoreCondFailReq mshr miss latency
-system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 20007.021072 # average overall mshr miss latency
-system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 20007.021072 # average overall mshr miss latency
+system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 20005.469779 # average overall mshr miss latency
+system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 20005.469779 # average overall mshr miss latency
system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency
system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data inf # average WriteReq mshr uncacheable latency
system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data inf # average overall mshr uncacheable latency
system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.iocache.fast_writes 0 # number of fast writes performed
system.iocache.cache_copies 0 # number of cache copies performed
-system.iocache.ReadReq_mshr_uncacheable_latency::realview.clcd 1308112364906 # number of ReadReq MSHR uncacheable cycles
-system.iocache.ReadReq_mshr_uncacheable_latency::total 1308112364906 # number of ReadReq MSHR uncacheable cycles
-system.iocache.overall_mshr_uncacheable_latency::realview.clcd 1308112364906 # number of overall MSHR uncacheable cycles
-system.iocache.overall_mshr_uncacheable_latency::total 1308112364906 # number of overall MSHR uncacheable cycles
+system.iocache.ReadReq_mshr_uncacheable_latency::realview.clcd 1308180699879 # number of ReadReq MSHR uncacheable cycles
+system.iocache.ReadReq_mshr_uncacheable_latency::total 1308180699879 # number of ReadReq MSHR uncacheable cycles
+system.iocache.overall_mshr_uncacheable_latency::realview.clcd 1308180699879 # number of overall MSHR uncacheable cycles
+system.iocache.overall_mshr_uncacheable_latency::total 1308180699879 # number of overall MSHR uncacheable cycles
system.iocache.ReadReq_avg_mshr_uncacheable_latency::realview.clcd inf # average ReadReq mshr uncacheable latency
system.iocache.overall_avg_mshr_uncacheable_latency::realview.clcd inf # average overall mshr uncacheable latency
system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu0.kern.inst.arm 0 # number of arm instructions executed
-system.cpu0.kern.inst.quiesce 36030 # number of quiesce instructions executed
+system.cpu0.kern.inst.quiesce 36058 # number of quiesce instructions executed
system.cpu1.kern.inst.arm 0 # number of arm instructions executed
-system.cpu1.kern.inst.quiesce 61524 # number of quiesce instructions executed
+system.cpu1.kern.inst.quiesce 61621 # number of quiesce instructions executed
---------- End Simulation Statistics ----------
warn: instruction 'mcr icimvau' unimplemented
warn: LCD dual screen mode not supported
warn: Returning thumbEE disabled for now since we don't support CP14config registers and jumping to ThumbEE vectors
-warn: Returning thumbEE disabled for now since we don't support CP14config registers and jumping to ThumbEE vectors
warn: instruction 'mcr icialluis' unimplemented
warn: instruction 'mcr bpiallis' unimplemented
hack: be nice to actually delete the event here
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
-gem5 compiled May 8 2012 15:17:37
-gem5 started May 8 2012 17:05:43
-gem5 executing on piton
+gem5 compiled May 10 2012 12:36:36
+gem5 started May 10 2012 12:41:59
+gem5 executing on u200540-lin
command line: build/ARM/gem5.opt -d build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview-o3 -re tests/run.py build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview-o3
Global frequency set at 1000000000000 ticks per second
-info: kernel located at: /dist/m5/system/binaries/vmlinux.arm.smp.fb.2.6.38.8
+info: kernel located at: /projects/pd/randd/dist/binaries/vmlinux.arm.smp.fb.2.6.38.8
info: Using bootloader at address 0x80000000
info: Entering event queue @ 0. Starting simulation...
-Exiting @ tick 2501676293500 because m5_exit instruction encountered
+Exiting @ tick 2501685689500 because m5_exit instruction encountered
---------- Begin Simulation Statistics ----------
-sim_seconds 2.501676 # Number of seconds simulated
-sim_ticks 2501676293500 # Number of ticks simulated
-final_tick 2501676293500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_seconds 2.501686 # Number of seconds simulated
+sim_ticks 2501685689500 # Number of ticks simulated
+final_tick 2501685689500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 32202 # Simulator instruction rate (inst/s)
-host_op_rate 41595 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 1355039119 # Simulator tick rate (ticks/s)
-host_mem_usage 388344 # Number of bytes of host memory used
-host_seconds 1846.20 # Real time elapsed on the host
-sim_insts 59451291 # Number of instructions simulated
-sim_ops 76792341 # Number of ops (including micro ops) simulated
-system.physmem.bytes_read 129652968 # Number of bytes read from this memory
-system.physmem.bytes_inst_read 1121024 # Number of instructions bytes read from this memory
-system.physmem.bytes_written 9585096 # Number of bytes written to this memory
-system.physmem.num_reads 14979455 # Number of read requests responded to by this memory
-system.physmem.num_writes 856659 # Number of write requests responded to by this memory
+host_inst_rate 62639 # Simulator instruction rate (inst/s)
+host_op_rate 80877 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 2630163340 # Simulator tick rate (ticks/s)
+host_mem_usage 384244 # Number of bytes of host memory used
+host_seconds 951.15 # Real time elapsed on the host
+sim_insts 59579009 # Number of instructions simulated
+sim_ops 76926775 # Number of ops (including micro ops) simulated
+system.physmem.bytes_read 129658608 # Number of bytes read from this memory
+system.physmem.bytes_inst_read 1119872 # Number of instructions bytes read from this memory
+system.physmem.bytes_written 9585736 # Number of bytes written to this memory
+system.physmem.num_reads 14980335 # Number of read requests responded to by this memory
+system.physmem.num_writes 856669 # Number of write requests responded to by this memory
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+system.cpu.dtb.accesses 64168245 # DTB accesses
+system.cpu.itb.inst_hits 13717584 # ITB inst hits
+system.cpu.itb.inst_misses 12272 # ITB inst misses
system.cpu.itb.read_hits 0 # DTB read hits
system.cpu.itb.read_misses 0 # DTB read misses
system.cpu.itb.write_hits 0 # DTB write hits
system.cpu.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
system.cpu.itb.flush_tlb_mva_asid 1439 # Number of times TLB was flushed by MVA & ASID
system.cpu.itb.flush_tlb_asid 63 # Number of times TLB was flushed by ASID
-system.cpu.itb.flush_entries 2626 # Number of entries that have been flushed from TLB
+system.cpu.itb.flush_entries 2655 # Number of entries that have been flushed from TLB
system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions
system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch
system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions
-system.cpu.itb.perms_faults 6936 # Number of TLB faults due to permissions restrictions
+system.cpu.itb.perms_faults 6863 # Number of TLB faults due to permissions restrictions
system.cpu.itb.read_accesses 0 # DTB read accesses
system.cpu.itb.write_accesses 0 # DTB write accesses
-system.cpu.itb.inst_accesses 13711672 # ITB inst accesses
-system.cpu.itb.hits 13699541 # DTB hits
-system.cpu.itb.misses 12131 # DTB misses
-system.cpu.itb.accesses 13711672 # DTB accesses
-system.cpu.numCycles 411150559 # number of cpu cycles simulated
+system.cpu.itb.inst_accesses 13729856 # ITB inst accesses
+system.cpu.itb.hits 13717584 # DTB hits
+system.cpu.itb.misses 12272 # DTB misses
+system.cpu.itb.accesses 13729856 # DTB accesses
+system.cpu.numCycles 411352060 # number of cpu cycles simulated
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
-system.cpu.BPredUnit.lookups 15631672 # Number of BP lookups
-system.cpu.BPredUnit.condPredicted 12342234 # Number of conditional branches predicted
-system.cpu.BPredUnit.condIncorrect 929456 # Number of conditional branches incorrect
-system.cpu.BPredUnit.BTBLookups 10552810 # Number of BTB lookups
-system.cpu.BPredUnit.BTBHits 8288947 # Number of BTB hits
+system.cpu.BPredUnit.lookups 15654738 # Number of BP lookups
+system.cpu.BPredUnit.condPredicted 12362397 # Number of conditional branches predicted
+system.cpu.BPredUnit.condIncorrect 932839 # Number of conditional branches incorrect
+system.cpu.BPredUnit.BTBLookups 10530768 # Number of BTB lookups
+system.cpu.BPredUnit.BTBHits 8288874 # Number of BTB hits
system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
-system.cpu.BPredUnit.usedRAS 1323523 # Number of times the RAS was used to get a target.
-system.cpu.BPredUnit.RASInCorrect 194787 # Number of incorrect RAS predictions.
-system.cpu.fetch.icacheStallCycles 32982972 # Number of cycles fetch is stalled on an Icache miss
-system.cpu.fetch.Insts 102837345 # Number of instructions fetch has processed
-system.cpu.fetch.Branches 15631672 # Number of branches that fetch encountered
-system.cpu.fetch.predictedBranches 9612470 # Number of branches that fetch has predicted taken
-system.cpu.fetch.Cycles 22590084 # Number of cycles fetch has run and was not squashing or blocked
-system.cpu.fetch.SquashCycles 6692504 # Number of cycles fetch has spent squashing
-system.cpu.fetch.TlbCycles 158663 # Number of cycles fetch has spent waiting for tlb
-system.cpu.fetch.BlockedCycles 89850563 # Number of cycles fetch has spent blocked
-system.cpu.fetch.MiscStallCycles 2746 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
-system.cpu.fetch.PendingTrapStallCycles 143204 # Number of stall cycles due to pending traps
-system.cpu.fetch.PendingQuiesceStallCycles 218934 # Number of stall cycles due to pending quiesce instructions
-system.cpu.fetch.IcacheWaitRetryStallCycles 483 # Number of stall cycles due to full MSHR
-system.cpu.fetch.CacheLines 13691858 # Number of cache lines fetched
-system.cpu.fetch.IcacheSquashes 996334 # Number of outstanding Icache misses that were squashed
-system.cpu.fetch.ItlbSquashes 6838 # Number of outstanding ITLB misses that were squashed
-system.cpu.fetch.rateDist::samples 150553763 # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::mean 0.848436 # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::stdev 2.233477 # Number of instructions fetched each cycle (Total)
+system.cpu.BPredUnit.usedRAS 1329017 # Number of times the RAS was used to get a target.
+system.cpu.BPredUnit.RASInCorrect 195537 # Number of incorrect RAS predictions.
+system.cpu.fetch.icacheStallCycles 33116930 # Number of cycles fetch is stalled on an Icache miss
+system.cpu.fetch.Insts 103031700 # Number of instructions fetch has processed
+system.cpu.fetch.Branches 15654738 # Number of branches that fetch encountered
+system.cpu.fetch.predictedBranches 9617891 # Number of branches that fetch has predicted taken
+system.cpu.fetch.Cycles 22620194 # Number of cycles fetch has run and was not squashing or blocked
+system.cpu.fetch.SquashCycles 6706106 # Number of cycles fetch has spent squashing
+system.cpu.fetch.TlbCycles 163882 # Number of cycles fetch has spent waiting for tlb
+system.cpu.fetch.BlockedCycles 89861042 # Number of cycles fetch has spent blocked
+system.cpu.fetch.MiscStallCycles 2823 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
+system.cpu.fetch.PendingTrapStallCycles 147160 # Number of stall cycles due to pending traps
+system.cpu.fetch.PendingQuiesceStallCycles 218224 # Number of stall cycles due to pending quiesce instructions
+system.cpu.fetch.IcacheWaitRetryStallCycles 462 # Number of stall cycles due to full MSHR
+system.cpu.fetch.CacheLines 13709942 # Number of cache lines fetched
+system.cpu.fetch.IcacheSquashes 998560 # Number of outstanding Icache misses that were squashed
+system.cpu.fetch.ItlbSquashes 6868 # Number of outstanding ITLB misses that were squashed
+system.cpu.fetch.rateDist::samples 150746244 # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::mean 0.848897 # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::stdev 2.234280 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::0 127980574 85.01% 85.01% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::1 1480097 0.98% 85.99% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::2 1855620 1.23% 87.22% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::3 2694532 1.79% 89.01% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::4 1893570 1.26% 90.27% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::5 1188011 0.79% 91.06% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::6 2948135 1.96% 93.02% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::7 848652 0.56% 93.58% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::8 9664572 6.42% 100.00% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::0 128142810 85.01% 85.01% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::1 1478319 0.98% 85.99% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::2 1855018 1.23% 87.22% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::3 2695901 1.79% 89.01% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::4 1893540 1.26% 90.26% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::5 1191101 0.79% 91.05% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::6 2951659 1.96% 93.01% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::7 850848 0.56% 93.57% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::8 9687048 6.43% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::total 150553763 # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.branchRate 0.038019 # Number of branch fetches per cycle
-system.cpu.fetch.rate 0.250121 # Number of inst fetches per cycle
-system.cpu.decode.IdleCycles 35091688 # Number of cycles decode is idle
-system.cpu.decode.BlockedCycles 89690975 # Number of cycles decode is blocked
-system.cpu.decode.RunCycles 20321625 # Number of cycles decode is running
-system.cpu.decode.UnblockCycles 1025705 # Number of cycles decode is unblocking
-system.cpu.decode.SquashCycles 4423770 # Number of cycles decode is squashing
-system.cpu.decode.BranchResolved 2273029 # Number of times decode resolved a branch
-system.cpu.decode.BranchMispred 186320 # Number of times decode detected a branch misprediction
-system.cpu.decode.DecodedInsts 119828190 # Number of instructions handled by decode
-system.cpu.decode.SquashedInsts 605140 # Number of squashed instructions handled by decode
-system.cpu.rename.SquashCycles 4423770 # Number of cycles rename is squashing
-system.cpu.rename.IdleCycles 37165531 # Number of cycles rename is idle
-system.cpu.rename.BlockCycles 37166387 # Number of cycles rename is blocking
-system.cpu.rename.serializeStallCycles 46484492 # count of cycles rename stalled for serializing inst
-system.cpu.rename.RunCycles 19226681 # Number of cycles rename is running
-system.cpu.rename.UnblockCycles 6086902 # Number of cycles rename is unblocking
-system.cpu.rename.RenamedInsts 112339029 # Number of instructions processed by rename
-system.cpu.rename.ROBFullEvents 3754 # Number of times rename has blocked due to ROB full
-system.cpu.rename.IQFullEvents 1012932 # Number of times rename has blocked due to IQ full
-system.cpu.rename.LSQFullEvents 4107831 # Number of times rename has blocked due to LSQ full
-system.cpu.rename.FullRegisterEvents 44905 # Number of times there has been no free registers
-system.cpu.rename.RenamedOperands 116884712 # Number of destination operands rename has renamed
-system.cpu.rename.RenameLookups 516607430 # Number of register rename lookups that rename has made
-system.cpu.rename.int_rename_lookups 516512877 # Number of integer rename lookups
-system.cpu.rename.fp_rename_lookups 94553 # Number of floating rename lookups
-system.cpu.rename.CommittedMaps 77495227 # Number of HB maps that are committed
-system.cpu.rename.UndoneMaps 39389484 # Number of HB maps that are undone due to squashing
-system.cpu.rename.serializingInsts 939636 # count of serializing insts renamed
-system.cpu.rename.tempSerializingInsts 835400 # count of temporary serializing insts renamed
-system.cpu.rename.skidInsts 12435347 # count of insts added to the skid buffer
-system.cpu.memDep0.insertedLoads 21635443 # Number of loads inserted to the mem dependence unit.
-system.cpu.memDep0.insertedStores 14050113 # Number of stores inserted to the mem dependence unit.
-system.cpu.memDep0.conflictingLoads 1939177 # Number of conflicting loads.
-system.cpu.memDep0.conflictingStores 2494760 # Number of conflicting stores.
-system.cpu.iq.iqInstsAdded 102209700 # Number of instructions added to the IQ (excludes non-spec)
-system.cpu.iq.iqNonSpecInstsAdded 1618930 # Number of non-speculative instructions added to the IQ
-system.cpu.iq.iqInstsIssued 126189021 # Number of instructions issued
-system.cpu.iq.iqSquashedInstsIssued 231742 # Number of squashed instructions issued
-system.cpu.iq.iqSquashedInstsExamined 26205661 # Number of squashed instructions iterated over during squash; mainly for profiling
-system.cpu.iq.iqSquashedOperandsExamined 71388624 # Number of squashed operands that are examined and possibly removed from graph
-system.cpu.iq.iqSquashedNonSpecRemoved 331981 # Number of squashed non-spec instructions that were removed
-system.cpu.iq.issued_per_cycle::samples 150553763 # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::mean 0.838166 # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::stdev 1.542583 # Number of insts issued each cycle
+system.cpu.fetch.rateDist::total 150746244 # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.branchRate 0.038057 # Number of branch fetches per cycle
+system.cpu.fetch.rate 0.250471 # Number of inst fetches per cycle
+system.cpu.decode.IdleCycles 35228906 # Number of cycles decode is idle
+system.cpu.decode.BlockedCycles 89710063 # Number of cycles decode is blocked
+system.cpu.decode.RunCycles 20347806 # Number of cycles decode is running
+system.cpu.decode.UnblockCycles 1026685 # Number of cycles decode is unblocking
+system.cpu.decode.SquashCycles 4432784 # Number of cycles decode is squashing
+system.cpu.decode.BranchResolved 2275641 # Number of times decode resolved a branch
+system.cpu.decode.BranchMispred 186729 # Number of times decode detected a branch misprediction
+system.cpu.decode.DecodedInsts 120042439 # Number of instructions handled by decode
+system.cpu.decode.SquashedInsts 604390 # Number of squashed instructions handled by decode
+system.cpu.rename.SquashCycles 4432784 # Number of cycles rename is squashing
+system.cpu.rename.IdleCycles 37305734 # Number of cycles rename is idle
+system.cpu.rename.BlockCycles 37165628 # Number of cycles rename is blocking
+system.cpu.rename.serializeStallCycles 46502465 # count of cycles rename stalled for serializing inst
+system.cpu.rename.RunCycles 19251695 # Number of cycles rename is running
+system.cpu.rename.UnblockCycles 6087938 # Number of cycles rename is unblocking
+system.cpu.rename.RenamedInsts 112539597 # Number of instructions processed by rename
+system.cpu.rename.ROBFullEvents 3873 # Number of times rename has blocked due to ROB full
+system.cpu.rename.IQFullEvents 1013212 # Number of times rename has blocked due to IQ full
+system.cpu.rename.LSQFullEvents 4109157 # Number of times rename has blocked due to LSQ full
+system.cpu.rename.FullRegisterEvents 45575 # Number of times there has been no free registers
+system.cpu.rename.RenamedOperands 117156815 # Number of destination operands rename has renamed
+system.cpu.rename.RenameLookups 517555842 # Number of register rename lookups that rename has made
+system.cpu.rename.int_rename_lookups 517460811 # Number of integer rename lookups
+system.cpu.rename.fp_rename_lookups 95031 # Number of floating rename lookups
+system.cpu.rename.CommittedMaps 77687687 # Number of HB maps that are committed
+system.cpu.rename.UndoneMaps 39469127 # Number of HB maps that are undone due to squashing
+system.cpu.rename.serializingInsts 939790 # count of serializing insts renamed
+system.cpu.rename.tempSerializingInsts 835958 # count of temporary serializing insts renamed
+system.cpu.rename.skidInsts 12443241 # count of insts added to the skid buffer
+system.cpu.memDep0.insertedLoads 21685850 # Number of loads inserted to the mem dependence unit.
+system.cpu.memDep0.insertedStores 14072237 # Number of stores inserted to the mem dependence unit.
+system.cpu.memDep0.conflictingLoads 1938675 # Number of conflicting loads.
+system.cpu.memDep0.conflictingStores 2482763 # Number of conflicting stores.
+system.cpu.iq.iqInstsAdded 102391550 # Number of instructions added to the IQ (excludes non-spec)
+system.cpu.iq.iqNonSpecInstsAdded 1619583 # Number of non-speculative instructions added to the IQ
+system.cpu.iq.iqInstsIssued 126350622 # Number of instructions issued
+system.cpu.iq.iqSquashedInstsIssued 234593 # Number of squashed instructions issued
+system.cpu.iq.iqSquashedInstsExamined 26254924 # Number of squashed instructions iterated over during squash; mainly for profiling
+system.cpu.iq.iqSquashedOperandsExamined 71509700 # Number of squashed operands that are examined and possibly removed from graph
+system.cpu.iq.iqSquashedNonSpecRemoved 332277 # Number of squashed non-spec instructions that were removed
+system.cpu.iq.issued_per_cycle::samples 150746244 # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::mean 0.838168 # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::stdev 1.542455 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::0 105343416 69.97% 69.97% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::1 14065037 9.34% 79.31% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::2 7354541 4.88% 84.20% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::3 5909522 3.93% 88.12% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::4 12758140 8.47% 96.60% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::5 2807768 1.86% 98.46% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::6 1730475 1.15% 99.61% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::7 446826 0.30% 99.91% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::8 138038 0.09% 100.00% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::0 105470655 69.97% 69.97% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::1 14086510 9.34% 79.31% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::2 7371222 4.89% 84.20% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::3 5923402 3.93% 88.13% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::4 12762751 8.47% 96.60% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::5 2810704 1.86% 98.46% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::6 1735902 1.15% 99.61% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::7 449258 0.30% 99.91% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::8 135840 0.09% 100.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::total 150553763 # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::total 150746244 # Number of insts issued each cycle
system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntAlu 60599 0.68% 0.68% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntMult 2 0.00% 0.68% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntDiv 0 0.00% 0.68% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatAdd 0 0.00% 0.68% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatCmp 0 0.00% 0.68% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatCvt 0 0.00% 0.68% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatMult 0 0.00% 0.68% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatDiv 0 0.00% 0.68% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatSqrt 0 0.00% 0.68% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAdd 0 0.00% 0.68% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 0.68% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAlu 0 0.00% 0.68% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdCmp 0 0.00% 0.68% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdCvt 0 0.00% 0.68% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMisc 0 0.00% 0.68% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMult 0 0.00% 0.68% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 0.68% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdShift 0 0.00% 0.68% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 0.68% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdSqrt 0 0.00% 0.68% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 0.68% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 0.68% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 0.68% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 0.68% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 0.68% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 0.68% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 0.68% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 0.68% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 0.68% # attempts to use FU when none available
-system.cpu.iq.fu_full::MemRead 8416262 94.64% 95.32% # attempts to use FU when none available
-system.cpu.iq.fu_full::MemWrite 416317 4.68% 100.00% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntAlu 61043 0.69% 0.69% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntMult 4 0.00% 0.69% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntDiv 0 0.00% 0.69% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatAdd 0 0.00% 0.69% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatCmp 0 0.00% 0.69% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatCvt 0 0.00% 0.69% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatMult 0 0.00% 0.69% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatDiv 0 0.00% 0.69% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatSqrt 0 0.00% 0.69% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAdd 0 0.00% 0.69% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 0.69% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAlu 0 0.00% 0.69% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdCmp 0 0.00% 0.69% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdCvt 0 0.00% 0.69% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMisc 0 0.00% 0.69% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMult 0 0.00% 0.69% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 0.69% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdShift 0 0.00% 0.69% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 0.69% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdSqrt 0 0.00% 0.69% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 0.69% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 0.69% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 0.69% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 0.69% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 0.69% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 0.69% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 0.69% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 0.69% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 0.69% # attempts to use FU when none available
+system.cpu.iq.fu_full::MemRead 8421186 94.66% 95.34% # attempts to use FU when none available
+system.cpu.iq.fu_full::MemWrite 414230 4.66% 100.00% # attempts to use FU when none available
system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available
system.cpu.iq.FU_type_0::No_OpClass 106530 0.08% 0.08% # Type of FU issued
-system.cpu.iq.FU_type_0::IntAlu 59665616 47.28% 47.37% # Type of FU issued
-system.cpu.iq.FU_type_0::IntMult 95635 0.08% 47.44% # Type of FU issued
-system.cpu.iq.FU_type_0::IntDiv 0 0.00% 47.44% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 47.44% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 47.44% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 47.44% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatMult 0 0.00% 47.44% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 47.44% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 47.44% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 47.44% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 47.44% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 47.44% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 47.44% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 47.44% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdMisc 36 0.00% 47.44% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdMult 0 0.00% 47.44% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 47.44% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdShift 48 0.00% 47.44% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdShiftAcc 9 0.00% 47.44% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 47.44% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 47.44% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 47.44% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 47.44% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 47.44% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 47.44% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatMisc 2270 0.00% 47.44% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 47.44% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatMultAcc 9 0.00% 47.44% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 47.44% # Type of FU issued
-system.cpu.iq.FU_type_0::MemRead 53732100 42.58% 90.03% # Type of FU issued
-system.cpu.iq.FU_type_0::MemWrite 12586768 9.97% 100.00% # Type of FU issued
+system.cpu.iq.FU_type_0::IntAlu 59762768 47.30% 47.38% # Type of FU issued
+system.cpu.iq.FU_type_0::IntMult 95812 0.08% 47.46% # Type of FU issued
+system.cpu.iq.FU_type_0::IntDiv 0 0.00% 47.46% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 47.46% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 47.46% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 47.46% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatMult 0 0.00% 47.46% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 47.46% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 47.46% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 47.46% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 47.46% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 47.46% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 47.46% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 47.46% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdMisc 38 0.00% 47.46% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdMult 0 0.00% 47.46% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 47.46% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdShift 45 0.00% 47.46% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdShiftAcc 9 0.00% 47.46% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 47.46% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 47.46% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 47.46% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 47.46% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 47.46% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 47.46% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatMisc 2279 0.00% 47.46% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 47.46% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatMultAcc 9 0.00% 47.46% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 47.46% # Type of FU issued
+system.cpu.iq.FU_type_0::MemRead 53776494 42.56% 90.02% # Type of FU issued
+system.cpu.iq.FU_type_0::MemWrite 12606638 9.98% 100.00% # Type of FU issued
system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued
system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued
-system.cpu.iq.FU_type_0::total 126189021 # Type of FU issued
-system.cpu.iq.rate 0.306917 # Inst issue rate
-system.cpu.iq.fu_busy_cnt 8893180 # FU busy when requested
-system.cpu.iq.fu_busy_rate 0.070475 # FU busy rate (busy events/executed inst)
-system.cpu.iq.int_inst_queue_reads 412149363 # Number of integer instruction queue reads
-system.cpu.iq.int_inst_queue_writes 130053896 # Number of integer instruction queue writes
-system.cpu.iq.int_inst_queue_wakeup_accesses 86886822 # Number of integer instruction queue wakeup accesses
-system.cpu.iq.fp_inst_queue_reads 24048 # Number of floating instruction queue reads
-system.cpu.iq.fp_inst_queue_writes 13080 # Number of floating instruction queue writes
-system.cpu.iq.fp_inst_queue_wakeup_accesses 10409 # Number of floating instruction queue wakeup accesses
-system.cpu.iq.int_alu_accesses 134962848 # Number of integer alu accesses
-system.cpu.iq.fp_alu_accesses 12823 # Number of floating point alu accesses
-system.cpu.iew.lsq.thread0.forwLoads 636825 # Number of loads that had data forwarded from stores
+system.cpu.iq.FU_type_0::total 126350622 # Type of FU issued
+system.cpu.iq.rate 0.307159 # Inst issue rate
+system.cpu.iq.fu_busy_cnt 8896463 # FU busy when requested
+system.cpu.iq.fu_busy_rate 0.070411 # FU busy rate (busy events/executed inst)
+system.cpu.iq.int_inst_queue_reads 412671946 # Number of integer instruction queue reads
+system.cpu.iq.int_inst_queue_writes 130285978 # Number of integer instruction queue writes
+system.cpu.iq.int_inst_queue_wakeup_accesses 87040433 # Number of integer instruction queue wakeup accesses
+system.cpu.iq.fp_inst_queue_reads 24078 # Number of floating instruction queue reads
+system.cpu.iq.fp_inst_queue_writes 13182 # Number of floating instruction queue writes
+system.cpu.iq.fp_inst_queue_wakeup_accesses 10434 # Number of floating instruction queue wakeup accesses
+system.cpu.iq.int_alu_accesses 135127716 # Number of integer alu accesses
+system.cpu.iq.fp_alu_accesses 12839 # Number of floating point alu accesses
+system.cpu.iew.lsq.thread0.forwLoads 636069 # Number of loads that had data forwarded from stores
system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address
-system.cpu.iew.lsq.thread0.squashedLoads 5953964 # Number of loads squashed
-system.cpu.iew.lsq.thread0.ignoredResponses 11249 # Number of memory responses ignored because the instruction is squashed
-system.cpu.iew.lsq.thread0.memOrderViolation 33793 # Number of memory ordering violations
-system.cpu.iew.lsq.thread0.squashedStores 2270680 # Number of stores squashed
+system.cpu.iew.lsq.thread0.squashedLoads 5970496 # Number of loads squashed
+system.cpu.iew.lsq.thread0.ignoredResponses 11101 # Number of memory responses ignored because the instruction is squashed
+system.cpu.iew.lsq.thread0.memOrderViolation 34253 # Number of memory ordering violations
+system.cpu.iew.lsq.thread0.squashedStores 2273952 # Number of stores squashed
system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
-system.cpu.iew.lsq.thread0.rescheduledLoads 34115287 # Number of loads that were rescheduled
-system.cpu.iew.lsq.thread0.cacheBlocked 1151875 # Number of times an access to memory failed due to the cache being blocked
+system.cpu.iew.lsq.thread0.rescheduledLoads 34114355 # Number of loads that were rescheduled
+system.cpu.iew.lsq.thread0.cacheBlocked 1152098 # Number of times an access to memory failed due to the cache being blocked
system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle
-system.cpu.iew.iewSquashCycles 4423770 # Number of cycles IEW is squashing
-system.cpu.iew.iewBlockCycles 28606306 # Number of cycles IEW is blocking
-system.cpu.iew.iewUnblockCycles 435959 # Number of cycles IEW is unblocking
-system.cpu.iew.iewDispatchedInsts 104089793 # Number of instructions dispatched to IQ
-system.cpu.iew.iewDispSquashedInsts 334839 # Number of squashed instructions skipped by dispatch
-system.cpu.iew.iewDispLoadInsts 21635443 # Number of dispatched load instructions
-system.cpu.iew.iewDispStoreInsts 14050113 # Number of dispatched store instructions
-system.cpu.iew.iewDispNonSpecInsts 991881 # Number of dispatched non-speculative instructions
-system.cpu.iew.iewIQFullEvents 95881 # Number of times the IQ has become full, causing a stall
-system.cpu.iew.iewLSQFullEvents 11592 # Number of times the LSQ has become full, causing a stall
-system.cpu.iew.memOrderViolationEvents 33793 # Number of memory order violations
-system.cpu.iew.predictedTakenIncorrect 550966 # Number of branches that were predicted taken incorrectly
-system.cpu.iew.predictedNotTakenIncorrect 345374 # Number of branches that were predicted not taken incorrectly
-system.cpu.iew.branchMispredicts 896340 # Number of branch mispredicts detected at execute
-system.cpu.iew.iewExecutedInsts 122956903 # Number of executed instructions
-system.cpu.iew.iewExecLoadInsts 52760819 # Number of load instructions executed
-system.cpu.iew.iewExecSquashedInsts 3232118 # Number of squashed instructions skipped in execute
+system.cpu.iew.iewSquashCycles 4432784 # Number of cycles IEW is squashing
+system.cpu.iew.iewBlockCycles 28604721 # Number of cycles IEW is blocking
+system.cpu.iew.iewUnblockCycles 436722 # Number of cycles IEW is unblocking
+system.cpu.iew.iewDispatchedInsts 104273041 # Number of instructions dispatched to IQ
+system.cpu.iew.iewDispSquashedInsts 335924 # Number of squashed instructions skipped by dispatch
+system.cpu.iew.iewDispLoadInsts 21685850 # Number of dispatched load instructions
+system.cpu.iew.iewDispStoreInsts 14072237 # Number of dispatched store instructions
+system.cpu.iew.iewDispNonSpecInsts 992808 # Number of dispatched non-speculative instructions
+system.cpu.iew.iewIQFullEvents 95700 # Number of times the IQ has become full, causing a stall
+system.cpu.iew.iewLSQFullEvents 11591 # Number of times the LSQ has become full, causing a stall
+system.cpu.iew.memOrderViolationEvents 34253 # Number of memory order violations
+system.cpu.iew.predictedTakenIncorrect 552378 # Number of branches that were predicted taken incorrectly
+system.cpu.iew.predictedNotTakenIncorrect 346914 # Number of branches that were predicted not taken incorrectly
+system.cpu.iew.branchMispredicts 899292 # Number of branch mispredicts detected at execute
+system.cpu.iew.iewExecutedInsts 123108789 # Number of executed instructions
+system.cpu.iew.iewExecLoadInsts 52799372 # Number of load instructions executed
+system.cpu.iew.iewExecSquashedInsts 3241833 # Number of squashed instructions skipped in execute
system.cpu.iew.exec_swp 0 # number of swp insts executed
-system.cpu.iew.exec_nop 261163 # number of nop insts executed
-system.cpu.iew.exec_refs 65197273 # number of memory reference insts executed
-system.cpu.iew.exec_branches 11589071 # Number of branches executed
-system.cpu.iew.exec_stores 12436454 # Number of stores executed
-system.cpu.iew.exec_rate 0.299056 # Inst execution rate
-system.cpu.iew.wb_sent 121403477 # cumulative count of insts sent to commit
-system.cpu.iew.wb_count 86897231 # cumulative count of insts written-back
-system.cpu.iew.wb_producers 47438485 # num instructions producing a value
-system.cpu.iew.wb_consumers 88321921 # num instructions consuming a value
+system.cpu.iew.exec_nop 261908 # number of nop insts executed
+system.cpu.iew.exec_refs 65255060 # number of memory reference insts executed
+system.cpu.iew.exec_branches 11601340 # Number of branches executed
+system.cpu.iew.exec_stores 12455688 # Number of stores executed
+system.cpu.iew.exec_rate 0.299278 # Inst execution rate
+system.cpu.iew.wb_sent 121555618 # cumulative count of insts sent to commit
+system.cpu.iew.wb_count 87050867 # cumulative count of insts written-back
+system.cpu.iew.wb_producers 47546734 # num instructions producing a value
+system.cpu.iew.wb_consumers 88572059 # num instructions consuming a value
system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ
-system.cpu.iew.wb_rate 0.211351 # insts written-back per cycle
-system.cpu.iew.wb_fanout 0.537109 # average fanout of values written-back
+system.cpu.iew.wb_rate 0.211621 # insts written-back per cycle
+system.cpu.iew.wb_fanout 0.536814 # average fanout of values written-back
system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ
-system.cpu.commit.commitCommittedInsts 59601672 # The number of committed instructions
-system.cpu.commit.commitCommittedOps 76942722 # The number of committed instructions
-system.cpu.commit.commitSquashedInsts 26965943 # The number of squashed insts skipped by commit
-system.cpu.commit.commitNonSpecStalls 1286949 # The number of times commit has been forced to stall to communicate backwards
-system.cpu.commit.branchMispredicts 790517 # The number of times a branch was mispredicted
-system.cpu.commit.committed_per_cycle::samples 146212348 # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::mean 0.526240 # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::stdev 1.505087 # Number of insts commited each cycle
+system.cpu.commit.commitCommittedInsts 59729390 # The number of committed instructions
+system.cpu.commit.commitCommittedOps 77077156 # The number of committed instructions
+system.cpu.commit.commitSquashedInsts 27015439 # The number of squashed insts skipped by commit
+system.cpu.commit.commitNonSpecStalls 1287306 # The number of times commit has been forced to stall to communicate backwards
+system.cpu.commit.branchMispredicts 793496 # The number of times a branch was mispredicted
+system.cpu.commit.committed_per_cycle::samples 146395876 # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::mean 0.526498 # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::stdev 1.504904 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::0 118498573 81.05% 81.05% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::1 13699176 9.37% 90.41% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::2 3966547 2.71% 93.13% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::3 2244227 1.53% 94.66% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::4 1750329 1.20% 95.86% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::5 1033206 0.71% 96.57% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::6 1542131 1.05% 97.62% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::7 667633 0.46% 98.08% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::8 2810526 1.92% 100.00% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::0 118626341 81.03% 81.03% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::1 13714527 9.37% 90.40% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::2 3991808 2.73% 93.13% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::3 2249419 1.54% 94.66% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::4 1746576 1.19% 95.86% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::5 1042045 0.71% 96.57% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::6 1550885 1.06% 97.63% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::7 665283 0.45% 98.08% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::8 2808992 1.92% 100.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::total 146212348 # Number of insts commited each cycle
-system.cpu.commit.committedInsts 59601672 # Number of instructions committed
-system.cpu.commit.committedOps 76942722 # Number of ops (including micro ops) committed
+system.cpu.commit.committed_per_cycle::total 146395876 # Number of insts commited each cycle
+system.cpu.commit.committedInsts 59729390 # Number of instructions committed
+system.cpu.commit.committedOps 77077156 # Number of ops (including micro ops) committed
system.cpu.commit.swp_count 0 # Number of s/w prefetches committed
-system.cpu.commit.refs 27460912 # Number of memory references committed
-system.cpu.commit.loads 15681479 # Number of loads committed
-system.cpu.commit.membars 413077 # Number of memory barriers committed
-system.cpu.commit.branches 9891359 # Number of branches committed
+system.cpu.commit.refs 27513639 # Number of memory references committed
+system.cpu.commit.loads 15715354 # Number of loads committed
+system.cpu.commit.membars 413068 # Number of memory barriers committed
+system.cpu.commit.branches 9904424 # Number of branches committed
system.cpu.commit.fp_insts 10212 # Number of committed floating point instructions.
-system.cpu.commit.int_insts 68495555 # Number of committed integer instructions.
-system.cpu.commit.function_calls 995632 # Number of function calls committed.
-system.cpu.commit.bw_lim_events 2810526 # number cycles where commit BW limit reached
+system.cpu.commit.int_insts 68617835 # Number of committed integer instructions.
+system.cpu.commit.function_calls 995976 # Number of function calls committed.
+system.cpu.commit.bw_lim_events 2808992 # number cycles where commit BW limit reached
system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits
-system.cpu.rob.rob_reads 245553933 # The number of ROB reads
-system.cpu.rob.rob_writes 212368242 # The number of ROB writes
-system.cpu.timesIdled 1894262 # Number of times that the entire CPU went into an idle state and unscheduled itself
-system.cpu.idleCycles 260596796 # Total number of cycles that the CPU has spent unscheduled due to idling
-system.cpu.quiesceCycles 4592114044 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
-system.cpu.committedInsts 59451291 # Number of Instructions Simulated
-system.cpu.committedOps 76792341 # Number of Ops (including micro ops) Simulated
-system.cpu.committedInsts_total 59451291 # Number of Instructions Simulated
-system.cpu.cpi 6.915755 # CPI: Cycles Per Instruction
-system.cpu.cpi_total 6.915755 # CPI: Total CPI of All Threads
-system.cpu.ipc 0.144597 # IPC: Instructions Per Cycle
-system.cpu.ipc_total 0.144597 # IPC: Total IPC of All Threads
-system.cpu.int_regfile_reads 557431988 # number of integer regfile reads
-system.cpu.int_regfile_writes 89182974 # number of integer regfile writes
-system.cpu.fp_regfile_reads 8912 # number of floating regfile reads
-system.cpu.fp_regfile_writes 2994 # number of floating regfile writes
-system.cpu.misc_regfile_reads 135303561 # number of misc regfile reads
-system.cpu.misc_regfile_writes 912352 # number of misc regfile writes
-system.cpu.icache.replacements 1013837 # number of replacements
-system.cpu.icache.tagsinuse 511.616166 # Cycle average of tags in use
-system.cpu.icache.total_refs 12585526 # Total number of references to valid blocks.
-system.cpu.icache.sampled_refs 1014349 # Sample count of references to valid blocks.
-system.cpu.icache.avg_refs 12.407491 # Average number of references to valid blocks.
-system.cpu.icache.warmup_cycle 6289783000 # Cycle when the warmup percentage was hit.
-system.cpu.icache.occ_blocks::cpu.inst 511.616166 # Average occupied blocks per requestor
-system.cpu.icache.occ_percent::cpu.inst 0.999250 # Average percentage of cache occupancy
-system.cpu.icache.occ_percent::total 0.999250 # Average percentage of cache occupancy
-system.cpu.icache.ReadReq_hits::cpu.inst 12585526 # number of ReadReq hits
-system.cpu.icache.ReadReq_hits::total 12585526 # number of ReadReq hits
-system.cpu.icache.demand_hits::cpu.inst 12585526 # number of demand (read+write) hits
-system.cpu.icache.demand_hits::total 12585526 # number of demand (read+write) hits
-system.cpu.icache.overall_hits::cpu.inst 12585526 # number of overall hits
-system.cpu.icache.overall_hits::total 12585526 # number of overall hits
-system.cpu.icache.ReadReq_misses::cpu.inst 1106194 # number of ReadReq misses
-system.cpu.icache.ReadReq_misses::total 1106194 # number of ReadReq misses
-system.cpu.icache.demand_misses::cpu.inst 1106194 # number of demand (read+write) misses
-system.cpu.icache.demand_misses::total 1106194 # number of demand (read+write) misses
-system.cpu.icache.overall_misses::cpu.inst 1106194 # number of overall misses
-system.cpu.icache.overall_misses::total 1106194 # number of overall misses
-system.cpu.icache.ReadReq_miss_latency::cpu.inst 16291440480 # number of ReadReq miss cycles
-system.cpu.icache.ReadReq_miss_latency::total 16291440480 # number of ReadReq miss cycles
-system.cpu.icache.demand_miss_latency::cpu.inst 16291440480 # number of demand (read+write) miss cycles
-system.cpu.icache.demand_miss_latency::total 16291440480 # number of demand (read+write) miss cycles
-system.cpu.icache.overall_miss_latency::cpu.inst 16291440480 # number of overall miss cycles
-system.cpu.icache.overall_miss_latency::total 16291440480 # number of overall miss cycles
-system.cpu.icache.ReadReq_accesses::cpu.inst 13691720 # number of ReadReq accesses(hits+misses)
-system.cpu.icache.ReadReq_accesses::total 13691720 # number of ReadReq accesses(hits+misses)
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+system.cpu.dcache.overall_accesses::cpu.data 25214634 # number of overall (read+write) accesses
+system.cpu.dcache.overall_accesses::total 25214634 # number of overall (read+write) accesses
+system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.049963 # miss rate for ReadReq accesses
+system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.289436 # miss rate for WriteReq accesses
+system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.045848 # miss rate for LoadLockedReq accesses
+system.cpu.dcache.StoreCondReq_miss_rate::cpu.data 0.000046 # miss rate for StoreCondReq accesses
+system.cpu.dcache.demand_miss_rate::cpu.data 0.147316 # miss rate for demand accesses
+system.cpu.dcache.overall_miss_rate::cpu.data 0.147316 # miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 15030.145589 # average ReadReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 37128.139717 # average WriteReq miss latency
+system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 16297.519459 # average LoadLockedReq miss latency
+system.cpu.dcache.StoreCondReq_avg_miss_latency::cpu.data 30307.692308 # average StoreCondReq miss latency
+system.cpu.dcache.demand_avg_miss_latency::cpu.data 32680.276789 # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::cpu.data 32680.276789 # average overall miss latency
+system.cpu.dcache.blocked_cycles::no_mshrs 17091437 # number of cycles access was blocked
+system.cpu.dcache.blocked_cycles::no_targets 7607500 # number of cycles access was blocked
+system.cpu.dcache.blocked::no_mshrs 3024 # number of cycles access was blocked
+system.cpu.dcache.blocked::no_targets 268 # number of cycles access was blocked
+system.cpu.dcache.avg_blocked_cycles::no_mshrs 5651.930225 # average number of cycles each access was blocked
+system.cpu.dcache.avg_blocked_cycles::no_targets 28386.194030 # average number of cycles each access was blocked
system.cpu.dcache.fast_writes 0 # number of fast writes performed
system.cpu.dcache.cache_copies 0 # number of cache copies performed
-system.cpu.dcache.writebacks::writebacks 575111 # number of writebacks
-system.cpu.dcache.writebacks::total 575111 # number of writebacks
-system.cpu.dcache.ReadReq_mshr_hits::cpu.data 358347 # number of ReadReq MSHR hits
-system.cpu.dcache.ReadReq_mshr_hits::total 358347 # number of ReadReq MSHR hits
-system.cpu.dcache.WriteReq_mshr_hits::cpu.data 2716460 # number of WriteReq MSHR hits
-system.cpu.dcache.WriteReq_mshr_hits::total 2716460 # number of WriteReq MSHR hits
-system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 1395 # number of LoadLockedReq MSHR hits
-system.cpu.dcache.LoadLockedReq_mshr_hits::total 1395 # number of LoadLockedReq MSHR hits
-system.cpu.dcache.demand_mshr_hits::cpu.data 3074807 # number of demand (read+write) MSHR hits
-system.cpu.dcache.demand_mshr_hits::total 3074807 # number of demand (read+write) MSHR hits
-system.cpu.dcache.overall_mshr_hits::cpu.data 3074807 # number of overall MSHR hits
-system.cpu.dcache.overall_mshr_hits::total 3074807 # number of overall MSHR hits
-system.cpu.dcache.ReadReq_mshr_misses::cpu.data 387588 # number of ReadReq MSHR misses
-system.cpu.dcache.ReadReq_mshr_misses::total 387588 # number of ReadReq MSHR misses
-system.cpu.dcache.WriteReq_mshr_misses::cpu.data 249344 # number of WriteReq MSHR misses
-system.cpu.dcache.WriteReq_mshr_misses::total 249344 # number of WriteReq MSHR misses
-system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data 12363 # number of LoadLockedReq MSHR misses
-system.cpu.dcache.LoadLockedReq_mshr_misses::total 12363 # number of LoadLockedReq MSHR misses
-system.cpu.dcache.StoreCondReq_mshr_misses::cpu.data 10 # number of StoreCondReq MSHR misses
-system.cpu.dcache.StoreCondReq_mshr_misses::total 10 # number of StoreCondReq MSHR misses
-system.cpu.dcache.demand_mshr_misses::cpu.data 636932 # number of demand (read+write) MSHR misses
-system.cpu.dcache.demand_mshr_misses::total 636932 # number of demand (read+write) MSHR misses
-system.cpu.dcache.overall_mshr_misses::cpu.data 636932 # number of overall MSHR misses
-system.cpu.dcache.overall_mshr_misses::total 636932 # number of overall MSHR misses
-system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 5281773000 # number of ReadReq MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_latency::total 5281773000 # number of ReadReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 8909514444 # number of WriteReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::total 8909514444 # number of WriteReq MSHR miss cycles
-system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data 166180500 # number of LoadLockedReq MSHR miss cycles
-system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 166180500 # number of LoadLockedReq MSHR miss cycles
-system.cpu.dcache.StoreCondReq_mshr_miss_latency::cpu.data 235000 # number of StoreCondReq MSHR miss cycles
-system.cpu.dcache.StoreCondReq_mshr_miss_latency::total 235000 # number of StoreCondReq MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::cpu.data 14191287444 # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::total 14191287444 # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::cpu.data 14191287444 # number of overall MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::total 14191287444 # number of overall MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 147159264500 # number of ReadReq MSHR uncacheable cycles
-system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 147159264500 # number of ReadReq MSHR uncacheable cycles
-system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data 42252638495 # number of WriteReq MSHR uncacheable cycles
-system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total 42252638495 # number of WriteReq MSHR uncacheable cycles
-system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 189411902995 # number of overall MSHR uncacheable cycles
-system.cpu.dcache.overall_mshr_uncacheable_latency::total 189411902995 # number of overall MSHR uncacheable cycles
-system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.025963 # mshr miss rate for ReadReq accesses
-system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.024370 # mshr miss rate for WriteReq accesses
-system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.041264 # mshr miss rate for LoadLockedReq accesses
-system.cpu.dcache.StoreCondReq_mshr_miss_rate::cpu.data 0.000035 # mshr miss rate for StoreCondReq accesses
-system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.025315 # mshr miss rate for demand accesses
-system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.025315 # mshr miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 13627.287223 # average ReadReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 35731.818067 # average WriteReq mshr miss latency
-system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 13441.761708 # average LoadLockedReq mshr miss latency
-system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::cpu.data 23500 # average StoreCondReq mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 22280.694712 # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 22280.694712 # average overall mshr miss latency
+system.cpu.dcache.writebacks::writebacks 574932 # number of writebacks
+system.cpu.dcache.writebacks::total 574932 # number of writebacks
+system.cpu.dcache.ReadReq_mshr_hits::cpu.data 359686 # number of ReadReq MSHR hits
+system.cpu.dcache.ReadReq_mshr_hits::total 359686 # number of ReadReq MSHR hits
+system.cpu.dcache.WriteReq_mshr_hits::cpu.data 2717440 # number of WriteReq MSHR hits
+system.cpu.dcache.WriteReq_mshr_hits::total 2717440 # number of WriteReq MSHR hits
+system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 1386 # number of LoadLockedReq MSHR hits
+system.cpu.dcache.LoadLockedReq_mshr_hits::total 1386 # number of LoadLockedReq MSHR hits
+system.cpu.dcache.demand_mshr_hits::cpu.data 3077126 # number of demand (read+write) MSHR hits
+system.cpu.dcache.demand_mshr_hits::total 3077126 # number of demand (read+write) MSHR hits
+system.cpu.dcache.overall_mshr_hits::cpu.data 3077126 # number of overall MSHR hits
+system.cpu.dcache.overall_mshr_hits::total 3077126 # number of overall MSHR hits
+system.cpu.dcache.ReadReq_mshr_misses::cpu.data 387969 # number of ReadReq MSHR misses
+system.cpu.dcache.ReadReq_mshr_misses::total 387969 # number of ReadReq MSHR misses
+system.cpu.dcache.WriteReq_mshr_misses::cpu.data 249425 # number of WriteReq MSHR misses
+system.cpu.dcache.WriteReq_mshr_misses::total 249425 # number of WriteReq MSHR misses
+system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data 12361 # number of LoadLockedReq MSHR misses
+system.cpu.dcache.LoadLockedReq_mshr_misses::total 12361 # number of LoadLockedReq MSHR misses
+system.cpu.dcache.StoreCondReq_mshr_misses::cpu.data 13 # number of StoreCondReq MSHR misses
+system.cpu.dcache.StoreCondReq_mshr_misses::total 13 # number of StoreCondReq MSHR misses
+system.cpu.dcache.demand_mshr_misses::cpu.data 637394 # number of demand (read+write) MSHR misses
+system.cpu.dcache.demand_mshr_misses::total 637394 # number of demand (read+write) MSHR misses
+system.cpu.dcache.overall_mshr_misses::cpu.data 637394 # number of overall MSHR misses
+system.cpu.dcache.overall_mshr_misses::total 637394 # number of overall MSHR misses
+system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 5287973500 # number of ReadReq MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_latency::total 5287973500 # number of ReadReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 8908906437 # number of WriteReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::total 8908906437 # number of WriteReq MSHR miss cycles
+system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data 165672500 # number of LoadLockedReq MSHR miss cycles
+system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 165672500 # number of LoadLockedReq MSHR miss cycles
+system.cpu.dcache.StoreCondReq_mshr_miss_latency::cpu.data 351500 # number of StoreCondReq MSHR miss cycles
+system.cpu.dcache.StoreCondReq_mshr_miss_latency::total 351500 # number of StoreCondReq MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::cpu.data 14196879937 # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::total 14196879937 # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::cpu.data 14196879937 # number of overall MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::total 14196879937 # number of overall MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 147151877500 # number of ReadReq MSHR uncacheable cycles
+system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 147151877500 # number of ReadReq MSHR uncacheable cycles
+system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data 42255772015 # number of WriteReq MSHR uncacheable cycles
+system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total 42255772015 # number of WriteReq MSHR uncacheable cycles
+system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 189407649515 # number of overall MSHR uncacheable cycles
+system.cpu.dcache.overall_mshr_uncacheable_latency::total 189407649515 # number of overall MSHR uncacheable cycles
+system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.025927 # mshr miss rate for ReadReq accesses
+system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.024333 # mshr miss rate for WriteReq accesses
+system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.041225 # mshr miss rate for LoadLockedReq accesses
+system.cpu.dcache.StoreCondReq_mshr_miss_rate::cpu.data 0.000046 # mshr miss rate for StoreCondReq accesses
+system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.025279 # mshr miss rate for demand accesses
+system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.025279 # mshr miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 13629.886666 # average ReadReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 35717.776634 # average WriteReq mshr miss latency
+system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 13402.839576 # average LoadLockedReq mshr miss latency
+system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::cpu.data 27038.461538 # average StoreCondReq mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 22273.319073 # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 22273.319073 # average overall mshr miss latency
system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency
system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu.data inf # average WriteReq mshr uncacheable latency
system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data inf # average overall mshr uncacheable latency
system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.iocache.fast_writes 0 # number of fast writes performed
system.iocache.cache_copies 0 # number of cache copies performed
-system.iocache.ReadReq_mshr_uncacheable_latency::realview.clcd 1296055922339 # number of ReadReq MSHR uncacheable cycles
-system.iocache.ReadReq_mshr_uncacheable_latency::total 1296055922339 # number of ReadReq MSHR uncacheable cycles
-system.iocache.overall_mshr_uncacheable_latency::realview.clcd 1296055922339 # number of overall MSHR uncacheable cycles
-system.iocache.overall_mshr_uncacheable_latency::total 1296055922339 # number of overall MSHR uncacheable cycles
+system.iocache.ReadReq_mshr_uncacheable_latency::realview.clcd 1296131413558 # number of ReadReq MSHR uncacheable cycles
+system.iocache.ReadReq_mshr_uncacheable_latency::total 1296131413558 # number of ReadReq MSHR uncacheable cycles
+system.iocache.overall_mshr_uncacheable_latency::realview.clcd 1296131413558 # number of overall MSHR uncacheable cycles
+system.iocache.overall_mshr_uncacheable_latency::total 1296131413558 # number of overall MSHR uncacheable cycles
system.iocache.ReadReq_avg_mshr_uncacheable_latency::realview.clcd inf # average ReadReq mshr uncacheable latency
system.iocache.overall_avg_mshr_uncacheable_latency::realview.clcd inf # average overall mshr uncacheable latency
system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.kern.inst.arm 0 # number of arm instructions executed
-system.cpu.kern.inst.quiesce 87985 # number of quiesce instructions executed
+system.cpu.kern.inst.quiesce 88053 # number of quiesce instructions executed
---------- End Simulation Statistics ----------
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
-gem5 compiled May 8 2012 15:17:37
-gem5 started May 8 2012 16:20:57
-gem5 executing on piton
+gem5 compiled May 10 2012 12:36:36
+gem5 started May 10 2012 12:36:42
+gem5 executing on u200540-lin
command line: build/ARM/gem5.opt -d build/ARM/tests/opt/quick/fs/10.linux-boot/arm/linux/realview-simple-atomic-dual -re tests/run.py build/ARM/tests/opt/quick/fs/10.linux-boot/arm/linux/realview-simple-atomic-dual
Global frequency set at 1000000000000 ticks per second
-info: kernel located at: /dist/m5/system/binaries/vmlinux.arm.smp.fb.2.6.38.8
+info: kernel located at: /projects/pd/randd/dist/binaries/vmlinux.arm.smp.fb.2.6.38.8
info: Using bootloader at address 0x80000000
info: Entering event queue @ 0. Starting simulation...
-Exiting @ tick 2411694099500 because m5_exit instruction encountered
+Exiting @ tick 911653589000 because m5_exit instruction encountered
---------- Begin Simulation Statistics ----------
-sim_seconds 2.411694 # Number of seconds simulated
-sim_ticks 2411694099500 # Number of ticks simulated
-final_tick 2411694099500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_seconds 0.911654 # Number of seconds simulated
+sim_ticks 911653589000 # Number of ticks simulated
+final_tick 911653589000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 781676 # Simulator instruction rate (inst/s)
-host_op_rate 1010494 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 30629621173 # Simulator tick rate (ticks/s)
-host_mem_usage 383944 # Number of bytes of host memory used
-host_seconds 78.74 # Real time elapsed on the host
-sim_insts 61547057 # Number of instructions simulated
-sim_ops 79563547 # Number of ops (including micro ops) simulated
-system.physmem.bytes_read 123270308 # Number of bytes read from this memory
-system.physmem.bytes_inst_read 1011392 # Number of instructions bytes read from this memory
-system.physmem.bytes_written 10185232 # Number of bytes written to this memory
-system.physmem.num_reads 14146769 # Number of read requests responded to by this memory
-system.physmem.num_writes 869038 # Number of write requests responded to by this memory
+host_inst_rate 1682178 # Simulator instruction rate (inst/s)
+host_op_rate 2174115 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 25299801897 # Simulator tick rate (ticks/s)
+host_mem_usage 379752 # Number of bytes of host memory used
+host_seconds 36.03 # Real time elapsed on the host
+sim_insts 60615585 # Number of instructions simulated
+sim_ops 78342060 # Number of ops (including micro ops) simulated
+system.physmem.bytes_read 50963556 # Number of bytes read from this memory
+system.physmem.bytes_inst_read 1003776 # Number of instructions bytes read from this memory
+system.physmem.bytes_written 10224784 # Number of bytes written to this memory
+system.physmem.num_reads 5103504 # Number of read requests responded to by this memory
+system.physmem.num_writes 869236 # Number of write requests responded to by this memory
system.physmem.num_other 0 # Number of other requests responded to by this memory
-system.physmem.bw_read 51113575 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read 419370 # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_write 4223269 # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_total 55336844 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_read 55902326 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read 1101050 # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_write 11215646 # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_total 67117972 # Total bandwidth to/from this memory (bytes/s)
system.realview.nvmem.bytes_read 68 # Number of bytes read from this memory
system.realview.nvmem.bytes_inst_read 68 # Number of instructions bytes read from this memory
system.realview.nvmem.bytes_written 0 # Number of bytes written to this memory
system.realview.nvmem.num_reads 17 # Number of read requests responded to by this memory
system.realview.nvmem.num_writes 0 # Number of write requests responded to by this memory
system.realview.nvmem.num_other 0 # Number of other requests responded to by this memory
-system.realview.nvmem.bw_read 28 # Total read bandwidth from this memory (bytes/s)
-system.realview.nvmem.bw_inst_read 28 # Instruction read bandwidth from this memory (bytes/s)
-system.realview.nvmem.bw_total 28 # Total bandwidth to/from this memory (bytes/s)
-system.l2c.replacements 127720 # number of replacements
-system.l2c.tagsinuse 25547.920882 # Cycle average of tags in use
-system.l2c.total_refs 1498993 # Total number of references to valid blocks.
-system.l2c.sampled_refs 156132 # Sample count of references to valid blocks.
-system.l2c.avg_refs 9.600806 # Average number of references to valid blocks.
+system.realview.nvmem.bw_read 75 # Total read bandwidth from this memory (bytes/s)
+system.realview.nvmem.bw_inst_read 75 # Instruction read bandwidth from this memory (bytes/s)
+system.realview.nvmem.bw_total 75 # Total bandwidth to/from this memory (bytes/s)
+system.l2c.replacements 127935 # number of replacements
+system.l2c.tagsinuse 26245.835103 # Cycle average of tags in use
+system.l2c.total_refs 1477463 # Total number of references to valid blocks.
+system.l2c.sampled_refs 156884 # Sample count of references to valid blocks.
+system.l2c.avg_refs 9.417551 # Average number of references to valid blocks.
system.l2c.warmup_cycle 0 # Cycle when the warmup percentage was hit.
-system.l2c.occ_blocks::writebacks 14919.913613 # Average occupied blocks per requestor
-system.l2c.occ_blocks::cpu0.dtb.walker 1.146267 # Average occupied blocks per requestor
-system.l2c.occ_blocks::cpu0.itb.walker 0.046172 # Average occupied blocks per requestor
-system.l2c.occ_blocks::cpu0.inst 3116.154275 # Average occupied blocks per requestor
-system.l2c.occ_blocks::cpu0.data 1287.935036 # Average occupied blocks per requestor
-system.l2c.occ_blocks::cpu1.dtb.walker 4.789000 # Average occupied blocks per requestor
-system.l2c.occ_blocks::cpu1.itb.walker 0.017808 # Average occupied blocks per requestor
-system.l2c.occ_blocks::cpu1.inst 2080.961372 # Average occupied blocks per requestor
-system.l2c.occ_blocks::cpu1.data 4136.957340 # Average occupied blocks per requestor
-system.l2c.occ_percent::writebacks 0.227660 # Average percentage of cache occupancy
-system.l2c.occ_percent::cpu0.dtb.walker 0.000017 # Average percentage of cache occupancy
-system.l2c.occ_percent::cpu0.itb.walker 0.000001 # Average percentage of cache occupancy
-system.l2c.occ_percent::cpu0.inst 0.047549 # Average percentage of cache occupancy
-system.l2c.occ_percent::cpu0.data 0.019652 # Average percentage of cache occupancy
-system.l2c.occ_percent::cpu1.dtb.walker 0.000073 # Average percentage of cache occupancy
-system.l2c.occ_percent::cpu1.itb.walker 0.000000 # Average percentage of cache occupancy
-system.l2c.occ_percent::cpu1.inst 0.031753 # Average percentage of cache occupancy
-system.l2c.occ_percent::cpu1.data 0.063125 # Average percentage of cache occupancy
-system.l2c.occ_percent::total 0.389830 # Average percentage of cache occupancy
-system.l2c.ReadReq_hits::cpu0.dtb.walker 5051 # number of ReadReq hits
-system.l2c.ReadReq_hits::cpu0.itb.walker 2156 # number of ReadReq hits
-system.l2c.ReadReq_hits::cpu0.inst 493019 # number of ReadReq hits
-system.l2c.ReadReq_hits::cpu0.data 213171 # number of ReadReq hits
-system.l2c.ReadReq_hits::cpu1.dtb.walker 4123 # number of ReadReq hits
-system.l2c.ReadReq_hits::cpu1.itb.walker 1590 # number of ReadReq hits
-system.l2c.ReadReq_hits::cpu1.inst 368111 # number of ReadReq hits
-system.l2c.ReadReq_hits::cpu1.data 131707 # number of ReadReq hits
-system.l2c.ReadReq_hits::total 1218928 # number of ReadReq hits
-system.l2c.Writeback_hits::writebacks 580462 # number of Writeback hits
-system.l2c.Writeback_hits::total 580462 # number of Writeback hits
-system.l2c.UpgradeReq_hits::cpu0.data 776 # number of UpgradeReq hits
-system.l2c.UpgradeReq_hits::cpu1.data 523 # number of UpgradeReq hits
-system.l2c.UpgradeReq_hits::total 1299 # number of UpgradeReq hits
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+system.l2c.ReadReq_miss_rate::cpu1.itb.walker 0.011465 # miss rate for ReadReq accesses
+system.l2c.ReadReq_miss_rate::cpu1.inst 0.014612 # miss rate for ReadReq accesses
+system.l2c.ReadReq_miss_rate::cpu1.data 0.073080 # miss rate for ReadReq accesses
+system.l2c.UpgradeReq_miss_rate::cpu0.data 0.882345 # miss rate for UpgradeReq accesses
+system.l2c.UpgradeReq_miss_rate::cpu1.data 0.805848 # miss rate for UpgradeReq accesses
+system.l2c.SCUpgradeReq_miss_rate::cpu0.data 0.845087 # miss rate for SCUpgradeReq accesses
+system.l2c.SCUpgradeReq_miss_rate::cpu1.data 0.655949 # miss rate for SCUpgradeReq accesses
+system.l2c.ReadExReq_miss_rate::cpu0.data 0.590549 # miss rate for ReadExReq accesses
+system.l2c.ReadExReq_miss_rate::cpu1.data 0.604811 # miss rate for ReadExReq accesses
+system.l2c.demand_miss_rate::cpu0.dtb.walker 0.002262 # miss rate for demand accesses
+system.l2c.demand_miss_rate::cpu0.itb.walker 0.003625 # miss rate for demand accesses
+system.l2c.demand_miss_rate::cpu0.inst 0.020038 # miss rate for demand accesses
+system.l2c.demand_miss_rate::cpu0.data 0.275589 # miss rate for demand accesses
+system.l2c.demand_miss_rate::cpu1.dtb.walker 0.003715 # miss rate for demand accesses
+system.l2c.demand_miss_rate::cpu1.itb.walker 0.011465 # miss rate for demand accesses
+system.l2c.demand_miss_rate::cpu1.inst 0.014612 # miss rate for demand accesses
+system.l2c.demand_miss_rate::cpu1.data 0.274157 # miss rate for demand accesses
+system.l2c.overall_miss_rate::cpu0.dtb.walker 0.002262 # miss rate for overall accesses
+system.l2c.overall_miss_rate::cpu0.itb.walker 0.003625 # miss rate for overall accesses
+system.l2c.overall_miss_rate::cpu0.inst 0.020038 # miss rate for overall accesses
+system.l2c.overall_miss_rate::cpu0.data 0.275589 # miss rate for overall accesses
+system.l2c.overall_miss_rate::cpu1.dtb.walker 0.003715 # miss rate for overall accesses
+system.l2c.overall_miss_rate::cpu1.itb.walker 0.011465 # miss rate for overall accesses
+system.l2c.overall_miss_rate::cpu1.inst 0.014612 # miss rate for overall accesses
+system.l2c.overall_miss_rate::cpu1.data 0.274157 # miss rate for overall accesses
system.l2c.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.l2c.blocked::no_mshrs 0 # number of cycles access was blocked
system.l2c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.l2c.fast_writes 0 # number of fast writes performed
system.l2c.cache_copies 0 # number of cache copies performed
-system.l2c.writebacks::writebacks 111818 # number of writebacks
-system.l2c.writebacks::total 111818 # number of writebacks
+system.l2c.writebacks::writebacks 112464 # number of writebacks
+system.l2c.writebacks::total 112464 # number of writebacks
system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate
system.cf0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD).
system.cf0.dma_read_bytes 0 # Number of bytes transfered via DMA reads (not PRD).
system.cf0.dma_write_txs 0 # Number of DMA write transactions.
system.cpu0.dtb.inst_hits 0 # ITB inst hits
system.cpu0.dtb.inst_misses 0 # ITB inst misses
-system.cpu0.dtb.read_hits 9339290 # DTB read hits
-system.cpu0.dtb.read_misses 5153 # DTB read misses
-system.cpu0.dtb.write_hits 6907877 # DTB write hits
-system.cpu0.dtb.write_misses 1048 # DTB write misses
+system.cpu0.dtb.read_hits 9312139 # DTB read hits
+system.cpu0.dtb.read_misses 5476 # DTB read misses
+system.cpu0.dtb.write_hits 6895585 # DTB write hits
+system.cpu0.dtb.write_misses 1137 # DTB write misses
system.cpu0.dtb.flush_tlb 4 # Number of times complete TLB was flushed
system.cpu0.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
system.cpu0.dtb.flush_tlb_mva_asid 1439 # Number of times TLB was flushed by MVA & ASID
system.cpu0.dtb.flush_tlb_asid 63 # Number of times TLB was flushed by ASID
-system.cpu0.dtb.flush_entries 2247 # Number of entries that have been flushed from TLB
+system.cpu0.dtb.flush_entries 2449 # Number of entries that have been flushed from TLB
system.cpu0.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions
-system.cpu0.dtb.prefetch_faults 150 # Number of TLB faults due to prefetch
+system.cpu0.dtb.prefetch_faults 187 # Number of TLB faults due to prefetch
system.cpu0.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions
-system.cpu0.dtb.perms_faults 248 # Number of TLB faults due to permissions restrictions
-system.cpu0.dtb.read_accesses 9344443 # DTB read accesses
-system.cpu0.dtb.write_accesses 6908925 # DTB write accesses
+system.cpu0.dtb.perms_faults 267 # Number of TLB faults due to permissions restrictions
+system.cpu0.dtb.read_accesses 9317615 # DTB read accesses
+system.cpu0.dtb.write_accesses 6896722 # DTB write accesses
system.cpu0.dtb.inst_accesses 0 # ITB inst accesses
-system.cpu0.dtb.hits 16247167 # DTB hits
-system.cpu0.dtb.misses 6201 # DTB misses
-system.cpu0.dtb.accesses 16253368 # DTB accesses
-system.cpu0.itb.inst_hits 34822572 # ITB inst hits
-system.cpu0.itb.inst_misses 2978 # ITB inst misses
+system.cpu0.dtb.hits 16207724 # DTB hits
+system.cpu0.dtb.misses 6613 # DTB misses
+system.cpu0.dtb.accesses 16214337 # DTB accesses
+system.cpu0.itb.inst_hits 34683994 # ITB inst hits
+system.cpu0.itb.inst_misses 3170 # ITB inst misses
system.cpu0.itb.read_hits 0 # DTB read hits
system.cpu0.itb.read_misses 0 # DTB read misses
system.cpu0.itb.write_hits 0 # DTB write hits
system.cpu0.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
system.cpu0.itb.flush_tlb_mva_asid 1439 # Number of times TLB was flushed by MVA & ASID
system.cpu0.itb.flush_tlb_asid 63 # Number of times TLB was flushed by ASID
-system.cpu0.itb.flush_entries 1462 # Number of entries that have been flushed from TLB
+system.cpu0.itb.flush_entries 1558 # Number of entries that have been flushed from TLB
system.cpu0.itb.align_faults 0 # Number of TLB faults due to alignment restrictions
system.cpu0.itb.prefetch_faults 0 # Number of TLB faults due to prefetch
system.cpu0.itb.domain_faults 0 # Number of TLB faults due to domain restrictions
system.cpu0.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions
system.cpu0.itb.read_accesses 0 # DTB read accesses
system.cpu0.itb.write_accesses 0 # DTB write accesses
-system.cpu0.itb.inst_accesses 34825550 # ITB inst accesses
-system.cpu0.itb.hits 34822572 # DTB hits
-system.cpu0.itb.misses 2978 # DTB misses
-system.cpu0.itb.accesses 34825550 # DTB accesses
-system.cpu0.numCycles 4823340800 # number of cpu cycles simulated
+system.cpu0.itb.inst_accesses 34687164 # ITB inst accesses
+system.cpu0.itb.hits 34683994 # DTB hits
+system.cpu0.itb.misses 3170 # DTB misses
+system.cpu0.itb.accesses 34687164 # DTB accesses
+system.cpu0.numCycles 1823259919 # number of cpu cycles simulated
system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed
-system.cpu0.committedInsts 34068123 # Number of instructions committed
-system.cpu0.committedOps 44975817 # Number of ops (including micro ops) committed
-system.cpu0.num_int_alu_accesses 39858141 # Number of integer alu accesses
-system.cpu0.num_fp_alu_accesses 4945 # Number of float alu accesses
-system.cpu0.num_func_calls 1311755 # number of times a function call or return occured
-system.cpu0.num_conditional_control_insts 4519198 # number of instructions that are conditional controls
-system.cpu0.num_int_insts 39858141 # number of integer instructions
-system.cpu0.num_fp_insts 4945 # number of float instructions
-system.cpu0.num_int_register_reads 202125837 # number of times the integer registers were read
-system.cpu0.num_int_register_writes 42204153 # number of times the integer registers were written
-system.cpu0.num_fp_register_reads 3641 # number of times the floating registers were read
-system.cpu0.num_fp_register_writes 1308 # number of times the floating registers were written
-system.cpu0.num_mem_refs 17030949 # number of memory refs
-system.cpu0.num_load_insts 9786551 # Number of load instructions
-system.cpu0.num_store_insts 7244398 # Number of store instructions
-system.cpu0.num_idle_cycles 4777543048.852804 # Number of idle cycles
-system.cpu0.num_busy_cycles 45797751.147196 # Number of busy cycles
-system.cpu0.not_idle_fraction 0.009495 # Percentage of non-idle cycles
-system.cpu0.idle_fraction 0.990505 # Percentage of idle cycles
+system.cpu0.committedInsts 33900598 # Number of instructions committed
+system.cpu0.committedOps 44786074 # Number of ops (including micro ops) committed
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+system.cpu0.num_fp_alu_accesses 5074 # Number of float alu accesses
+system.cpu0.num_func_calls 1296918 # number of times a function call or return occured
+system.cpu0.num_conditional_control_insts 4494112 # number of instructions that are conditional controls
+system.cpu0.num_int_insts 39685287 # number of integer instructions
+system.cpu0.num_fp_insts 5074 # number of float instructions
+system.cpu0.num_int_register_reads 201262894 # number of times the integer registers were read
+system.cpu0.num_int_register_writes 42034263 # number of times the integer registers were written
+system.cpu0.num_fp_register_reads 3706 # number of times the floating registers were read
+system.cpu0.num_fp_register_writes 1372 # number of times the floating registers were written
+system.cpu0.num_mem_refs 16978573 # number of memory refs
+system.cpu0.num_load_insts 9760184 # Number of load instructions
+system.cpu0.num_store_insts 7218389 # Number of store instructions
+system.cpu0.num_idle_cycles 1777623684.411826 # Number of idle cycles
+system.cpu0.num_busy_cycles 45636234.588174 # Number of busy cycles
+system.cpu0.not_idle_fraction 0.025030 # Percentage of non-idle cycles
+system.cpu0.idle_fraction 0.974970 # Percentage of idle cycles
system.cpu0.kern.inst.arm 0 # number of arm instructions executed
-system.cpu0.kern.inst.quiesce 59311 # number of quiesce instructions executed
-system.cpu0.icache.replacements 504460 # number of replacements
-system.cpu0.icache.tagsinuse 511.627588 # Cycle average of tags in use
-system.cpu0.icache.total_refs 34319175 # Total number of references to valid blocks.
-system.cpu0.icache.sampled_refs 504972 # Sample count of references to valid blocks.
-system.cpu0.icache.avg_refs 67.962531 # Average number of references to valid blocks.
-system.cpu0.icache.warmup_cycle 64519524000 # Cycle when the warmup percentage was hit.
-system.cpu0.icache.occ_blocks::cpu0.inst 511.627588 # Average occupied blocks per requestor
-system.cpu0.icache.occ_percent::cpu0.inst 0.999273 # Average percentage of cache occupancy
-system.cpu0.icache.occ_percent::total 0.999273 # Average percentage of cache occupancy
-system.cpu0.icache.ReadReq_hits::cpu0.inst 34319175 # number of ReadReq hits
-system.cpu0.icache.ReadReq_hits::total 34319175 # number of ReadReq hits
-system.cpu0.icache.demand_hits::cpu0.inst 34319175 # number of demand (read+write) hits
-system.cpu0.icache.demand_hits::total 34319175 # number of demand (read+write) hits
-system.cpu0.icache.overall_hits::cpu0.inst 34319175 # number of overall hits
-system.cpu0.icache.overall_hits::total 34319175 # number of overall hits
-system.cpu0.icache.ReadReq_misses::cpu0.inst 504973 # number of ReadReq misses
-system.cpu0.icache.ReadReq_misses::total 504973 # number of ReadReq misses
-system.cpu0.icache.demand_misses::cpu0.inst 504973 # number of demand (read+write) misses
-system.cpu0.icache.demand_misses::total 504973 # number of demand (read+write) misses
-system.cpu0.icache.overall_misses::cpu0.inst 504973 # number of overall misses
-system.cpu0.icache.overall_misses::total 504973 # number of overall misses
-system.cpu0.icache.ReadReq_accesses::cpu0.inst 34824148 # number of ReadReq accesses(hits+misses)
-system.cpu0.icache.ReadReq_accesses::total 34824148 # number of ReadReq accesses(hits+misses)
-system.cpu0.icache.demand_accesses::cpu0.inst 34824148 # number of demand (read+write) accesses
-system.cpu0.icache.demand_accesses::total 34824148 # number of demand (read+write) accesses
-system.cpu0.icache.overall_accesses::cpu0.inst 34824148 # number of overall (read+write) accesses
-system.cpu0.icache.overall_accesses::total 34824148 # number of overall (read+write) accesses
-system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.014501 # miss rate for ReadReq accesses
-system.cpu0.icache.demand_miss_rate::cpu0.inst 0.014501 # miss rate for demand accesses
-system.cpu0.icache.overall_miss_rate::cpu0.inst 0.014501 # miss rate for overall accesses
+system.cpu0.kern.inst.quiesce 58955 # number of quiesce instructions executed
+system.cpu0.icache.replacements 497177 # number of replacements
+system.cpu0.icache.tagsinuse 511.014795 # Cycle average of tags in use
+system.cpu0.icache.total_refs 34187980 # Total number of references to valid blocks.
+system.cpu0.icache.sampled_refs 497689 # Sample count of references to valid blocks.
+system.cpu0.icache.avg_refs 68.693461 # Average number of references to valid blocks.
+system.cpu0.icache.warmup_cycle 64536851000 # Cycle when the warmup percentage was hit.
+system.cpu0.icache.occ_blocks::cpu0.inst 511.014795 # Average occupied blocks per requestor
+system.cpu0.icache.occ_percent::cpu0.inst 0.998076 # Average percentage of cache occupancy
+system.cpu0.icache.occ_percent::total 0.998076 # Average percentage of cache occupancy
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+system.cpu0.icache.overall_misses::total 497690 # number of overall misses
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+system.cpu0.icache.ReadReq_accesses::total 34685670 # number of ReadReq accesses(hits+misses)
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system.cpu0.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu0.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu0.icache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu0.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu0.icache.fast_writes 0 # number of fast writes performed
system.cpu0.icache.cache_copies 0 # number of cache copies performed
-system.cpu0.icache.writebacks::writebacks 24728 # number of writebacks
-system.cpu0.icache.writebacks::total 24728 # number of writebacks
+system.cpu0.icache.writebacks::writebacks 26062 # number of writebacks
+system.cpu0.icache.writebacks::total 26062 # number of writebacks
system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate
-system.cpu0.dcache.replacements 380107 # number of replacements
-system.cpu0.dcache.tagsinuse 479.716402 # Cycle average of tags in use
-system.cpu0.dcache.total_refs 14708289 # Total number of references to valid blocks.
-system.cpu0.dcache.sampled_refs 380619 # Sample count of references to valid blocks.
-system.cpu0.dcache.avg_refs 38.643076 # Average number of references to valid blocks.
+system.cpu0.dcache.replacements 385595 # number of replacements
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+system.cpu0.dcache.sampled_refs 386107 # Sample count of references to valid blocks.
+system.cpu0.dcache.avg_refs 37.988371 # Average number of references to valid blocks.
system.cpu0.dcache.warmup_cycle 22115000 # Cycle when the warmup percentage was hit.
-system.cpu0.dcache.occ_blocks::cpu0.data 479.716402 # Average occupied blocks per requestor
-system.cpu0.dcache.occ_percent::cpu0.data 0.936946 # Average percentage of cache occupancy
-system.cpu0.dcache.occ_percent::total 0.936946 # Average percentage of cache occupancy
-system.cpu0.dcache.ReadReq_hits::cpu0.data 7803298 # number of ReadReq hits
-system.cpu0.dcache.ReadReq_hits::total 7803298 # number of ReadReq hits
-system.cpu0.dcache.WriteReq_hits::cpu0.data 6534060 # number of WriteReq hits
-system.cpu0.dcache.WriteReq_hits::total 6534060 # number of WriteReq hits
-system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 172314 # number of LoadLockedReq hits
-system.cpu0.dcache.LoadLockedReq_hits::total 172314 # number of LoadLockedReq hits
-system.cpu0.dcache.StoreCondReq_hits::cpu0.data 174866 # number of StoreCondReq hits
-system.cpu0.dcache.StoreCondReq_hits::total 174866 # number of StoreCondReq hits
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-system.cpu0.dcache.demand_hits::total 14337358 # number of demand (read+write) hits
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-system.cpu0.dcache.overall_hits::total 14337358 # number of overall hits
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-system.cpu0.dcache.ReadReq_misses::total 237350 # number of ReadReq misses
-system.cpu0.dcache.WriteReq_misses::cpu0.data 183580 # number of WriteReq misses
-system.cpu0.dcache.WriteReq_misses::total 183580 # number of WriteReq misses
-system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 9878 # number of LoadLockedReq misses
-system.cpu0.dcache.LoadLockedReq_misses::total 9878 # number of LoadLockedReq misses
-system.cpu0.dcache.StoreCondReq_misses::cpu0.data 7293 # number of StoreCondReq misses
-system.cpu0.dcache.StoreCondReq_misses::total 7293 # number of StoreCondReq misses
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-system.cpu0.dcache.demand_misses::total 420930 # number of demand (read+write) misses
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-system.cpu0.dcache.overall_misses::total 420930 # number of overall misses
-system.cpu0.dcache.ReadReq_accesses::cpu0.data 8040648 # number of ReadReq accesses(hits+misses)
-system.cpu0.dcache.ReadReq_accesses::total 8040648 # number of ReadReq accesses(hits+misses)
-system.cpu0.dcache.WriteReq_accesses::cpu0.data 6717640 # number of WriteReq accesses(hits+misses)
-system.cpu0.dcache.WriteReq_accesses::total 6717640 # number of WriteReq accesses(hits+misses)
-system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 182192 # number of LoadLockedReq accesses(hits+misses)
-system.cpu0.dcache.LoadLockedReq_accesses::total 182192 # number of LoadLockedReq accesses(hits+misses)
-system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 182159 # number of StoreCondReq accesses(hits+misses)
-system.cpu0.dcache.StoreCondReq_accesses::total 182159 # number of StoreCondReq accesses(hits+misses)
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-system.cpu0.dcache.overall_accesses::total 14758288 # number of overall (read+write) accesses
-system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.029519 # miss rate for ReadReq accesses
-system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.027328 # miss rate for WriteReq accesses
-system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.054218 # miss rate for LoadLockedReq accesses
-system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.040036 # miss rate for StoreCondReq accesses
-system.cpu0.dcache.demand_miss_rate::cpu0.data 0.028522 # miss rate for demand accesses
-system.cpu0.dcache.overall_miss_rate::cpu0.data 0.028522 # miss rate for overall accesses
+system.cpu0.dcache.occ_blocks::cpu0.data 475.569441 # Average occupied blocks per requestor
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+system.cpu0.dcache.occ_percent::total 0.928847 # Average percentage of cache occupancy
+system.cpu0.dcache.ReadReq_hits::cpu0.data 7775792 # number of ReadReq hits
+system.cpu0.dcache.ReadReq_hits::total 7775792 # number of ReadReq hits
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+system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 172927 # number of LoadLockedReq hits
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+system.cpu0.dcache.StoreCondReq_hits::total 175483 # number of StoreCondReq hits
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+system.cpu0.dcache.overall_hits::total 14295015 # number of overall hits
+system.cpu0.dcache.ReadReq_misses::cpu0.data 240570 # number of ReadReq misses
+system.cpu0.dcache.ReadReq_misses::total 240570 # number of ReadReq misses
+system.cpu0.dcache.WriteReq_misses::cpu0.data 186007 # number of WriteReq misses
+system.cpu0.dcache.WriteReq_misses::total 186007 # number of WriteReq misses
+system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 9987 # number of LoadLockedReq misses
+system.cpu0.dcache.LoadLockedReq_misses::total 9987 # number of LoadLockedReq misses
+system.cpu0.dcache.StoreCondReq_misses::cpu0.data 7377 # number of StoreCondReq misses
+system.cpu0.dcache.StoreCondReq_misses::total 7377 # number of StoreCondReq misses
+system.cpu0.dcache.demand_misses::cpu0.data 426577 # number of demand (read+write) misses
+system.cpu0.dcache.demand_misses::total 426577 # number of demand (read+write) misses
+system.cpu0.dcache.overall_misses::cpu0.data 426577 # number of overall misses
+system.cpu0.dcache.overall_misses::total 426577 # number of overall misses
+system.cpu0.dcache.ReadReq_accesses::cpu0.data 8016362 # number of ReadReq accesses(hits+misses)
+system.cpu0.dcache.ReadReq_accesses::total 8016362 # number of ReadReq accesses(hits+misses)
+system.cpu0.dcache.WriteReq_accesses::cpu0.data 6705230 # number of WriteReq accesses(hits+misses)
+system.cpu0.dcache.WriteReq_accesses::total 6705230 # number of WriteReq accesses(hits+misses)
+system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 182914 # number of LoadLockedReq accesses(hits+misses)
+system.cpu0.dcache.LoadLockedReq_accesses::total 182914 # number of LoadLockedReq accesses(hits+misses)
+system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 182860 # number of StoreCondReq accesses(hits+misses)
+system.cpu0.dcache.StoreCondReq_accesses::total 182860 # number of StoreCondReq accesses(hits+misses)
+system.cpu0.dcache.demand_accesses::cpu0.data 14721592 # number of demand (read+write) accesses
+system.cpu0.dcache.demand_accesses::total 14721592 # number of demand (read+write) accesses
+system.cpu0.dcache.overall_accesses::cpu0.data 14721592 # number of overall (read+write) accesses
+system.cpu0.dcache.overall_accesses::total 14721592 # number of overall (read+write) accesses
+system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.030010 # miss rate for ReadReq accesses
+system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.027741 # miss rate for WriteReq accesses
+system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.054599 # miss rate for LoadLockedReq accesses
+system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.040342 # miss rate for StoreCondReq accesses
+system.cpu0.dcache.demand_miss_rate::cpu0.data 0.028976 # miss rate for demand accesses
+system.cpu0.dcache.overall_miss_rate::cpu0.data 0.028976 # miss rate for overall accesses
system.cpu0.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu0.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu0.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu0.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu0.dcache.fast_writes 0 # number of fast writes performed
system.cpu0.dcache.cache_copies 0 # number of cache copies performed
-system.cpu0.dcache.writebacks::writebacks 339627 # number of writebacks
-system.cpu0.dcache.writebacks::total 339627 # number of writebacks
+system.cpu0.dcache.writebacks::writebacks 342703 # number of writebacks
+system.cpu0.dcache.writebacks::total 342703 # number of writebacks
system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu1.dtb.inst_hits 0 # ITB inst hits
system.cpu1.dtb.inst_misses 0 # ITB inst misses
-system.cpu1.dtb.read_hits 6258240 # DTB read hits
-system.cpu1.dtb.read_misses 2159 # DTB read misses
-system.cpu1.dtb.write_hits 4713968 # DTB write hits
-system.cpu1.dtb.write_misses 1181 # DTB write misses
+system.cpu1.dtb.read_hits 6036043 # DTB read hits
+system.cpu1.dtb.read_misses 1895 # DTB read misses
+system.cpu1.dtb.write_hits 4565126 # DTB write hits
+system.cpu1.dtb.write_misses 1147 # DTB write misses
system.cpu1.dtb.flush_tlb 4 # Number of times complete TLB was flushed
system.cpu1.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
system.cpu1.dtb.flush_tlb_mva_asid 1439 # Number of times TLB was flushed by MVA & ASID
system.cpu1.dtb.flush_tlb_asid 63 # Number of times TLB was flushed by ASID
-system.cpu1.dtb.flush_entries 1498 # Number of entries that have been flushed from TLB
+system.cpu1.dtb.flush_entries 1364 # Number of entries that have been flushed from TLB
system.cpu1.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions
-system.cpu1.dtb.prefetch_faults 92 # Number of TLB faults due to prefetch
+system.cpu1.dtb.prefetch_faults 95 # Number of TLB faults due to prefetch
system.cpu1.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions
-system.cpu1.dtb.perms_faults 204 # Number of TLB faults due to permissions restrictions
-system.cpu1.dtb.read_accesses 6260399 # DTB read accesses
-system.cpu1.dtb.write_accesses 4715149 # DTB write accesses
+system.cpu1.dtb.perms_faults 185 # Number of TLB faults due to permissions restrictions
+system.cpu1.dtb.read_accesses 6037938 # DTB read accesses
+system.cpu1.dtb.write_accesses 4566273 # DTB write accesses
system.cpu1.dtb.inst_accesses 0 # ITB inst accesses
-system.cpu1.dtb.hits 10972208 # DTB hits
-system.cpu1.dtb.misses 3340 # DTB misses
-system.cpu1.dtb.accesses 10975548 # DTB accesses
-system.cpu1.itb.inst_hits 27739473 # ITB inst hits
-system.cpu1.itb.inst_misses 1388 # ITB inst misses
+system.cpu1.dtb.hits 10601169 # DTB hits
+system.cpu1.dtb.misses 3042 # DTB misses
+system.cpu1.dtb.accesses 10604211 # DTB accesses
+system.cpu1.itb.inst_hits 26944447 # ITB inst hits
+system.cpu1.itb.inst_misses 1203 # ITB inst misses
system.cpu1.itb.read_hits 0 # DTB read hits
system.cpu1.itb.read_misses 0 # DTB read misses
system.cpu1.itb.write_hits 0 # DTB write hits
system.cpu1.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
system.cpu1.itb.flush_tlb_mva_asid 1439 # Number of times TLB was flushed by MVA & ASID
system.cpu1.itb.flush_tlb_asid 63 # Number of times TLB was flushed by ASID
-system.cpu1.itb.flush_entries 1342 # Number of entries that have been flushed from TLB
+system.cpu1.itb.flush_entries 1228 # Number of entries that have been flushed from TLB
system.cpu1.itb.align_faults 0 # Number of TLB faults due to alignment restrictions
system.cpu1.itb.prefetch_faults 0 # Number of TLB faults due to prefetch
system.cpu1.itb.domain_faults 0 # Number of TLB faults due to domain restrictions
system.cpu1.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions
system.cpu1.itb.read_accesses 0 # DTB read accesses
system.cpu1.itb.write_accesses 0 # DTB write accesses
-system.cpu1.itb.inst_accesses 27740861 # ITB inst accesses
-system.cpu1.itb.hits 27739473 # DTB hits
-system.cpu1.itb.misses 1388 # DTB misses
-system.cpu1.itb.accesses 27740861 # DTB accesses
-system.cpu1.numCycles 4822838236 # number of cpu cycles simulated
+system.cpu1.itb.inst_accesses 26945650 # ITB inst accesses
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+system.cpu1.itb.misses 1203 # DTB misses
+system.cpu1.itb.accesses 26945650 # DTB accesses
+system.cpu1.numCycles 1822760078 # number of cpu cycles simulated
system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed
-system.cpu1.committedInsts 27478934 # Number of instructions committed
-system.cpu1.committedOps 34587730 # Number of ops (including micro ops) committed
-system.cpu1.num_int_alu_accesses 30998282 # Number of integer alu accesses
-system.cpu1.num_fp_alu_accesses 5772 # Number of float alu accesses
-system.cpu1.num_func_calls 758024 # number of times a function call or return occured
-system.cpu1.num_conditional_control_insts 3403316 # number of instructions that are conditional controls
-system.cpu1.num_int_insts 30998282 # number of integer instructions
-system.cpu1.num_fp_insts 5772 # number of float instructions
-system.cpu1.num_int_register_reads 156835224 # number of times the integer registers were read
-system.cpu1.num_int_register_writes 33469234 # number of times the integer registers were written
-system.cpu1.num_fp_register_reads 3980 # number of times the floating registers were read
-system.cpu1.num_fp_register_writes 1792 # number of times the floating registers were written
-system.cpu1.num_mem_refs 11415851 # number of memory refs
-system.cpu1.num_load_insts 6479004 # Number of load instructions
-system.cpu1.num_store_insts 4936847 # Number of store instructions
-system.cpu1.num_idle_cycles 4787960139.182108 # Number of idle cycles
-system.cpu1.num_busy_cycles 34878096.817892 # Number of busy cycles
-system.cpu1.not_idle_fraction 0.007232 # Percentage of non-idle cycles
-system.cpu1.idle_fraction 0.992768 # Percentage of idle cycles
+system.cpu1.committedInsts 26714987 # Number of instructions committed
+system.cpu1.committedOps 33555986 # Number of ops (including micro ops) committed
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+system.cpu1.num_fp_alu_accesses 5643 # Number of float alu accesses
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+system.cpu1.num_conditional_control_insts 3301562 # number of instructions that are conditional controls
+system.cpu1.num_int_insts 30087808 # number of integer instructions
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+system.cpu1.num_int_register_writes 32495677 # number of times the integer registers were written
+system.cpu1.num_fp_register_reads 3915 # number of times the floating registers were read
+system.cpu1.num_fp_register_writes 1728 # number of times the floating registers were written
+system.cpu1.num_mem_refs 11031013 # number of memory refs
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+system.cpu1.num_store_insts 4783547 # Number of store instructions
+system.cpu1.num_idle_cycles 1788952556.347001 # Number of idle cycles
+system.cpu1.num_busy_cycles 33807521.652999 # Number of busy cycles
+system.cpu1.not_idle_fraction 0.018547 # Percentage of non-idle cycles
+system.cpu1.idle_fraction 0.981453 # Percentage of idle cycles
system.cpu1.kern.inst.arm 0 # number of arm instructions executed
-system.cpu1.kern.inst.quiesce 33011 # number of quiesce instructions executed
-system.cpu1.icache.replacements 374408 # number of replacements
-system.cpu1.icache.tagsinuse 498.143079 # Cycle average of tags in use
-system.cpu1.icache.total_refs 27365609 # Total number of references to valid blocks.
-system.cpu1.icache.sampled_refs 374920 # Sample count of references to valid blocks.
-system.cpu1.icache.avg_refs 72.990529 # Average number of references to valid blocks.
-system.cpu1.icache.warmup_cycle 69956153000 # Cycle when the warmup percentage was hit.
-system.cpu1.icache.occ_blocks::cpu1.inst 498.143079 # Average occupied blocks per requestor
-system.cpu1.icache.occ_percent::cpu1.inst 0.972936 # Average percentage of cache occupancy
-system.cpu1.icache.occ_percent::total 0.972936 # Average percentage of cache occupancy
-system.cpu1.icache.ReadReq_hits::cpu1.inst 27365609 # number of ReadReq hits
-system.cpu1.icache.ReadReq_hits::total 27365609 # number of ReadReq hits
-system.cpu1.icache.demand_hits::cpu1.inst 27365609 # number of demand (read+write) hits
-system.cpu1.icache.demand_hits::total 27365609 # number of demand (read+write) hits
-system.cpu1.icache.overall_hits::cpu1.inst 27365609 # number of overall hits
-system.cpu1.icache.overall_hits::total 27365609 # number of overall hits
-system.cpu1.icache.ReadReq_misses::cpu1.inst 374922 # number of ReadReq misses
-system.cpu1.icache.ReadReq_misses::total 374922 # number of ReadReq misses
-system.cpu1.icache.demand_misses::cpu1.inst 374922 # number of demand (read+write) misses
-system.cpu1.icache.demand_misses::total 374922 # number of demand (read+write) misses
-system.cpu1.icache.overall_misses::cpu1.inst 374922 # number of overall misses
-system.cpu1.icache.overall_misses::total 374922 # number of overall misses
-system.cpu1.icache.ReadReq_accesses::cpu1.inst 27740531 # number of ReadReq accesses(hits+misses)
-system.cpu1.icache.ReadReq_accesses::total 27740531 # number of ReadReq accesses(hits+misses)
-system.cpu1.icache.demand_accesses::cpu1.inst 27740531 # number of demand (read+write) accesses
-system.cpu1.icache.demand_accesses::total 27740531 # number of demand (read+write) accesses
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-system.cpu1.icache.overall_accesses::total 27740531 # number of overall (read+write) accesses
-system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.013515 # miss rate for ReadReq accesses
-system.cpu1.icache.demand_miss_rate::cpu1.inst 0.013515 # miss rate for demand accesses
-system.cpu1.icache.overall_miss_rate::cpu1.inst 0.013515 # miss rate for overall accesses
+system.cpu1.kern.inst.quiesce 31471 # number of quiesce instructions executed
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+system.cpu1.icache.tagsinuse 475.430525 # Cycle average of tags in use
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+system.cpu1.icache.sampled_refs 366344 # Sample count of references to valid blocks.
+system.cpu1.icache.avg_refs 72.552213 # Average number of references to valid blocks.
+system.cpu1.icache.warmup_cycle 69967043000 # Cycle when the warmup percentage was hit.
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+system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.013596 # miss rate for ReadReq accesses
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+system.cpu1.icache.overall_miss_rate::cpu1.inst 0.013596 # miss rate for overall accesses
system.cpu1.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu1.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu1.icache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu1.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu1.icache.fast_writes 0 # number of fast writes performed
system.cpu1.icache.cache_copies 0 # number of cache copies performed
-system.cpu1.icache.writebacks::writebacks 13905 # number of writebacks
-system.cpu1.icache.writebacks::total 13905 # number of writebacks
+system.cpu1.icache.writebacks::writebacks 12806 # number of writebacks
+system.cpu1.icache.writebacks::total 12806 # number of writebacks
system.cpu1.icache.no_allocate_misses 0 # Number of misses that were no-allocate
-system.cpu1.dcache.replacements 247435 # number of replacements
-system.cpu1.dcache.tagsinuse 444.903487 # Cycle average of tags in use
-system.cpu1.dcache.total_refs 9876841 # Total number of references to valid blocks.
-system.cpu1.dcache.sampled_refs 247806 # Sample count of references to valid blocks.
-system.cpu1.dcache.avg_refs 39.857150 # Average number of references to valid blocks.
-system.cpu1.dcache.warmup_cycle 69253216000 # Cycle when the warmup percentage was hit.
-system.cpu1.dcache.occ_blocks::cpu1.data 444.903487 # Average occupied blocks per requestor
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-system.cpu1.dcache.occ_percent::total 0.868952 # Average percentage of cache occupancy
-system.cpu1.dcache.ReadReq_hits::cpu1.data 5955982 # number of ReadReq hits
-system.cpu1.dcache.ReadReq_hits::total 5955982 # number of ReadReq hits
-system.cpu1.dcache.WriteReq_hits::cpu1.data 3777044 # number of WriteReq hits
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-system.cpu1.dcache.LoadLockedReq_hits::cpu1.data 59593 # number of LoadLockedReq hits
-system.cpu1.dcache.LoadLockedReq_hits::total 59593 # number of LoadLockedReq hits
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-system.cpu1.dcache.overall_hits::total 9733026 # number of overall hits
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-system.cpu1.dcache.ReadReq_misses::total 165800 # number of ReadReq misses
-system.cpu1.dcache.WriteReq_misses::cpu1.data 111467 # number of WriteReq misses
-system.cpu1.dcache.WriteReq_misses::total 111467 # number of WriteReq misses
-system.cpu1.dcache.LoadLockedReq_misses::cpu1.data 10725 # number of LoadLockedReq misses
-system.cpu1.dcache.LoadLockedReq_misses::total 10725 # number of LoadLockedReq misses
-system.cpu1.dcache.StoreCondReq_misses::cpu1.data 10198 # number of StoreCondReq misses
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-system.cpu1.dcache.overall_misses::total 277267 # number of overall misses
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-system.cpu1.dcache.WriteReq_accesses::cpu1.data 3888511 # number of WriteReq accesses(hits+misses)
-system.cpu1.dcache.WriteReq_accesses::total 3888511 # number of WriteReq accesses(hits+misses)
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-system.cpu1.dcache.LoadLockedReq_accesses::total 70318 # number of LoadLockedReq accesses(hits+misses)
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-system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.027084 # miss rate for ReadReq accesses
-system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.028666 # miss rate for WriteReq accesses
-system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data 0.152521 # miss rate for LoadLockedReq accesses
-system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data 0.145089 # miss rate for StoreCondReq accesses
-system.cpu1.dcache.demand_miss_rate::cpu1.data 0.027698 # miss rate for demand accesses
-system.cpu1.dcache.overall_miss_rate::cpu1.data 0.027698 # miss rate for overall accesses
+system.cpu1.dcache.replacements 240038 # number of replacements
+system.cpu1.dcache.tagsinuse 389.638585 # Cycle average of tags in use
+system.cpu1.dcache.total_refs 9512122 # Total number of references to valid blocks.
+system.cpu1.dcache.sampled_refs 240396 # Sample count of references to valid blocks.
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+system.cpu1.dcache.warmup_cycle 69263687500 # Cycle when the warmup percentage was hit.
+system.cpu1.dcache.occ_blocks::cpu1.data 389.638585 # Average occupied blocks per requestor
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+system.cpu1.dcache.occ_percent::total 0.761013 # Average percentage of cache occupancy
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+system.cpu1.dcache.WriteReq_misses::total 108913 # number of WriteReq misses
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+system.cpu1.dcache.StoreCondReq_misses::total 10014 # number of StoreCondReq misses
+system.cpu1.dcache.demand_misses::cpu1.data 269979 # number of demand (read+write) misses
+system.cpu1.dcache.demand_misses::total 269979 # number of demand (read+write) misses
+system.cpu1.dcache.overall_misses::cpu1.data 269979 # number of overall misses
+system.cpu1.dcache.overall_misses::total 269979 # number of overall misses
+system.cpu1.dcache.ReadReq_accesses::cpu1.data 5901104 # number of ReadReq accesses(hits+misses)
+system.cpu1.dcache.ReadReq_accesses::total 5901104 # number of ReadReq accesses(hits+misses)
+system.cpu1.dcache.WriteReq_accesses::cpu1.data 3743600 # number of WriteReq accesses(hits+misses)
+system.cpu1.dcache.WriteReq_accesses::total 3743600 # number of WriteReq accesses(hits+misses)
+system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data 67130 # number of LoadLockedReq accesses(hits+misses)
+system.cpu1.dcache.LoadLockedReq_accesses::total 67130 # number of LoadLockedReq accesses(hits+misses)
+system.cpu1.dcache.StoreCondReq_accesses::cpu1.data 67074 # number of StoreCondReq accesses(hits+misses)
+system.cpu1.dcache.StoreCondReq_accesses::total 67074 # number of StoreCondReq accesses(hits+misses)
+system.cpu1.dcache.demand_accesses::cpu1.data 9644704 # number of demand (read+write) accesses
+system.cpu1.dcache.demand_accesses::total 9644704 # number of demand (read+write) accesses
+system.cpu1.dcache.overall_accesses::cpu1.data 9644704 # number of overall (read+write) accesses
+system.cpu1.dcache.overall_accesses::total 9644704 # number of overall (read+write) accesses
+system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.027294 # miss rate for ReadReq accesses
+system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.029093 # miss rate for WriteReq accesses
+system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data 0.158141 # miss rate for LoadLockedReq accesses
+system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data 0.149298 # miss rate for StoreCondReq accesses
+system.cpu1.dcache.demand_miss_rate::cpu1.data 0.027992 # miss rate for demand accesses
+system.cpu1.dcache.overall_miss_rate::cpu1.data 0.027992 # miss rate for overall accesses
system.cpu1.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu1.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu1.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu1.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu1.dcache.fast_writes 0 # number of fast writes performed
system.cpu1.dcache.cache_copies 0 # number of cache copies performed
-system.cpu1.dcache.writebacks::writebacks 202202 # number of writebacks
-system.cpu1.dcache.writebacks::total 202202 # number of writebacks
+system.cpu1.dcache.writebacks::writebacks 196629 # number of writebacks
+system.cpu1.dcache.writebacks::total 196629 # number of writebacks
system.cpu1.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
system.iocache.replacements 0 # number of replacements
system.iocache.tagsinuse 0 # Cycle average of tags in use
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
-gem5 compiled May 8 2012 15:17:37
-gem5 started May 8 2012 16:20:57
-gem5 executing on piton
+gem5 compiled May 10 2012 12:36:36
+gem5 started May 10 2012 12:36:42
+gem5 executing on u200540-lin
command line: build/ARM/gem5.opt -d build/ARM/tests/opt/quick/fs/10.linux-boot/arm/linux/realview-simple-atomic -re tests/run.py build/ARM/tests/opt/quick/fs/10.linux-boot/arm/linux/realview-simple-atomic
Global frequency set at 1000000000000 ticks per second
-info: kernel located at: /dist/m5/system/binaries/vmlinux.arm.smp.fb.2.6.38.8
+info: kernel located at: /projects/pd/randd/dist/binaries/vmlinux.arm.smp.fb.2.6.38.8
info: Using bootloader at address 0x80000000
info: Entering event queue @ 0. Starting simulation...
-Exiting @ tick 2332316587000 because m5_exit instruction encountered
+Exiting @ tick 2332330037000 because m5_exit instruction encountered
---------- Begin Simulation Statistics ----------
-sim_seconds 2.332317 # Number of seconds simulated
-sim_ticks 2332316587000 # Number of ticks simulated
-final_tick 2332316587000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_seconds 2.332330 # Number of seconds simulated
+sim_ticks 2332330037000 # Number of ticks simulated
+final_tick 2332330037000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 864582 # Simulator instruction rate (inst/s)
-host_op_rate 1116533 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 34025972839 # Simulator tick rate (ticks/s)
-host_mem_usage 383900 # Number of bytes of host memory used
-host_seconds 68.55 # Real time elapsed on the host
-sim_insts 59262896 # Number of instructions simulated
-sim_ops 76532951 # Number of ops (including micro ops) simulated
-system.physmem.bytes_read 122663536 # Number of bytes read from this memory
-system.physmem.bytes_inst_read 941280 # Number of instructions bytes read from this memory
-system.physmem.bytes_written 9577800 # Number of bytes written to this memory
-system.physmem.num_reads 14137126 # Number of read requests responded to by this memory
-system.physmem.num_writes 856485 # Number of write requests responded to by this memory
+host_inst_rate 1538399 # Simulator instruction rate (inst/s)
+host_op_rate 1985816 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 60412799239 # Simulator tick rate (ticks/s)
+host_mem_usage 379756 # Number of bytes of host memory used
+host_seconds 38.61 # Real time elapsed on the host
+sim_insts 59392246 # Number of instructions simulated
+sim_ops 76665494 # Number of ops (including micro ops) simulated
+system.physmem.bytes_read 122661296 # Number of bytes read from this memory
+system.physmem.bytes_inst_read 941920 # Number of instructions bytes read from this memory
+system.physmem.bytes_written 9590216 # Number of bytes written to this memory
+system.physmem.num_reads 14137091 # Number of read requests responded to by this memory
+system.physmem.num_writes 856679 # Number of write requests responded to by this memory
system.physmem.num_other 0 # Number of other requests responded to by this memory
-system.physmem.bw_read 52593004 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read 403582 # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_write 4106561 # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_total 56699565 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_read 52591740 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read 403854 # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_write 4111861 # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_total 56703601 # Total bandwidth to/from this memory (bytes/s)
system.realview.nvmem.bytes_read 20 # Number of bytes read from this memory
system.realview.nvmem.bytes_inst_read 20 # Number of instructions bytes read from this memory
system.realview.nvmem.bytes_written 0 # Number of bytes written to this memory
system.realview.nvmem.bw_read 9 # Total read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_inst_read 9 # Instruction read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_total 9 # Total bandwidth to/from this memory (bytes/s)
-system.l2c.replacements 116822 # number of replacements
-system.l2c.tagsinuse 24240.388395 # Cycle average of tags in use
-system.l2c.total_refs 1520830 # Total number of references to valid blocks.
-system.l2c.sampled_refs 146847 # Sample count of references to valid blocks.
-system.l2c.avg_refs 10.356562 # Average number of references to valid blocks.
+system.l2c.replacements 117012 # number of replacements
+system.l2c.tagsinuse 24288.656748 # Cycle average of tags in use
+system.l2c.total_refs 1527554 # Total number of references to valid blocks.
+system.l2c.sampled_refs 146810 # Sample count of references to valid blocks.
+system.l2c.avg_refs 10.404972 # Average number of references to valid blocks.
system.l2c.warmup_cycle 0 # Cycle when the warmup percentage was hit.
-system.l2c.occ_blocks::writebacks 13639.466229 # Average occupied blocks per requestor
-system.l2c.occ_blocks::cpu.dtb.walker 7.864412 # Average occupied blocks per requestor
-system.l2c.occ_blocks::cpu.itb.walker 1.966419 # Average occupied blocks per requestor
-system.l2c.occ_blocks::cpu.inst 5246.411267 # Average occupied blocks per requestor
-system.l2c.occ_blocks::cpu.data 5344.680068 # Average occupied blocks per requestor
-system.l2c.occ_percent::writebacks 0.208122 # Average percentage of cache occupancy
+system.l2c.occ_blocks::writebacks 13693.996987 # Average occupied blocks per requestor
+system.l2c.occ_blocks::cpu.dtb.walker 7.872000 # Average occupied blocks per requestor
+system.l2c.occ_blocks::cpu.itb.walker 1.975558 # Average occupied blocks per requestor
+system.l2c.occ_blocks::cpu.inst 5248.163956 # Average occupied blocks per requestor
+system.l2c.occ_blocks::cpu.data 5336.648246 # Average occupied blocks per requestor
+system.l2c.occ_percent::writebacks 0.208954 # Average percentage of cache occupancy
system.l2c.occ_percent::cpu.dtb.walker 0.000120 # Average percentage of cache occupancy
system.l2c.occ_percent::cpu.itb.walker 0.000030 # Average percentage of cache occupancy
-system.l2c.occ_percent::cpu.inst 0.080054 # Average percentage of cache occupancy
-system.l2c.occ_percent::cpu.data 0.081553 # Average percentage of cache occupancy
-system.l2c.occ_percent::total 0.369879 # Average percentage of cache occupancy
-system.l2c.ReadReq_hits::cpu.dtb.walker 7522 # number of ReadReq hits
-system.l2c.ReadReq_hits::cpu.itb.walker 3147 # number of ReadReq hits
-system.l2c.ReadReq_hits::cpu.inst 831710 # number of ReadReq hits
-system.l2c.ReadReq_hits::cpu.data 356506 # number of ReadReq hits
-system.l2c.ReadReq_hits::total 1198885 # number of ReadReq hits
-system.l2c.Writeback_hits::writebacks 604613 # number of Writeback hits
-system.l2c.Writeback_hits::total 604613 # number of Writeback hits
+system.l2c.occ_percent::cpu.inst 0.080081 # Average percentage of cache occupancy
+system.l2c.occ_percent::cpu.data 0.081431 # Average percentage of cache occupancy
+system.l2c.occ_percent::total 0.370615 # Average percentage of cache occupancy
+system.l2c.ReadReq_hits::cpu.dtb.walker 7515 # number of ReadReq hits
+system.l2c.ReadReq_hits::cpu.itb.walker 3139 # number of ReadReq hits
+system.l2c.ReadReq_hits::cpu.inst 835264 # number of ReadReq hits
+system.l2c.ReadReq_hits::cpu.data 357385 # number of ReadReq hits
+system.l2c.ReadReq_hits::total 1203303 # number of ReadReq hits
+system.l2c.Writeback_hits::writebacks 605735 # number of Writeback hits
+system.l2c.Writeback_hits::total 605735 # number of Writeback hits
system.l2c.UpgradeReq_hits::cpu.data 26 # number of UpgradeReq hits
system.l2c.UpgradeReq_hits::total 26 # number of UpgradeReq hits
-system.l2c.ReadExReq_hits::cpu.data 105791 # number of ReadExReq hits
-system.l2c.ReadExReq_hits::total 105791 # number of ReadExReq hits
-system.l2c.demand_hits::cpu.dtb.walker 7522 # number of demand (read+write) hits
-system.l2c.demand_hits::cpu.itb.walker 3147 # number of demand (read+write) hits
-system.l2c.demand_hits::cpu.inst 831710 # number of demand (read+write) hits
-system.l2c.demand_hits::cpu.data 462297 # number of demand (read+write) hits
-system.l2c.demand_hits::total 1304676 # number of demand (read+write) hits
-system.l2c.overall_hits::cpu.dtb.walker 7522 # number of overall hits
-system.l2c.overall_hits::cpu.itb.walker 3147 # number of overall hits
-system.l2c.overall_hits::cpu.inst 831710 # number of overall hits
-system.l2c.overall_hits::cpu.data 462297 # number of overall hits
-system.l2c.overall_hits::total 1304676 # number of overall hits
-system.l2c.ReadReq_misses::cpu.dtb.walker 19 # number of ReadReq misses
-system.l2c.ReadReq_misses::cpu.itb.walker 8 # number of ReadReq misses
-system.l2c.ReadReq_misses::cpu.inst 14294 # number of ReadReq misses
-system.l2c.ReadReq_misses::cpu.data 17422 # number of ReadReq misses
-system.l2c.ReadReq_misses::total 31743 # number of ReadReq misses
-system.l2c.UpgradeReq_misses::cpu.data 2911 # number of UpgradeReq misses
-system.l2c.UpgradeReq_misses::total 2911 # number of UpgradeReq misses
-system.l2c.ReadExReq_misses::cpu.data 141169 # number of ReadExReq misses
-system.l2c.ReadExReq_misses::total 141169 # number of ReadExReq misses
-system.l2c.demand_misses::cpu.dtb.walker 19 # number of demand (read+write) misses
-system.l2c.demand_misses::cpu.itb.walker 8 # number of demand (read+write) misses
-system.l2c.demand_misses::cpu.inst 14294 # number of demand (read+write) misses
-system.l2c.demand_misses::cpu.data 158591 # number of demand (read+write) misses
-system.l2c.demand_misses::total 172912 # number of demand (read+write) misses
-system.l2c.overall_misses::cpu.dtb.walker 19 # number of overall misses
-system.l2c.overall_misses::cpu.itb.walker 8 # number of overall misses
-system.l2c.overall_misses::cpu.inst 14294 # number of overall misses
-system.l2c.overall_misses::cpu.data 158591 # number of overall misses
-system.l2c.overall_misses::total 172912 # number of overall misses
-system.l2c.ReadReq_accesses::cpu.dtb.walker 7541 # number of ReadReq accesses(hits+misses)
-system.l2c.ReadReq_accesses::cpu.itb.walker 3155 # number of ReadReq accesses(hits+misses)
-system.l2c.ReadReq_accesses::cpu.inst 846004 # number of ReadReq accesses(hits+misses)
-system.l2c.ReadReq_accesses::cpu.data 373928 # number of ReadReq accesses(hits+misses)
-system.l2c.ReadReq_accesses::total 1230628 # number of ReadReq accesses(hits+misses)
-system.l2c.Writeback_accesses::writebacks 604613 # number of Writeback accesses(hits+misses)
-system.l2c.Writeback_accesses::total 604613 # number of Writeback accesses(hits+misses)
-system.l2c.UpgradeReq_accesses::cpu.data 2937 # number of UpgradeReq accesses(hits+misses)
-system.l2c.UpgradeReq_accesses::total 2937 # number of UpgradeReq accesses(hits+misses)
-system.l2c.ReadExReq_accesses::cpu.data 246960 # number of ReadExReq accesses(hits+misses)
-system.l2c.ReadExReq_accesses::total 246960 # number of ReadExReq accesses(hits+misses)
-system.l2c.demand_accesses::cpu.dtb.walker 7541 # number of demand (read+write) accesses
-system.l2c.demand_accesses::cpu.itb.walker 3155 # number of demand (read+write) accesses
-system.l2c.demand_accesses::cpu.inst 846004 # number of demand (read+write) accesses
-system.l2c.demand_accesses::cpu.data 620888 # number of demand (read+write) accesses
-system.l2c.demand_accesses::total 1477588 # number of demand (read+write) accesses
-system.l2c.overall_accesses::cpu.dtb.walker 7541 # number of overall (read+write) accesses
-system.l2c.overall_accesses::cpu.itb.walker 3155 # number of overall (read+write) accesses
-system.l2c.overall_accesses::cpu.inst 846004 # number of overall (read+write) accesses
-system.l2c.overall_accesses::cpu.data 620888 # number of overall (read+write) accesses
-system.l2c.overall_accesses::total 1477588 # number of overall (read+write) accesses
-system.l2c.ReadReq_miss_rate::cpu.dtb.walker 0.002520 # miss rate for ReadReq accesses
-system.l2c.ReadReq_miss_rate::cpu.itb.walker 0.002536 # miss rate for ReadReq accesses
-system.l2c.ReadReq_miss_rate::cpu.inst 0.016896 # miss rate for ReadReq accesses
+system.l2c.ReadExReq_hits::cpu.data 106156 # number of ReadExReq hits
+system.l2c.ReadExReq_hits::total 106156 # number of ReadExReq hits
+system.l2c.demand_hits::cpu.dtb.walker 7515 # number of demand (read+write) hits
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+system.l2c.demand_hits::cpu.inst 835264 # number of demand (read+write) hits
+system.l2c.demand_hits::cpu.data 463541 # number of demand (read+write) hits
+system.l2c.demand_hits::total 1309459 # number of demand (read+write) hits
+system.l2c.overall_hits::cpu.dtb.walker 7515 # number of overall hits
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+system.l2c.overall_hits::cpu.data 463541 # number of overall hits
+system.l2c.overall_hits::total 1309459 # number of overall hits
+system.l2c.ReadReq_misses::cpu.dtb.walker 24 # number of ReadReq misses
+system.l2c.ReadReq_misses::cpu.itb.walker 15 # number of ReadReq misses
+system.l2c.ReadReq_misses::cpu.inst 14304 # number of ReadReq misses
+system.l2c.ReadReq_misses::cpu.data 17465 # number of ReadReq misses
+system.l2c.ReadReq_misses::total 31808 # number of ReadReq misses
+system.l2c.UpgradeReq_misses::cpu.data 2918 # number of UpgradeReq misses
+system.l2c.UpgradeReq_misses::total 2918 # number of UpgradeReq misses
+system.l2c.ReadExReq_misses::cpu.data 141050 # number of ReadExReq misses
+system.l2c.ReadExReq_misses::total 141050 # number of ReadExReq misses
+system.l2c.demand_misses::cpu.dtb.walker 24 # number of demand (read+write) misses
+system.l2c.demand_misses::cpu.itb.walker 15 # number of demand (read+write) misses
+system.l2c.demand_misses::cpu.inst 14304 # number of demand (read+write) misses
+system.l2c.demand_misses::cpu.data 158515 # number of demand (read+write) misses
+system.l2c.demand_misses::total 172858 # number of demand (read+write) misses
+system.l2c.overall_misses::cpu.dtb.walker 24 # number of overall misses
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+system.l2c.overall_misses::cpu.data 158515 # number of overall misses
+system.l2c.overall_misses::total 172858 # number of overall misses
+system.l2c.ReadReq_accesses::cpu.dtb.walker 7539 # number of ReadReq accesses(hits+misses)
+system.l2c.ReadReq_accesses::cpu.itb.walker 3154 # number of ReadReq accesses(hits+misses)
+system.l2c.ReadReq_accesses::cpu.inst 849568 # number of ReadReq accesses(hits+misses)
+system.l2c.ReadReq_accesses::cpu.data 374850 # number of ReadReq accesses(hits+misses)
+system.l2c.ReadReq_accesses::total 1235111 # number of ReadReq accesses(hits+misses)
+system.l2c.Writeback_accesses::writebacks 605735 # number of Writeback accesses(hits+misses)
+system.l2c.Writeback_accesses::total 605735 # number of Writeback accesses(hits+misses)
+system.l2c.UpgradeReq_accesses::cpu.data 2944 # number of UpgradeReq accesses(hits+misses)
+system.l2c.UpgradeReq_accesses::total 2944 # number of UpgradeReq accesses(hits+misses)
+system.l2c.ReadExReq_accesses::cpu.data 247206 # number of ReadExReq accesses(hits+misses)
+system.l2c.ReadExReq_accesses::total 247206 # number of ReadExReq accesses(hits+misses)
+system.l2c.demand_accesses::cpu.dtb.walker 7539 # number of demand (read+write) accesses
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+system.l2c.overall_accesses::cpu.data 622056 # number of overall (read+write) accesses
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+system.l2c.ReadReq_miss_rate::cpu.dtb.walker 0.003183 # miss rate for ReadReq accesses
+system.l2c.ReadReq_miss_rate::cpu.itb.walker 0.004756 # miss rate for ReadReq accesses
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system.l2c.ReadReq_miss_rate::cpu.data 0.046592 # miss rate for ReadReq accesses
-system.l2c.UpgradeReq_miss_rate::cpu.data 0.991147 # miss rate for UpgradeReq accesses
-system.l2c.ReadExReq_miss_rate::cpu.data 0.571627 # miss rate for ReadExReq accesses
-system.l2c.demand_miss_rate::cpu.dtb.walker 0.002520 # miss rate for demand accesses
-system.l2c.demand_miss_rate::cpu.itb.walker 0.002536 # miss rate for demand accesses
-system.l2c.demand_miss_rate::cpu.inst 0.016896 # miss rate for demand accesses
-system.l2c.demand_miss_rate::cpu.data 0.255426 # miss rate for demand accesses
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-system.l2c.overall_miss_rate::cpu.data 0.255426 # miss rate for overall accesses
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+system.l2c.overall_miss_rate::cpu.dtb.walker 0.003183 # miss rate for overall accesses
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+system.l2c.overall_miss_rate::cpu.data 0.254824 # miss rate for overall accesses
system.l2c.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.l2c.blocked::no_mshrs 0 # number of cycles access was blocked
system.l2c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.l2c.fast_writes 0 # number of fast writes performed
system.l2c.cache_copies 0 # number of cache copies performed
-system.l2c.writebacks::writebacks 102531 # number of writebacks
-system.l2c.writebacks::total 102531 # number of writebacks
+system.l2c.writebacks::writebacks 102725 # number of writebacks
+system.l2c.writebacks::total 102725 # number of writebacks
system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate
system.cf0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD).
system.cf0.dma_read_bytes 0 # Number of bytes transfered via DMA reads (not PRD).
system.cf0.dma_write_txs 0 # Number of DMA write transactions.
system.cpu.dtb.inst_hits 0 # ITB inst hits
system.cpu.dtb.inst_misses 0 # ITB inst misses
-system.cpu.dtb.read_hits 14940568 # DTB read hits
-system.cpu.dtb.read_misses 7288 # DTB read misses
-system.cpu.dtb.write_hits 11198206 # DTB write hits
-system.cpu.dtb.write_misses 2199 # DTB write misses
+system.cpu.dtb.read_hits 14971229 # DTB read hits
+system.cpu.dtb.read_misses 7293 # DTB read misses
+system.cpu.dtb.write_hits 11217018 # DTB write hits
+system.cpu.dtb.write_misses 2181 # DTB write misses
system.cpu.dtb.flush_tlb 2 # Number of times complete TLB was flushed
system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
system.cpu.dtb.flush_tlb_mva_asid 1439 # Number of times TLB was flushed by MVA & ASID
system.cpu.dtb.flush_tlb_asid 63 # Number of times TLB was flushed by ASID
-system.cpu.dtb.flush_entries 3505 # Number of entries that have been flushed from TLB
+system.cpu.dtb.flush_entries 3492 # Number of entries that have been flushed from TLB
system.cpu.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions
-system.cpu.dtb.prefetch_faults 189 # Number of TLB faults due to prefetch
+system.cpu.dtb.prefetch_faults 174 # Number of TLB faults due to prefetch
system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions
system.cpu.dtb.perms_faults 452 # Number of TLB faults due to permissions restrictions
-system.cpu.dtb.read_accesses 14947856 # DTB read accesses
-system.cpu.dtb.write_accesses 11200405 # DTB write accesses
+system.cpu.dtb.read_accesses 14978522 # DTB read accesses
+system.cpu.dtb.write_accesses 11219199 # DTB write accesses
system.cpu.dtb.inst_accesses 0 # ITB inst accesses
-system.cpu.dtb.hits 26138774 # DTB hits
-system.cpu.dtb.misses 9487 # DTB misses
-system.cpu.dtb.accesses 26148261 # DTB accesses
-system.cpu.itb.inst_hits 60273909 # ITB inst hits
+system.cpu.dtb.hits 26188247 # DTB hits
+system.cpu.dtb.misses 9474 # DTB misses
+system.cpu.dtb.accesses 26197721 # DTB accesses
+system.cpu.itb.inst_hits 60403303 # ITB inst hits
system.cpu.itb.inst_misses 4471 # ITB inst misses
system.cpu.itb.read_hits 0 # DTB read hits
system.cpu.itb.read_misses 0 # DTB read misses
system.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions
system.cpu.itb.read_accesses 0 # DTB read accesses
system.cpu.itb.write_accesses 0 # DTB write accesses
-system.cpu.itb.inst_accesses 60278380 # ITB inst accesses
-system.cpu.itb.hits 60273909 # DTB hits
+system.cpu.itb.inst_accesses 60407774 # ITB inst accesses
+system.cpu.itb.hits 60403303 # DTB hits
system.cpu.itb.misses 4471 # DTB misses
-system.cpu.itb.accesses 60278380 # DTB accesses
-system.cpu.numCycles 4664556206 # number of cpu cycles simulated
+system.cpu.itb.accesses 60407774 # DTB accesses
+system.cpu.numCycles 4664583062 # number of cpu cycles simulated
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
-system.cpu.committedInsts 59262896 # Number of instructions committed
-system.cpu.committedOps 76532951 # Number of ops (including micro ops) committed
-system.cpu.num_int_alu_accesses 68161195 # Number of integer alu accesses
+system.cpu.committedInsts 59392246 # Number of instructions committed
+system.cpu.committedOps 76665494 # Number of ops (including micro ops) committed
+system.cpu.num_int_alu_accesses 68281415 # Number of integer alu accesses
system.cpu.num_fp_alu_accesses 10269 # Number of float alu accesses
-system.cpu.num_func_calls 1971944 # number of times a function call or return occured
-system.cpu.num_conditional_control_insts 7636089 # number of instructions that are conditional controls
-system.cpu.num_int_insts 68161195 # number of integer instructions
+system.cpu.num_func_calls 1972385 # number of times a function call or return occured
+system.cpu.num_conditional_control_insts 7647793 # number of instructions that are conditional controls
+system.cpu.num_int_insts 68281415 # number of integer instructions
system.cpu.num_fp_insts 10269 # number of float instructions
-system.cpu.num_int_register_reads 345365700 # number of times the integer registers were read
-system.cpu.num_int_register_writes 72877714 # number of times the integer registers were written
+system.cpu.num_int_register_reads 345981857 # number of times the integer registers were read
+system.cpu.num_int_register_writes 73062916 # number of times the integer registers were written
system.cpu.num_fp_register_reads 7493 # number of times the floating registers were read
system.cpu.num_fp_register_writes 2780 # number of times the floating registers were written
-system.cpu.num_mem_refs 27310787 # number of memory refs
-system.cpu.num_load_insts 15607076 # Number of load instructions
-system.cpu.num_store_insts 11703711 # Number of store instructions
-system.cpu.num_idle_cycles 4586920130.978250 # Number of idle cycles
-system.cpu.num_busy_cycles 77636075.021750 # Number of busy cycles
-system.cpu.not_idle_fraction 0.016644 # Percentage of non-idle cycles
-system.cpu.idle_fraction 0.983356 # Percentage of idle cycles
+system.cpu.num_mem_refs 27361692 # number of memory refs
+system.cpu.num_load_insts 15639569 # Number of load instructions
+system.cpu.num_store_insts 11722123 # Number of store instructions
+system.cpu.num_idle_cycles 4586814358.980880 # Number of idle cycles
+system.cpu.num_busy_cycles 77768703.019120 # Number of busy cycles
+system.cpu.not_idle_fraction 0.016672 # Percentage of non-idle cycles
+system.cpu.idle_fraction 0.983328 # Percentage of idle cycles
system.cpu.kern.inst.arm 0 # number of arm instructions executed
-system.cpu.kern.inst.quiesce 82751 # number of quiesce instructions executed
-system.cpu.icache.replacements 847054 # number of replacements
-system.cpu.icache.tagsinuse 511.678552 # Cycle average of tags in use
-system.cpu.icache.total_refs 59429103 # Total number of references to valid blocks.
-system.cpu.icache.sampled_refs 847566 # Sample count of references to valid blocks.
-system.cpu.icache.avg_refs 70.117375 # Average number of references to valid blocks.
-system.cpu.icache.warmup_cycle 5705462000 # Cycle when the warmup percentage was hit.
-system.cpu.icache.occ_blocks::cpu.inst 511.678552 # Average occupied blocks per requestor
+system.cpu.kern.inst.quiesce 82795 # number of quiesce instructions executed
+system.cpu.icache.replacements 850612 # number of replacements
+system.cpu.icache.tagsinuse 511.678549 # Cycle average of tags in use
+system.cpu.icache.total_refs 59554939 # Total number of references to valid blocks.
+system.cpu.icache.sampled_refs 851124 # Sample count of references to valid blocks.
+system.cpu.icache.avg_refs 69.972106 # Average number of references to valid blocks.
+system.cpu.icache.warmup_cycle 5708999000 # Cycle when the warmup percentage was hit.
+system.cpu.icache.occ_blocks::cpu.inst 511.678549 # Average occupied blocks per requestor
system.cpu.icache.occ_percent::cpu.inst 0.999372 # Average percentage of cache occupancy
system.cpu.icache.occ_percent::total 0.999372 # Average percentage of cache occupancy
-system.cpu.icache.ReadReq_hits::cpu.inst 59429103 # number of ReadReq hits
-system.cpu.icache.ReadReq_hits::total 59429103 # number of ReadReq hits
-system.cpu.icache.demand_hits::cpu.inst 59429103 # number of demand (read+write) hits
-system.cpu.icache.demand_hits::total 59429103 # number of demand (read+write) hits
-system.cpu.icache.overall_hits::cpu.inst 59429103 # number of overall hits
-system.cpu.icache.overall_hits::total 59429103 # number of overall hits
-system.cpu.icache.ReadReq_misses::cpu.inst 847566 # number of ReadReq misses
-system.cpu.icache.ReadReq_misses::total 847566 # number of ReadReq misses
-system.cpu.icache.demand_misses::cpu.inst 847566 # number of demand (read+write) misses
-system.cpu.icache.demand_misses::total 847566 # number of demand (read+write) misses
-system.cpu.icache.overall_misses::cpu.inst 847566 # number of overall misses
-system.cpu.icache.overall_misses::total 847566 # number of overall misses
-system.cpu.icache.ReadReq_accesses::cpu.inst 60276669 # number of ReadReq accesses(hits+misses)
-system.cpu.icache.ReadReq_accesses::total 60276669 # number of ReadReq accesses(hits+misses)
-system.cpu.icache.demand_accesses::cpu.inst 60276669 # number of demand (read+write) accesses
-system.cpu.icache.demand_accesses::total 60276669 # number of demand (read+write) accesses
-system.cpu.icache.overall_accesses::cpu.inst 60276669 # number of overall (read+write) accesses
-system.cpu.icache.overall_accesses::total 60276669 # number of overall (read+write) accesses
-system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.014061 # miss rate for ReadReq accesses
-system.cpu.icache.demand_miss_rate::cpu.inst 0.014061 # miss rate for demand accesses
-system.cpu.icache.overall_miss_rate::cpu.inst 0.014061 # miss rate for overall accesses
+system.cpu.icache.ReadReq_hits::cpu.inst 59554939 # number of ReadReq hits
+system.cpu.icache.ReadReq_hits::total 59554939 # number of ReadReq hits
+system.cpu.icache.demand_hits::cpu.inst 59554939 # number of demand (read+write) hits
+system.cpu.icache.demand_hits::total 59554939 # number of demand (read+write) hits
+system.cpu.icache.overall_hits::cpu.inst 59554939 # number of overall hits
+system.cpu.icache.overall_hits::total 59554939 # number of overall hits
+system.cpu.icache.ReadReq_misses::cpu.inst 851124 # number of ReadReq misses
+system.cpu.icache.ReadReq_misses::total 851124 # number of ReadReq misses
+system.cpu.icache.demand_misses::cpu.inst 851124 # number of demand (read+write) misses
+system.cpu.icache.demand_misses::total 851124 # number of demand (read+write) misses
+system.cpu.icache.overall_misses::cpu.inst 851124 # number of overall misses
+system.cpu.icache.overall_misses::total 851124 # number of overall misses
+system.cpu.icache.ReadReq_accesses::cpu.inst 60406063 # number of ReadReq accesses(hits+misses)
+system.cpu.icache.ReadReq_accesses::total 60406063 # number of ReadReq accesses(hits+misses)
+system.cpu.icache.demand_accesses::cpu.inst 60406063 # number of demand (read+write) accesses
+system.cpu.icache.demand_accesses::total 60406063 # number of demand (read+write) accesses
+system.cpu.icache.overall_accesses::cpu.inst 60406063 # number of overall (read+write) accesses
+system.cpu.icache.overall_accesses::total 60406063 # number of overall (read+write) accesses
+system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.014090 # miss rate for ReadReq accesses
+system.cpu.icache.demand_miss_rate::cpu.inst 0.014090 # miss rate for demand accesses
+system.cpu.icache.overall_miss_rate::cpu.inst 0.014090 # miss rate for overall accesses
system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu.icache.fast_writes 0 # number of fast writes performed
system.cpu.icache.cache_copies 0 # number of cache copies performed
-system.cpu.icache.writebacks::writebacks 44721 # number of writebacks
-system.cpu.icache.writebacks::total 44721 # number of writebacks
+system.cpu.icache.writebacks::writebacks 44595 # number of writebacks
+system.cpu.icache.writebacks::total 44595 # number of writebacks
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
-system.cpu.dcache.replacements 622134 # number of replacements
+system.cpu.dcache.replacements 623347 # number of replacements
system.cpu.dcache.tagsinuse 511.997030 # Cycle average of tags in use
-system.cpu.dcache.total_refs 23580072 # Total number of references to valid blocks.
-system.cpu.dcache.sampled_refs 622646 # Sample count of references to valid blocks.
-system.cpu.dcache.avg_refs 37.870752 # Average number of references to valid blocks.
+system.cpu.dcache.total_refs 23628362 # Total number of references to valid blocks.
+system.cpu.dcache.sampled_refs 623859 # Sample count of references to valid blocks.
+system.cpu.dcache.avg_refs 37.874523 # Average number of references to valid blocks.
system.cpu.dcache.warmup_cycle 21763000 # Cycle when the warmup percentage was hit.
system.cpu.dcache.occ_blocks::cpu.data 511.997030 # Average occupied blocks per requestor
system.cpu.dcache.occ_percent::cpu.data 0.999994 # Average percentage of cache occupancy
system.cpu.dcache.occ_percent::total 0.999994 # Average percentage of cache occupancy
-system.cpu.dcache.ReadReq_hits::cpu.data 13150368 # number of ReadReq hits
-system.cpu.dcache.ReadReq_hits::total 13150368 # number of ReadReq hits
-system.cpu.dcache.WriteReq_hits::cpu.data 9943632 # number of WriteReq hits
-system.cpu.dcache.WriteReq_hits::total 9943632 # number of WriteReq hits
-system.cpu.dcache.LoadLockedReq_hits::cpu.data 235999 # number of LoadLockedReq hits
-system.cpu.dcache.LoadLockedReq_hits::total 235999 # number of LoadLockedReq hits
-system.cpu.dcache.StoreCondReq_hits::cpu.data 247136 # number of StoreCondReq hits
-system.cpu.dcache.StoreCondReq_hits::total 247136 # number of StoreCondReq hits
-system.cpu.dcache.demand_hits::cpu.data 23094000 # number of demand (read+write) hits
-system.cpu.dcache.demand_hits::total 23094000 # number of demand (read+write) hits
-system.cpu.dcache.overall_hits::cpu.data 23094000 # number of overall hits
-system.cpu.dcache.overall_hits::total 23094000 # number of overall hits
-system.cpu.dcache.ReadReq_misses::cpu.data 364548 # number of ReadReq misses
-system.cpu.dcache.ReadReq_misses::total 364548 # number of ReadReq misses
-system.cpu.dcache.WriteReq_misses::cpu.data 249897 # number of WriteReq misses
-system.cpu.dcache.WriteReq_misses::total 249897 # number of WriteReq misses
-system.cpu.dcache.LoadLockedReq_misses::cpu.data 11138 # number of LoadLockedReq misses
-system.cpu.dcache.LoadLockedReq_misses::total 11138 # number of LoadLockedReq misses
-system.cpu.dcache.demand_misses::cpu.data 614445 # number of demand (read+write) misses
-system.cpu.dcache.demand_misses::total 614445 # number of demand (read+write) misses
-system.cpu.dcache.overall_misses::cpu.data 614445 # number of overall misses
-system.cpu.dcache.overall_misses::total 614445 # number of overall misses
-system.cpu.dcache.ReadReq_accesses::cpu.data 13514916 # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.ReadReq_accesses::total 13514916 # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.WriteReq_accesses::cpu.data 10193529 # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.WriteReq_accesses::total 10193529 # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.LoadLockedReq_accesses::cpu.data 247137 # number of LoadLockedReq accesses(hits+misses)
-system.cpu.dcache.LoadLockedReq_accesses::total 247137 # number of LoadLockedReq accesses(hits+misses)
-system.cpu.dcache.StoreCondReq_accesses::cpu.data 247136 # number of StoreCondReq accesses(hits+misses)
-system.cpu.dcache.StoreCondReq_accesses::total 247136 # number of StoreCondReq accesses(hits+misses)
-system.cpu.dcache.demand_accesses::cpu.data 23708445 # number of demand (read+write) accesses
-system.cpu.dcache.demand_accesses::total 23708445 # number of demand (read+write) accesses
-system.cpu.dcache.overall_accesses::cpu.data 23708445 # number of overall (read+write) accesses
-system.cpu.dcache.overall_accesses::total 23708445 # number of overall (read+write) accesses
-system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.026974 # miss rate for ReadReq accesses
-system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.024515 # miss rate for WriteReq accesses
-system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.045068 # miss rate for LoadLockedReq accesses
-system.cpu.dcache.demand_miss_rate::cpu.data 0.025917 # miss rate for demand accesses
-system.cpu.dcache.overall_miss_rate::cpu.data 0.025917 # miss rate for overall accesses
+system.cpu.dcache.ReadReq_hits::cpu.data 13180074 # number of ReadReq hits
+system.cpu.dcache.ReadReq_hits::total 13180074 # number of ReadReq hits
+system.cpu.dcache.WriteReq_hits::cpu.data 9962087 # number of WriteReq hits
+system.cpu.dcache.WriteReq_hits::total 9962087 # number of WriteReq hits
+system.cpu.dcache.LoadLockedReq_hits::cpu.data 236035 # number of LoadLockedReq hits
+system.cpu.dcache.LoadLockedReq_hits::total 236035 # number of LoadLockedReq hits
+system.cpu.dcache.StoreCondReq_hits::cpu.data 247222 # number of StoreCondReq hits
+system.cpu.dcache.StoreCondReq_hits::total 247222 # number of StoreCondReq hits
+system.cpu.dcache.demand_hits::cpu.data 23142161 # number of demand (read+write) hits
+system.cpu.dcache.demand_hits::total 23142161 # number of demand (read+write) hits
+system.cpu.dcache.overall_hits::cpu.data 23142161 # number of overall hits
+system.cpu.dcache.overall_hits::total 23142161 # number of overall hits
+system.cpu.dcache.ReadReq_misses::cpu.data 365465 # number of ReadReq misses
+system.cpu.dcache.ReadReq_misses::total 365465 # number of ReadReq misses
+system.cpu.dcache.WriteReq_misses::cpu.data 250150 # number of WriteReq misses
+system.cpu.dcache.WriteReq_misses::total 250150 # number of WriteReq misses
+system.cpu.dcache.LoadLockedReq_misses::cpu.data 11188 # number of LoadLockedReq misses
+system.cpu.dcache.LoadLockedReq_misses::total 11188 # number of LoadLockedReq misses
+system.cpu.dcache.demand_misses::cpu.data 615615 # number of demand (read+write) misses
+system.cpu.dcache.demand_misses::total 615615 # number of demand (read+write) misses
+system.cpu.dcache.overall_misses::cpu.data 615615 # number of overall misses
+system.cpu.dcache.overall_misses::total 615615 # number of overall misses
+system.cpu.dcache.ReadReq_accesses::cpu.data 13545539 # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.ReadReq_accesses::total 13545539 # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.WriteReq_accesses::cpu.data 10212237 # number of WriteReq accesses(hits+misses)
+system.cpu.dcache.WriteReq_accesses::total 10212237 # number of WriteReq accesses(hits+misses)
+system.cpu.dcache.LoadLockedReq_accesses::cpu.data 247223 # number of LoadLockedReq accesses(hits+misses)
+system.cpu.dcache.LoadLockedReq_accesses::total 247223 # number of LoadLockedReq accesses(hits+misses)
+system.cpu.dcache.StoreCondReq_accesses::cpu.data 247222 # number of StoreCondReq accesses(hits+misses)
+system.cpu.dcache.StoreCondReq_accesses::total 247222 # number of StoreCondReq accesses(hits+misses)
+system.cpu.dcache.demand_accesses::cpu.data 23757776 # number of demand (read+write) accesses
+system.cpu.dcache.demand_accesses::total 23757776 # number of demand (read+write) accesses
+system.cpu.dcache.overall_accesses::cpu.data 23757776 # number of overall (read+write) accesses
+system.cpu.dcache.overall_accesses::total 23757776 # number of overall (read+write) accesses
+system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.026980 # miss rate for ReadReq accesses
+system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.024495 # miss rate for WriteReq accesses
+system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.045255 # miss rate for LoadLockedReq accesses
+system.cpu.dcache.demand_miss_rate::cpu.data 0.025912 # miss rate for demand accesses
+system.cpu.dcache.overall_miss_rate::cpu.data 0.025912 # miss rate for overall accesses
system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu.dcache.fast_writes 0 # number of fast writes performed
system.cpu.dcache.cache_copies 0 # number of cache copies performed
-system.cpu.dcache.writebacks::writebacks 559892 # number of writebacks
-system.cpu.dcache.writebacks::total 559892 # number of writebacks
+system.cpu.dcache.writebacks::writebacks 561140 # number of writebacks
+system.cpu.dcache.writebacks::total 561140 # number of writebacks
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
system.iocache.replacements 0 # number of replacements
system.iocache.tagsinuse 0 # Cycle average of tags in use
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
-gem5 compiled May 8 2012 15:17:37
-gem5 started May 8 2012 16:20:58
-gem5 executing on piton
+gem5 compiled May 10 2012 12:36:36
+gem5 started May 10 2012 12:36:42
+gem5 executing on u200540-lin
command line: build/ARM/gem5.opt -d build/ARM/tests/opt/quick/fs/10.linux-boot/arm/linux/realview-simple-timing-dual -re tests/run.py build/ARM/tests/opt/quick/fs/10.linux-boot/arm/linux/realview-simple-timing-dual
Global frequency set at 1000000000000 ticks per second
-info: kernel located at: /dist/m5/system/binaries/vmlinux.arm.smp.fb.2.6.38.8
+info: kernel located at: /projects/pd/randd/dist/binaries/vmlinux.arm.smp.fb.2.6.38.8
info: Using bootloader at address 0x80000000
info: Entering event queue @ 0. Starting simulation...
-Exiting @ tick 2669611225000 because m5_exit instruction encountered
+Exiting @ tick 1169707043000 because m5_exit instruction encountered
---------- Begin Simulation Statistics ----------
-sim_seconds 2.669611 # Number of seconds simulated
-sim_ticks 2669611225000 # Number of ticks simulated
-final_tick 2669611225000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_seconds 1.169707 # Number of seconds simulated
+sim_ticks 1169707043000 # Number of ticks simulated
+final_tick 1169707043000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 280373 # Simulator instruction rate (inst/s)
-host_op_rate 358676 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 12211141498 # Simulator tick rate (ticks/s)
-host_mem_usage 385748 # Number of bytes of host memory used
-host_seconds 218.62 # Real time elapsed on the host
-sim_insts 61295282 # Number of instructions simulated
-sim_ops 78413979 # Number of ops (including micro ops) simulated
-system.physmem.bytes_read 134334820 # Number of bytes read from this memory
-system.physmem.bytes_inst_read 1003520 # Number of instructions bytes read from this memory
-system.physmem.bytes_written 10194256 # Number of bytes written to this memory
-system.physmem.num_reads 15523876 # Number of read requests responded to by this memory
-system.physmem.num_writes 869239 # Number of write requests responded to by this memory
+host_inst_rate 754175 # Simulator instruction rate (inst/s)
+host_op_rate 964493 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 14598169556 # Simulator tick rate (ticks/s)
+host_mem_usage 379804 # Number of bytes of host memory used
+host_seconds 80.13 # Real time elapsed on the host
+sim_insts 60429704 # Number of instructions simulated
+sim_ops 77281862 # Number of ops (including micro ops) simulated
+system.physmem.bytes_read 61898788 # Number of bytes read from this memory
+system.physmem.bytes_inst_read 1004992 # Number of instructions bytes read from this memory
+system.physmem.bytes_written 10078928 # Number of bytes written to this memory
+system.physmem.num_reads 6478591 # Number of read requests responded to by this memory
+system.physmem.num_writes 867017 # Number of write requests responded to by this memory
system.physmem.num_other 0 # Number of other requests responded to by this memory
-system.physmem.bw_read 50319994 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read 375905 # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_write 3818629 # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_total 54138623 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_read 52918197 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read 859183 # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_write 8616626 # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_total 61534823 # Total bandwidth to/from this memory (bytes/s)
system.realview.nvmem.bytes_read 68 # Number of bytes read from this memory
system.realview.nvmem.bytes_inst_read 68 # Number of instructions bytes read from this memory
system.realview.nvmem.bytes_written 0 # Number of bytes written to this memory
system.realview.nvmem.num_reads 17 # Number of read requests responded to by this memory
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-system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 40086.080586 # average SCUpgradeReq mshr miss latency
-system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 40161.237785 # average SCUpgradeReq mshr miss latency
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-system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 40160.818259 # average ReadExReq mshr miss latency
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+system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 40041.506205 # average UpgradeReq mshr miss latency
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system.l2c.demand_avg_mshr_miss_latency::cpu0.itb.walker 40000 # average overall mshr miss latency
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-system.l2c.demand_avg_mshr_miss_latency::cpu0.data 40032.722670 # average overall mshr miss latency
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system.l2c.demand_avg_mshr_miss_latency::cpu1.itb.walker 40000 # average overall mshr miss latency
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system.l2c.overall_avg_mshr_miss_latency::cpu0.itb.walker 40000 # average overall mshr miss latency
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-system.l2c.overall_avg_mshr_miss_latency::cpu0.data 40032.722670 # average overall mshr miss latency
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system.l2c.overall_avg_mshr_miss_latency::cpu1.itb.walker 40000 # average overall mshr miss latency
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system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst inf # average ReadReq mshr uncacheable latency
system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data inf # average ReadReq mshr uncacheable latency
system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst inf # average ReadReq mshr uncacheable latency
system.cf0.dma_write_txs 0 # Number of DMA write transactions.
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system.cpu0.dtb.inst_misses 0 # ITB inst misses
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system.cpu0.dtb.flush_tlb 4 # Number of times complete TLB was flushed
system.cpu0.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
system.cpu0.dtb.flush_tlb_mva_asid 1439 # Number of times TLB was flushed by MVA & ASID
system.cpu0.dtb.flush_tlb_asid 63 # Number of times TLB was flushed by ASID
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system.cpu0.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions
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system.cpu0.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions
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system.cpu0.dtb.inst_accesses 0 # ITB inst accesses
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system.cpu0.itb.read_hits 0 # DTB read hits
system.cpu0.itb.read_misses 0 # DTB read misses
system.cpu0.itb.write_hits 0 # DTB write hits
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system.cpu0.itb.flush_tlb_mva_asid 1439 # Number of times TLB was flushed by MVA & ASID
system.cpu0.itb.flush_tlb_asid 63 # Number of times TLB was flushed by ASID
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system.cpu0.itb.align_faults 0 # Number of TLB faults due to alignment restrictions
system.cpu0.itb.prefetch_faults 0 # Number of TLB faults due to prefetch
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system.cpu0.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions
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system.cpu0.itb.write_accesses 0 # DTB write accesses
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system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed
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system.cpu0.kern.inst.arm 0 # number of arm instructions executed
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system.cpu0.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu0.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu0.icache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu0.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu0.icache.fast_writes 0 # number of fast writes performed
system.cpu0.icache.cache_copies 0 # number of cache copies performed
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system.cpu0.icache.ReadReq_mshr_uncacheable_latency::cpu0.inst 351814000 # number of ReadReq MSHR uncacheable cycles
system.cpu0.icache.ReadReq_mshr_uncacheable_latency::total 351814000 # number of ReadReq MSHR uncacheable cycles
system.cpu0.icache.overall_mshr_uncacheable_latency::cpu0.inst 351814000 # number of overall MSHR uncacheable cycles
system.cpu0.icache.overall_mshr_uncacheable_latency::total 351814000 # number of overall MSHR uncacheable cycles
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system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst inf # average ReadReq mshr uncacheable latency
system.cpu0.icache.overall_avg_mshr_uncacheable_latency::cpu0.inst inf # average overall mshr uncacheable latency
system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate
-system.cpu0.dcache.replacements 334596 # number of replacements
-system.cpu0.dcache.tagsinuse 450.118379 # Cycle average of tags in use
-system.cpu0.dcache.total_refs 12875674 # Total number of references to valid blocks.
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system.cpu0.dcache.warmup_cycle 663204000 # Cycle when the warmup percentage was hit.
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system.cpu0.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
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+system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.060456 # mshr miss rate for LoadLockedReq accesses
+system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.047474 # mshr miss rate for StoreCondReq accesses
+system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.030342 # mshr miss rate for demand accesses
+system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.030342 # mshr miss rate for overall accesses
+system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 12319.946018 # average ReadReq mshr miss latency
+system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 32591.360717 # average WriteReq mshr miss latency
+system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 8039.558127 # average LoadLockedReq mshr miss latency
+system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 6149.443774 # average StoreCondReq mshr miss latency
+system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 20054.000080 # average overall mshr miss latency
+system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 20054.000080 # average overall mshr miss latency
system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data inf # average ReadReq mshr uncacheable latency
system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data inf # average WriteReq mshr uncacheable latency
system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data inf # average overall mshr uncacheable latency
system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu1.dtb.inst_hits 0 # ITB inst hits
system.cpu1.dtb.inst_misses 0 # ITB inst misses
-system.cpu1.dtb.read_hits 7762498 # DTB read hits
-system.cpu1.dtb.read_misses 5432 # DTB read misses
-system.cpu1.dtb.write_hits 5411649 # DTB write hits
-system.cpu1.dtb.write_misses 1096 # DTB write misses
+system.cpu1.dtb.read_hits 8313009 # DTB read hits
+system.cpu1.dtb.read_misses 3663 # DTB read misses
+system.cpu1.dtb.write_hits 5829499 # DTB write hits
+system.cpu1.dtb.write_misses 1439 # DTB write misses
system.cpu1.dtb.flush_tlb 4 # Number of times complete TLB was flushed
system.cpu1.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
system.cpu1.dtb.flush_tlb_mva_asid 1439 # Number of times TLB was flushed by MVA & ASID
system.cpu1.dtb.flush_tlb_asid 63 # Number of times TLB was flushed by ASID
-system.cpu1.dtb.flush_entries 2346 # Number of entries that have been flushed from TLB
+system.cpu1.dtb.flush_entries 1967 # Number of entries that have been flushed from TLB
system.cpu1.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions
-system.cpu1.dtb.prefetch_faults 166 # Number of TLB faults due to prefetch
+system.cpu1.dtb.prefetch_faults 136 # Number of TLB faults due to prefetch
system.cpu1.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions
-system.cpu1.dtb.perms_faults 261 # Number of TLB faults due to permissions restrictions
-system.cpu1.dtb.read_accesses 7767930 # DTB read accesses
-system.cpu1.dtb.write_accesses 5412745 # DTB write accesses
+system.cpu1.dtb.perms_faults 248 # Number of TLB faults due to permissions restrictions
+system.cpu1.dtb.read_accesses 8316672 # DTB read accesses
+system.cpu1.dtb.write_accesses 5830938 # DTB write accesses
system.cpu1.dtb.inst_accesses 0 # ITB inst accesses
-system.cpu1.dtb.hits 13174147 # DTB hits
-system.cpu1.dtb.misses 6528 # DTB misses
-system.cpu1.dtb.accesses 13180675 # DTB accesses
-system.cpu1.itb.inst_hits 26848300 # ITB inst hits
-system.cpu1.itb.inst_misses 3154 # ITB inst misses
+system.cpu1.dtb.hits 14142508 # DTB hits
+system.cpu1.dtb.misses 5102 # DTB misses
+system.cpu1.dtb.accesses 14147610 # DTB accesses
+system.cpu1.itb.inst_hits 32286240 # ITB inst hits
+system.cpu1.itb.inst_misses 2171 # ITB inst misses
system.cpu1.itb.read_hits 0 # DTB read hits
system.cpu1.itb.read_misses 0 # DTB read misses
system.cpu1.itb.write_hits 0 # DTB write hits
system.cpu1.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
system.cpu1.itb.flush_tlb_mva_asid 1439 # Number of times TLB was flushed by MVA & ASID
system.cpu1.itb.flush_tlb_asid 63 # Number of times TLB was flushed by ASID
-system.cpu1.itb.flush_entries 1544 # Number of entries that have been flushed from TLB
+system.cpu1.itb.flush_entries 1495 # Number of entries that have been flushed from TLB
system.cpu1.itb.align_faults 0 # Number of TLB faults due to alignment restrictions
system.cpu1.itb.prefetch_faults 0 # Number of TLB faults due to prefetch
system.cpu1.itb.domain_faults 0 # Number of TLB faults due to domain restrictions
system.cpu1.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions
system.cpu1.itb.read_accesses 0 # DTB read accesses
system.cpu1.itb.write_accesses 0 # DTB write accesses
-system.cpu1.itb.inst_accesses 26851454 # ITB inst accesses
-system.cpu1.itb.hits 26848300 # DTB hits
-system.cpu1.itb.misses 3154 # DTB misses
-system.cpu1.itb.accesses 26851454 # DTB accesses
-system.cpu1.numCycles 5339222450 # number of cpu cycles simulated
+system.cpu1.itb.inst_accesses 32288411 # ITB inst accesses
+system.cpu1.itb.hits 32286240 # DTB hits
+system.cpu1.itb.misses 2171 # DTB misses
+system.cpu1.itb.accesses 32288411 # DTB accesses
+system.cpu1.numCycles 2338003468 # number of cpu cycles simulated
system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed
-system.cpu1.committedInsts 25921780 # Number of instructions committed
-system.cpu1.committedOps 34444955 # Number of ops (including micro ops) committed
-system.cpu1.num_int_alu_accesses 31033271 # Number of integer alu accesses
-system.cpu1.num_fp_alu_accesses 5714 # Number of float alu accesses
-system.cpu1.num_func_calls 1093852 # number of times a function call or return occured
-system.cpu1.num_conditional_control_insts 3472619 # number of instructions that are conditional controls
-system.cpu1.num_int_insts 31033271 # number of integer instructions
-system.cpu1.num_fp_insts 5714 # number of float instructions
-system.cpu1.num_int_register_reads 181157292 # number of times the integer registers were read
-system.cpu1.num_int_register_writes 32585326 # number of times the integer registers were written
-system.cpu1.num_fp_register_reads 3770 # number of times the floating registers were read
-system.cpu1.num_fp_register_writes 1948 # number of times the floating registers were written
-system.cpu1.num_mem_refs 13796846 # number of memory refs
-system.cpu1.num_load_insts 8139021 # Number of load instructions
-system.cpu1.num_store_insts 5657825 # Number of store instructions
-system.cpu1.num_idle_cycles 4950307196.068146 # Number of idle cycles
-system.cpu1.num_busy_cycles 388915253.931854 # Number of busy cycles
-system.cpu1.not_idle_fraction 0.072841 # Percentage of non-idle cycles
-system.cpu1.idle_fraction 0.927159 # Percentage of idle cycles
+system.cpu1.committedInsts 31682438 # Number of instructions committed
+system.cpu1.committedOps 40196649 # Number of ops (including micro ops) committed
+system.cpu1.num_int_alu_accesses 36868206 # Number of integer alu accesses
+system.cpu1.num_fp_alu_accesses 6793 # Number of float alu accesses
+system.cpu1.num_func_calls 909270 # number of times a function call or return occured
+system.cpu1.num_conditional_control_insts 3487065 # number of instructions that are conditional controls
+system.cpu1.num_int_insts 36868206 # number of integer instructions
+system.cpu1.num_fp_insts 6793 # number of float instructions
+system.cpu1.num_int_register_reads 210764243 # number of times the integer registers were read
+system.cpu1.num_int_register_writes 38547083 # number of times the integer registers were written
+system.cpu1.num_fp_register_reads 4535 # number of times the floating registers were read
+system.cpu1.num_fp_register_writes 2260 # number of times the floating registers were written
+system.cpu1.num_mem_refs 14680299 # number of memory refs
+system.cpu1.num_load_insts 8634860 # Number of load instructions
+system.cpu1.num_store_insts 6045439 # Number of store instructions
+system.cpu1.num_idle_cycles 1858954745.472398 # Number of idle cycles
+system.cpu1.num_busy_cycles 479048722.527602 # Number of busy cycles
+system.cpu1.not_idle_fraction 0.204896 # Percentage of non-idle cycles
+system.cpu1.idle_fraction 0.795104 # Percentage of idle cycles
system.cpu1.kern.inst.arm 0 # number of arm instructions executed
-system.cpu1.kern.inst.quiesce 53838 # number of quiesce instructions executed
-system.cpu1.icache.replacements 508221 # number of replacements
-system.cpu1.icache.tagsinuse 497.375159 # Cycle average of tags in use
-system.cpu1.icache.total_refs 26339563 # Total number of references to valid blocks.
-system.cpu1.icache.sampled_refs 508733 # Sample count of references to valid blocks.
-system.cpu1.icache.avg_refs 51.774827 # Average number of references to valid blocks.
-system.cpu1.icache.warmup_cycle 191336880000 # Cycle when the warmup percentage was hit.
-system.cpu1.icache.occ_blocks::cpu1.inst 497.375159 # Average occupied blocks per requestor
-system.cpu1.icache.occ_percent::cpu1.inst 0.971436 # Average percentage of cache occupancy
-system.cpu1.icache.occ_percent::total 0.971436 # Average percentage of cache occupancy
-system.cpu1.icache.ReadReq_hits::cpu1.inst 26339563 # number of ReadReq hits
-system.cpu1.icache.ReadReq_hits::total 26339563 # number of ReadReq hits
-system.cpu1.icache.demand_hits::cpu1.inst 26339563 # number of demand (read+write) hits
-system.cpu1.icache.demand_hits::total 26339563 # number of demand (read+write) hits
-system.cpu1.icache.overall_hits::cpu1.inst 26339563 # number of overall hits
-system.cpu1.icache.overall_hits::total 26339563 # number of overall hits
-system.cpu1.icache.ReadReq_misses::cpu1.inst 508733 # number of ReadReq misses
-system.cpu1.icache.ReadReq_misses::total 508733 # number of ReadReq misses
-system.cpu1.icache.demand_misses::cpu1.inst 508733 # number of demand (read+write) misses
-system.cpu1.icache.demand_misses::total 508733 # number of demand (read+write) misses
-system.cpu1.icache.overall_misses::cpu1.inst 508733 # number of overall misses
-system.cpu1.icache.overall_misses::total 508733 # number of overall misses
-system.cpu1.icache.ReadReq_miss_latency::cpu1.inst 7436443000 # number of ReadReq miss cycles
-system.cpu1.icache.ReadReq_miss_latency::total 7436443000 # number of ReadReq miss cycles
-system.cpu1.icache.demand_miss_latency::cpu1.inst 7436443000 # number of demand (read+write) miss cycles
-system.cpu1.icache.demand_miss_latency::total 7436443000 # number of demand (read+write) miss cycles
-system.cpu1.icache.overall_miss_latency::cpu1.inst 7436443000 # number of overall miss cycles
-system.cpu1.icache.overall_miss_latency::total 7436443000 # number of overall miss cycles
-system.cpu1.icache.ReadReq_accesses::cpu1.inst 26848296 # number of ReadReq accesses(hits+misses)
-system.cpu1.icache.ReadReq_accesses::total 26848296 # number of ReadReq accesses(hits+misses)
-system.cpu1.icache.demand_accesses::cpu1.inst 26848296 # number of demand (read+write) accesses
-system.cpu1.icache.demand_accesses::total 26848296 # number of demand (read+write) accesses
-system.cpu1.icache.overall_accesses::cpu1.inst 26848296 # number of overall (read+write) accesses
-system.cpu1.icache.overall_accesses::total 26848296 # number of overall (read+write) accesses
-system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.018948 # miss rate for ReadReq accesses
-system.cpu1.icache.demand_miss_rate::cpu1.inst 0.018948 # miss rate for demand accesses
-system.cpu1.icache.overall_miss_rate::cpu1.inst 0.018948 # miss rate for overall accesses
-system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 14617.575428 # average ReadReq miss latency
-system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 14617.575428 # average overall miss latency
-system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 14617.575428 # average overall miss latency
+system.cpu1.kern.inst.quiesce 43911 # number of quiesce instructions executed
+system.cpu1.icache.replacements 454317 # number of replacements
+system.cpu1.icache.tagsinuse 478.423780 # Cycle average of tags in use
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+system.cpu1.icache.sampled_refs 454829 # Sample count of references to valid blocks.
+system.cpu1.icache.avg_refs 69.985438 # Average number of references to valid blocks.
+system.cpu1.icache.warmup_cycle 91926225000 # Cycle when the warmup percentage was hit.
+system.cpu1.icache.occ_blocks::cpu1.inst 478.423780 # Average occupied blocks per requestor
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+system.cpu1.icache.occ_percent::total 0.934421 # Average percentage of cache occupancy
+system.cpu1.icache.ReadReq_hits::cpu1.inst 31831407 # number of ReadReq hits
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+system.cpu1.icache.overall_hits::total 31831407 # number of overall hits
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+system.cpu1.icache.ReadReq_misses::total 454829 # number of ReadReq misses
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+system.cpu1.icache.overall_misses::total 454829 # number of overall misses
+system.cpu1.icache.ReadReq_miss_latency::cpu1.inst 6679957000 # number of ReadReq miss cycles
+system.cpu1.icache.ReadReq_miss_latency::total 6679957000 # number of ReadReq miss cycles
+system.cpu1.icache.demand_miss_latency::cpu1.inst 6679957000 # number of demand (read+write) miss cycles
+system.cpu1.icache.demand_miss_latency::total 6679957000 # number of demand (read+write) miss cycles
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+system.cpu1.icache.overall_miss_latency::total 6679957000 # number of overall miss cycles
+system.cpu1.icache.ReadReq_accesses::cpu1.inst 32286236 # number of ReadReq accesses(hits+misses)
+system.cpu1.icache.ReadReq_accesses::total 32286236 # number of ReadReq accesses(hits+misses)
+system.cpu1.icache.demand_accesses::cpu1.inst 32286236 # number of demand (read+write) accesses
+system.cpu1.icache.demand_accesses::total 32286236 # number of demand (read+write) accesses
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+system.cpu1.icache.overall_accesses::total 32286236 # number of overall (read+write) accesses
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+system.cpu1.icache.overall_miss_rate::cpu1.inst 0.014087 # miss rate for overall accesses
+system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 14686.743809 # average ReadReq miss latency
+system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 14686.743809 # average overall miss latency
+system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 14686.743809 # average overall miss latency
system.cpu1.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu1.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu1.icache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu1.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu1.icache.fast_writes 0 # number of fast writes performed
system.cpu1.icache.cache_copies 0 # number of cache copies performed
-system.cpu1.icache.writebacks::writebacks 27998 # number of writebacks
-system.cpu1.icache.writebacks::total 27998 # number of writebacks
-system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst 508733 # number of ReadReq MSHR misses
-system.cpu1.icache.ReadReq_mshr_misses::total 508733 # number of ReadReq MSHR misses
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-system.cpu1.icache.demand_mshr_misses::total 508733 # number of demand (read+write) MSHR misses
-system.cpu1.icache.overall_mshr_misses::cpu1.inst 508733 # number of overall MSHR misses
-system.cpu1.icache.overall_mshr_misses::total 508733 # number of overall MSHR misses
-system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst 5908061000 # number of ReadReq MSHR miss cycles
-system.cpu1.icache.ReadReq_mshr_miss_latency::total 5908061000 # number of ReadReq MSHR miss cycles
-system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst 5908061000 # number of demand (read+write) MSHR miss cycles
-system.cpu1.icache.demand_mshr_miss_latency::total 5908061000 # number of demand (read+write) MSHR miss cycles
-system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst 5908061000 # number of overall MSHR miss cycles
-system.cpu1.icache.overall_mshr_miss_latency::total 5908061000 # number of overall MSHR miss cycles
+system.cpu1.icache.writebacks::writebacks 19149 # number of writebacks
+system.cpu1.icache.writebacks::total 19149 # number of writebacks
+system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst 454829 # number of ReadReq MSHR misses
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+system.cpu1.icache.ReadReq_mshr_miss_latency::total 5314262500 # number of ReadReq MSHR miss cycles
+system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst 5314262500 # number of demand (read+write) MSHR miss cycles
+system.cpu1.icache.demand_mshr_miss_latency::total 5314262500 # number of demand (read+write) MSHR miss cycles
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+system.cpu1.icache.overall_mshr_miss_latency::total 5314262500 # number of overall MSHR miss cycles
system.cpu1.icache.ReadReq_mshr_uncacheable_latency::cpu1.inst 5250000 # number of ReadReq MSHR uncacheable cycles
system.cpu1.icache.ReadReq_mshr_uncacheable_latency::total 5250000 # number of ReadReq MSHR uncacheable cycles
system.cpu1.icache.overall_mshr_uncacheable_latency::cpu1.inst 5250000 # number of overall MSHR uncacheable cycles
system.cpu1.icache.overall_mshr_uncacheable_latency::total 5250000 # number of overall MSHR uncacheable cycles
-system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.018948 # mshr miss rate for ReadReq accesses
-system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst 0.018948 # mshr miss rate for demand accesses
-system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst 0.018948 # mshr miss rate for overall accesses
-system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 11613.284375 # average ReadReq mshr miss latency
-system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 11613.284375 # average overall mshr miss latency
-system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 11613.284375 # average overall mshr miss latency
+system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.014087 # mshr miss rate for ReadReq accesses
+system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst 0.014087 # mshr miss rate for demand accesses
+system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst 0.014087 # mshr miss rate for overall accesses
+system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 11684.088965 # average ReadReq mshr miss latency
+system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 11684.088965 # average overall mshr miss latency
+system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 11684.088965 # average overall mshr miss latency
system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst inf # average ReadReq mshr uncacheable latency
system.cpu1.icache.overall_avg_mshr_uncacheable_latency::cpu1.inst inf # average overall mshr uncacheable latency
system.cpu1.icache.no_allocate_misses 0 # Number of misses that were no-allocate
-system.cpu1.dcache.replacements 295754 # number of replacements
-system.cpu1.dcache.tagsinuse 467.166428 # Cycle average of tags in use
-system.cpu1.dcache.total_refs 11737110 # Total number of references to valid blocks.
-system.cpu1.dcache.sampled_refs 296266 # Sample count of references to valid blocks.
-system.cpu1.dcache.avg_refs 39.616797 # Average number of references to valid blocks.
-system.cpu1.dcache.warmup_cycle 75924171000 # Cycle when the warmup percentage was hit.
-system.cpu1.dcache.occ_blocks::cpu1.data 467.166428 # Average occupied blocks per requestor
-system.cpu1.dcache.occ_percent::cpu1.data 0.912434 # Average percentage of cache occupancy
-system.cpu1.dcache.occ_percent::total 0.912434 # Average percentage of cache occupancy
-system.cpu1.dcache.ReadReq_hits::cpu1.data 6345292 # number of ReadReq hits
-system.cpu1.dcache.ReadReq_hits::total 6345292 # number of ReadReq hits
-system.cpu1.dcache.WriteReq_hits::cpu1.data 5152611 # number of WriteReq hits
-system.cpu1.dcache.WriteReq_hits::total 5152611 # number of WriteReq hits
-system.cpu1.dcache.LoadLockedReq_hits::cpu1.data 104795 # number of LoadLockedReq hits
-system.cpu1.dcache.LoadLockedReq_hits::total 104795 # number of LoadLockedReq hits
-system.cpu1.dcache.StoreCondReq_hits::cpu1.data 106403 # number of StoreCondReq hits
-system.cpu1.dcache.StoreCondReq_hits::total 106403 # number of StoreCondReq hits
-system.cpu1.dcache.demand_hits::cpu1.data 11497903 # number of demand (read+write) hits
-system.cpu1.dcache.demand_hits::total 11497903 # number of demand (read+write) hits
-system.cpu1.dcache.overall_hits::cpu1.data 11497903 # number of overall hits
-system.cpu1.dcache.overall_hits::total 11497903 # number of overall hits
-system.cpu1.dcache.ReadReq_misses::cpu1.data 188245 # number of ReadReq misses
-system.cpu1.dcache.ReadReq_misses::total 188245 # number of ReadReq misses
-system.cpu1.dcache.WriteReq_misses::cpu1.data 137493 # number of WriteReq misses
-system.cpu1.dcache.WriteReq_misses::total 137493 # number of WriteReq misses
-system.cpu1.dcache.LoadLockedReq_misses::cpu1.data 11557 # number of LoadLockedReq misses
-system.cpu1.dcache.LoadLockedReq_misses::total 11557 # number of LoadLockedReq misses
-system.cpu1.dcache.StoreCondReq_misses::cpu1.data 9906 # number of StoreCondReq misses
-system.cpu1.dcache.StoreCondReq_misses::total 9906 # number of StoreCondReq misses
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-system.cpu1.dcache.demand_misses::total 325738 # number of demand (read+write) misses
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-system.cpu1.dcache.overall_misses::total 325738 # number of overall misses
-system.cpu1.dcache.ReadReq_miss_latency::cpu1.data 2729025500 # number of ReadReq miss cycles
-system.cpu1.dcache.ReadReq_miss_latency::total 2729025500 # number of ReadReq miss cycles
-system.cpu1.dcache.WriteReq_miss_latency::cpu1.data 4123985000 # number of WriteReq miss cycles
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-system.cpu1.dcache.LoadLockedReq_miss_latency::cpu1.data 131720000 # number of LoadLockedReq miss cycles
-system.cpu1.dcache.LoadLockedReq_miss_latency::total 131720000 # number of LoadLockedReq miss cycles
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-system.cpu1.dcache.ReadReq_accesses::cpu1.data 6533537 # number of ReadReq accesses(hits+misses)
-system.cpu1.dcache.ReadReq_accesses::total 6533537 # number of ReadReq accesses(hits+misses)
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-system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data 116352 # number of LoadLockedReq accesses(hits+misses)
-system.cpu1.dcache.LoadLockedReq_accesses::total 116352 # number of LoadLockedReq accesses(hits+misses)
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-system.cpu1.dcache.StoreCondReq_accesses::total 116309 # number of StoreCondReq accesses(hits+misses)
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-system.cpu1.dcache.demand_accesses::total 11823641 # number of demand (read+write) accesses
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-system.cpu1.dcache.overall_accesses::total 11823641 # number of overall (read+write) accesses
-system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.028812 # miss rate for ReadReq accesses
-system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.025991 # miss rate for WriteReq accesses
-system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data 0.099328 # miss rate for LoadLockedReq accesses
-system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data 0.085170 # miss rate for StoreCondReq accesses
-system.cpu1.dcache.demand_miss_rate::cpu1.data 0.027550 # miss rate for demand accesses
-system.cpu1.dcache.overall_miss_rate::cpu1.data 0.027550 # miss rate for overall accesses
-system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 14497.200457 # average ReadReq miss latency
-system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 29994.145156 # average WriteReq miss latency
-system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 11397.421476 # average LoadLockedReq miss latency
-system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.data 8327.579245 # average StoreCondReq miss latency
-system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 21038.412773 # average overall miss latency
-system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 21038.412773 # average overall miss latency
+system.cpu1.dcache.replacements 294642 # number of replacements
+system.cpu1.dcache.tagsinuse 457.752328 # Cycle average of tags in use
+system.cpu1.dcache.total_refs 11964721 # Total number of references to valid blocks.
+system.cpu1.dcache.sampled_refs 295088 # Sample count of references to valid blocks.
+system.cpu1.dcache.avg_refs 40.546281 # Average number of references to valid blocks.
+system.cpu1.dcache.warmup_cycle 89831748000 # Cycle when the warmup percentage was hit.
+system.cpu1.dcache.occ_blocks::cpu1.data 457.752328 # Average occupied blocks per requestor
+system.cpu1.dcache.occ_percent::cpu1.data 0.894048 # Average percentage of cache occupancy
+system.cpu1.dcache.occ_percent::total 0.894048 # Average percentage of cache occupancy
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+system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 24134.585035 # average overall miss latency
system.cpu1.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu1.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu1.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu1.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu1.dcache.fast_writes 0 # number of fast writes performed
system.cpu1.dcache.cache_copies 0 # number of cache copies performed
-system.cpu1.dcache.writebacks::writebacks 253551 # number of writebacks
-system.cpu1.dcache.writebacks::total 253551 # number of writebacks
-system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data 188245 # number of ReadReq MSHR misses
-system.cpu1.dcache.ReadReq_mshr_misses::total 188245 # number of ReadReq MSHR misses
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-system.cpu1.dcache.WriteReq_mshr_misses::total 137493 # number of WriteReq MSHR misses
-system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.data 11557 # number of LoadLockedReq MSHR misses
-system.cpu1.dcache.LoadLockedReq_mshr_misses::total 11557 # number of LoadLockedReq MSHR misses
-system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.data 9900 # number of StoreCondReq MSHR misses
-system.cpu1.dcache.StoreCondReq_mshr_misses::total 9900 # number of StoreCondReq MSHR misses
-system.cpu1.dcache.demand_mshr_misses::cpu1.data 325738 # number of demand (read+write) MSHR misses
-system.cpu1.dcache.demand_mshr_misses::total 325738 # number of demand (read+write) MSHR misses
-system.cpu1.dcache.overall_mshr_misses::cpu1.data 325738 # number of overall MSHR misses
-system.cpu1.dcache.overall_mshr_misses::total 325738 # number of overall MSHR misses
-system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 2164155000 # number of ReadReq MSHR miss cycles
-system.cpu1.dcache.ReadReq_mshr_miss_latency::total 2164155000 # number of ReadReq MSHR miss cycles
-system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 3711466500 # number of WriteReq MSHR miss cycles
-system.cpu1.dcache.WriteReq_mshr_miss_latency::total 3711466500 # number of WriteReq MSHR miss cycles
-system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 97049000 # number of LoadLockedReq MSHR miss cycles
-system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total 97049000 # number of LoadLockedReq MSHR miss cycles
-system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data 52793000 # number of StoreCondReq MSHR miss cycles
-system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total 52793000 # number of StoreCondReq MSHR miss cycles
-system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 5875621500 # number of demand (read+write) MSHR miss cycles
-system.cpu1.dcache.demand_mshr_miss_latency::total 5875621500 # number of demand (read+write) MSHR miss cycles
-system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 5875621500 # number of overall MSHR miss cycles
-system.cpu1.dcache.overall_mshr_miss_latency::total 5875621500 # number of overall MSHR miss cycles
-system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 137931976000 # number of ReadReq MSHR uncacheable cycles
-system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total 137931976000 # number of ReadReq MSHR uncacheable cycles
-system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 470527000 # number of WriteReq MSHR uncacheable cycles
-system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::total 470527000 # number of WriteReq MSHR uncacheable cycles
-system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data 138402503000 # number of overall MSHR uncacheable cycles
-system.cpu1.dcache.overall_mshr_uncacheable_latency::total 138402503000 # number of overall MSHR uncacheable cycles
-system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.028812 # mshr miss rate for ReadReq accesses
-system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.025991 # mshr miss rate for WriteReq accesses
-system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.099328 # mshr miss rate for LoadLockedReq accesses
-system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.085118 # mshr miss rate for StoreCondReq accesses
-system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.027550 # mshr miss rate for demand accesses
-system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.027550 # mshr miss rate for overall accesses
-system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 11496.480650 # average ReadReq mshr miss latency
-system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 26993.857869 # average WriteReq mshr miss latency
-system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 8397.421476 # average LoadLockedReq mshr miss latency
-system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 5332.626263 # average StoreCondReq mshr miss latency
-system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 18037.875532 # average overall mshr miss latency
-system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 18037.875532 # average overall mshr miss latency
+system.cpu1.dcache.writebacks::writebacks 254584 # number of writebacks
+system.cpu1.dcache.writebacks::total 254584 # number of writebacks
+system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data 172105 # number of ReadReq MSHR misses
+system.cpu1.dcache.ReadReq_mshr_misses::total 172105 # number of ReadReq MSHR misses
+system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data 150416 # number of WriteReq MSHR misses
+system.cpu1.dcache.WriteReq_mshr_misses::total 150416 # number of WriteReq MSHR misses
+system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.data 11123 # number of LoadLockedReq MSHR misses
+system.cpu1.dcache.LoadLockedReq_mshr_misses::total 11123 # number of LoadLockedReq MSHR misses
+system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.data 9710 # number of StoreCondReq MSHR misses
+system.cpu1.dcache.StoreCondReq_mshr_misses::total 9710 # number of StoreCondReq MSHR misses
+system.cpu1.dcache.demand_mshr_misses::cpu1.data 322521 # number of demand (read+write) MSHR misses
+system.cpu1.dcache.demand_mshr_misses::total 322521 # number of demand (read+write) MSHR misses
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+system.cpu1.dcache.overall_mshr_misses::total 322521 # number of overall MSHR misses
+system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 1979754000 # number of ReadReq MSHR miss cycles
+system.cpu1.dcache.ReadReq_mshr_miss_latency::total 1979754000 # number of ReadReq MSHR miss cycles
+system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 4836439500 # number of WriteReq MSHR miss cycles
+system.cpu1.dcache.WriteReq_mshr_miss_latency::total 4836439500 # number of WriteReq MSHR miss cycles
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+system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total 91205500 # number of LoadLockedReq MSHR miss cycles
+system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data 44502000 # number of StoreCondReq MSHR miss cycles
+system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total 44502000 # number of StoreCondReq MSHR miss cycles
+system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 6816193500 # number of demand (read+write) MSHR miss cycles
+system.cpu1.dcache.demand_mshr_miss_latency::total 6816193500 # number of demand (read+write) MSHR miss cycles
+system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 6816193500 # number of overall MSHR miss cycles
+system.cpu1.dcache.overall_mshr_miss_latency::total 6816193500 # number of overall MSHR miss cycles
+system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 136553272000 # number of ReadReq MSHR uncacheable cycles
+system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total 136553272000 # number of ReadReq MSHR uncacheable cycles
+system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 39714562000 # number of WriteReq MSHR uncacheable cycles
+system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::total 39714562000 # number of WriteReq MSHR uncacheable cycles
+system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data 176267834000 # number of overall MSHR uncacheable cycles
+system.cpu1.dcache.overall_mshr_uncacheable_latency::total 176267834000 # number of overall MSHR uncacheable cycles
+system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.024175 # mshr miss rate for ReadReq accesses
+system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.030209 # mshr miss rate for WriteReq accesses
+system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.119732 # mshr miss rate for LoadLockedReq accesses
+system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.104604 # mshr miss rate for StoreCondReq accesses
+system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.026659 # mshr miss rate for demand accesses
+system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.026659 # mshr miss rate for overall accesses
+system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 11503.175387 # average ReadReq mshr miss latency
+system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 32153.756914 # average WriteReq mshr miss latency
+system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 8199.721298 # average LoadLockedReq mshr miss latency
+system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 4583.110196 # average StoreCondReq mshr miss latency
+system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 21134.107546 # average overall mshr miss latency
+system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 21134.107546 # average overall mshr miss latency
system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency
system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data inf # average WriteReq mshr uncacheable latency
system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data inf # average overall mshr uncacheable latency
system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.iocache.fast_writes 0 # number of fast writes performed
system.iocache.cache_copies 0 # number of cache copies performed
-system.iocache.ReadReq_mshr_uncacheable_latency::realview.clcd 1342252853622 # number of ReadReq MSHR uncacheable cycles
-system.iocache.ReadReq_mshr_uncacheable_latency::total 1342252853622 # number of ReadReq MSHR uncacheable cycles
-system.iocache.overall_mshr_uncacheable_latency::realview.clcd 1342252853622 # number of overall MSHR uncacheable cycles
-system.iocache.overall_mshr_uncacheable_latency::total 1342252853622 # number of overall MSHR uncacheable cycles
+system.iocache.ReadReq_mshr_uncacheable_latency::realview.clcd 550616164273 # number of ReadReq MSHR uncacheable cycles
+system.iocache.ReadReq_mshr_uncacheable_latency::total 550616164273 # number of ReadReq MSHR uncacheable cycles
+system.iocache.overall_mshr_uncacheable_latency::realview.clcd 550616164273 # number of overall MSHR uncacheable cycles
+system.iocache.overall_mshr_uncacheable_latency::total 550616164273 # number of overall MSHR uncacheable cycles
system.iocache.ReadReq_avg_mshr_uncacheable_latency::realview.clcd inf # average ReadReq mshr uncacheable latency
system.iocache.overall_avg_mshr_uncacheable_latency::realview.clcd inf # average overall mshr uncacheable latency
system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
-gem5 compiled May 8 2012 15:17:37
-gem5 started May 8 2012 16:20:58
-gem5 executing on piton
+gem5 compiled May 10 2012 12:36:36
+gem5 started May 10 2012 12:36:42
+gem5 executing on u200540-lin
command line: build/ARM/gem5.opt -d build/ARM/tests/opt/quick/fs/10.linux-boot/arm/linux/realview-simple-timing -re tests/run.py build/ARM/tests/opt/quick/fs/10.linux-boot/arm/linux/realview-simple-timing
Global frequency set at 1000000000000 ticks per second
-info: kernel located at: /dist/m5/system/binaries/vmlinux.arm.smp.fb.2.6.38.8
+info: kernel located at: /projects/pd/randd/dist/binaries/vmlinux.arm.smp.fb.2.6.38.8
info: Using bootloader at address 0x80000000
info: Entering event queue @ 0. Starting simulation...
-Exiting @ tick 2591441692000 because m5_exit instruction encountered
+Exiting @ tick 2591419000000 because m5_exit instruction encountered
---------- Begin Simulation Statistics ----------
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sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 302887 # Simulator instruction rate (inst/s)
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-host_mem_usage 384192 # Number of bytes of host memory used
-host_seconds 195.04 # Real time elapsed on the host
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+host_inst_rate 632591 # Simulator instruction rate (inst/s)
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system.physmem.num_other 0 # Number of other requests responded to by this memory
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system.realview.nvmem.bytes_read 20 # Number of bytes read from this memory
system.realview.nvmem.bytes_inst_read 20 # Number of instructions bytes read from this memory
system.realview.nvmem.bytes_written 0 # Number of bytes written to this memory
system.realview.nvmem.bw_read 8 # Total read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_inst_read 8 # Instruction read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_total 8 # Total bandwidth to/from this memory (bytes/s)
-system.l2c.replacements 117809 # number of replacements
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system.l2c.warmup_cycle 0 # Cycle when the warmup percentage was hit.
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system.l2c.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
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system.l2c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
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system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu.inst inf # average ReadReq mshr uncacheable latency
system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency
system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu.data inf # average WriteReq mshr uncacheable latency
system.cf0.dma_write_txs 0 # Number of DMA write transactions.
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system.cpu.dtb.inst_misses 0 # ITB inst misses
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system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
system.cpu.dtb.flush_tlb_mva_asid 1439 # Number of times TLB was flushed by MVA & ASID
system.cpu.dtb.flush_tlb_asid 63 # Number of times TLB was flushed by ASID
system.cpu.dtb.flush_entries 3488 # Number of entries that have been flushed from TLB
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system.cpu.dtb.inst_accesses 0 # ITB inst accesses
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system.cpu.dtb.misses 9551 # DTB misses
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system.cpu.itb.inst_misses 4471 # ITB inst misses
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system.cpu.itb.read_misses 0 # DTB read misses
system.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions
system.cpu.itb.read_accesses 0 # DTB read accesses
system.cpu.itb.write_accesses 0 # DTB write accesses
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system.cpu.itb.misses 4471 # DTB misses
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system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
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system.cpu.num_fp_register_reads 7493 # number of times the floating registers were read
system.cpu.num_fp_register_writes 2780 # number of times the floating registers were written
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system.cpu.kern.inst.arm 0 # number of arm instructions executed
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-system.cpu.dcache.ReadReq_mshr_miss_latency::total 4741074500 # number of ReadReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 8800219500 # number of WriteReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::total 8800219500 # number of WriteReq MSHR miss cycles
-system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data 151723500 # number of LoadLockedReq MSHR miss cycles
-system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 151723500 # number of LoadLockedReq MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::cpu.data 13541294000 # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::total 13541294000 # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::cpu.data 13541294000 # number of overall MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::total 13541294000 # number of overall MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 146946835000 # number of ReadReq MSHR uncacheable cycles
-system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 146946835000 # number of ReadReq MSHR uncacheable cycles
-system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data 40367455500 # number of WriteReq MSHR uncacheable cycles
-system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total 40367455500 # number of WriteReq MSHR uncacheable cycles
-system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 187314290500 # number of overall MSHR uncacheable cycles
-system.cpu.dcache.overall_mshr_uncacheable_latency::total 187314290500 # number of overall MSHR uncacheable cycles
-system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.027222 # mshr miss rate for ReadReq accesses
-system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.024519 # mshr miss rate for WriteReq accesses
-system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.046249 # mshr miss rate for LoadLockedReq accesses
-system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.026060 # mshr miss rate for demand accesses
-system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.026060 # mshr miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 12863.674596 # average ReadReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 35158.406645 # average WriteReq mshr miss latency
-system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 13249.803511 # average LoadLockedReq mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 21880.852852 # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 21880.852852 # average overall mshr miss latency
+system.cpu.dcache.writebacks::writebacks 566088 # number of writebacks
+system.cpu.dcache.writebacks::total 566088 # number of writebacks
+system.cpu.dcache.ReadReq_mshr_misses::cpu.data 368647 # number of ReadReq MSHR misses
+system.cpu.dcache.ReadReq_mshr_misses::total 368647 # number of ReadReq MSHR misses
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+system.cpu.dcache.LoadLockedReq_mshr_misses::total 11373 # number of LoadLockedReq MSHR misses
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+system.cpu.dcache.demand_mshr_misses::total 619130 # number of demand (read+write) MSHR misses
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+system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 151180500 # number of LoadLockedReq MSHR miss cycles
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+system.cpu.dcache.demand_mshr_miss_latency::total 13524762000 # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::cpu.data 13524762000 # number of overall MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::total 13524762000 # number of overall MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 146938040000 # number of ReadReq MSHR uncacheable cycles
+system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 146938040000 # number of ReadReq MSHR uncacheable cycles
+system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data 40368528500 # number of WriteReq MSHR uncacheable cycles
+system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total 40368528500 # number of WriteReq MSHR uncacheable cycles
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+system.cpu.dcache.overall_mshr_uncacheable_latency::total 187306568500 # number of overall MSHR uncacheable cycles
+system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.027178 # mshr miss rate for ReadReq accesses
+system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.024500 # mshr miss rate for WriteReq accesses
+system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.045914 # mshr miss rate for LoadLockedReq accesses
+system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.026027 # mshr miss rate for demand accesses
+system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.026027 # mshr miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 12830.916839 # average ReadReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 35110.897746 # average WriteReq mshr miss latency
+system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 13292.930625 # average LoadLockedReq mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 21844.785425 # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 21844.785425 # average overall mshr miss latency
system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency
system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu.data inf # average WriteReq mshr uncacheable latency
system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data inf # average overall mshr uncacheable latency
system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.iocache.fast_writes 0 # number of fast writes performed
system.iocache.cache_copies 0 # number of cache copies performed
-system.iocache.ReadReq_mshr_uncacheable_latency::realview.clcd 1341941439938 # number of ReadReq MSHR uncacheable cycles
-system.iocache.ReadReq_mshr_uncacheable_latency::total 1341941439938 # number of ReadReq MSHR uncacheable cycles
-system.iocache.overall_mshr_uncacheable_latency::realview.clcd 1341941439938 # number of overall MSHR uncacheable cycles
-system.iocache.overall_mshr_uncacheable_latency::total 1341941439938 # number of overall MSHR uncacheable cycles
+system.iocache.ReadReq_mshr_uncacheable_latency::realview.clcd 1342278175263 # number of ReadReq MSHR uncacheable cycles
+system.iocache.ReadReq_mshr_uncacheable_latency::total 1342278175263 # number of ReadReq MSHR uncacheable cycles
+system.iocache.overall_mshr_uncacheable_latency::realview.clcd 1342278175263 # number of overall MSHR uncacheable cycles
+system.iocache.overall_mshr_uncacheable_latency::total 1342278175263 # number of overall MSHR uncacheable cycles
system.iocache.ReadReq_avg_mshr_uncacheable_latency::realview.clcd inf # average ReadReq mshr uncacheable latency
system.iocache.overall_avg_mshr_uncacheable_latency::realview.clcd inf # average overall mshr uncacheable latency
system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate
projects / gem5.git / commitdiff