Removed SigSpec::extend_xx() api

diff --git a/kernel/rtlil.cc b/kernel/rtlil.cc
index cd2232c8c61fceff4fb16fb59e24acb2777e598b..d396d6c24555604d991f5eb5aa0229845a2b1d58 100644 (file)
--- a/kernel/rtlil.cc
+++ b/kernel/rtlil.cc
@@ -2673,24 +2673,6 @@ void RTLIL::SigSpec::append_bit(const RTLIL::SigBit &bit)
        check();
 }
 
-void RTLIL::SigSpec::extend_xx(int width, bool is_signed)
-{
-       cover("kernel.rtlil.sigspec.extend_xx");
-
-       pack();
-
-       if (width_ > width)
-               remove(width, width_ - width);
-       
-       if (width_ < width) {
-               RTLIL::SigBit padding = width_ > 0 ? (*this)[width_ - 1] : RTLIL::State::S0;
-               if (!is_signed && (padding == RTLIL::State::S1 || padding.wire))
-                       padding = RTLIL::State::S0;
-               while (width_ < width)
-                       append(padding);
-       }
-}
-
 void RTLIL::SigSpec::extend_u0(int width, bool is_signed)
 {
        cover("kernel.rtlil.sigspec.extend_u0");

diff --git a/kernel/rtlil.h b/kernel/rtlil.h
index 7618780b0a5f43933b42dc30b4d46aa32e519e70..53ee24c2253f940ccab929e5b4dc8d8c88b9c9ac 100644 (file)
--- a/kernel/rtlil.h
+++ b/kernel/rtlil.h
@@ -651,7 +651,6 @@ public:
        void append(const RTLIL::SigSpec &signal);
        void append_bit(const RTLIL::SigBit &bit);
 
-       void extend_xx(int width, bool is_signed = false);
        void extend_u0(int width, bool is_signed = false);
 
        RTLIL::SigSpec repeat(int num) const;

diff --git a/passes/proc/proc_arst.cc b/passes/proc/proc_arst.cc
index 0874d0981ae6e0b383afd918052c772be08e007c..27c6b3bcf6346d15351fe1c50cb0e4ce964131ef 100644 (file)
--- a/passes/proc/proc_arst.cc
+++ b/passes/proc/proc_arst.cc
@@ -262,7 +262,7 @@ struct ProcArstPass : public Pass {
                                                                for (auto &chunk : act.first.chunks())
                                                                        if (chunk.wire && chunk.wire->attributes.count("\\init")) {
                                                                                RTLIL::SigSpec value = chunk.wire->attributes.at("\\init");
-                                                                               value.extend_xx(chunk.wire->width, false);
+                                                                               value.extend_u0(chunk.wire->width, false);
                                                                                arst_sig.append(chunk);
                                                                                arst_val.append(value.extract(chunk.offset, chunk.width));
                                                                        }