Actually, there might not be any harm in updating sigmap...

diff --git a/passes/techmap/shregmap.cc b/passes/techmap/shregmap.cc
index 8881ba468dcd8448e251c3b7b5ff4b4fb24f9dac..d9d1e257b667b92bd4f451f9fabcf89b6d1bbcb0 100644 (file)
--- a/passes/techmap/shregmap.cc
+++ b/passes/techmap/shregmap.cc
@@ -304,11 +304,9 @@ struct ShregmapWorker
                                                // so that it can be identified as another chain
                                                // (omitting this common flop)
                                                // Link: https://github.com/YosysHQ/yosys/pull/1085
-                                               // NB: This relies on us not updating sigmap with this
-                                               //     alias otherwise it would think they are the same
-                                               //     wire
                                                Wire *wire = module->addWire(NEW_ID);
                                                module->connect(wire, d_bit);
+                                               sigmap.add(wire, d_bit);
                                                sigbit_chain_next.insert(std::make_pair(wire, cell));
                                        }