fpga/bram: Generate stall signal

This doesn't yet pipeline the block RAM, just generate a valid stall
signal so it's compatible with a pipelined master

Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>

diff --git a/fpga/mw_soc_memory.vhdl b/fpga/mw_soc_memory.vhdl
index e9ace3662a4c4e30fe7e04820ffc505819d6b0f5..af31c890e1319f9c56003298a5e9a71898affdd9 100644 (file)
--- a/fpga/mw_soc_memory.vhdl
+++ b/fpga/mw_soc_memory.vhdl
@@ -65,7 +65,8 @@ begin
 
     wb_adr_in <= wishbone_in.adr(log2(MEMORY_SIZE) - 1 downto 0);
 
-    wishbone_out.ack <= read_ack and wishbone_in.stb;
+    wishbone_out.ack <= read_ack and wishbone_in.cyc and wishbone_in.stb;
+    wishbone_out.stall <= '0' when wishbone_in.cyc = '0' else not wishbone_out.ack;
 
     memory_0: process(clk)
     begin