Fix synth_ice40 doc regarding -top default

diff --git a/techlibs/ice40/synth_ice40.cc b/techlibs/ice40/synth_ice40.cc
index 2533d3af84f3dfe2763fe668f8d999b2b29a5c3e..a49372c8aa65bd08189eb85214fe889f5df3658e 100644 (file)
--- a/techlibs/ice40/synth_ice40.cc
+++ b/techlibs/ice40/synth_ice40.cc
@@ -38,7 +38,7 @@ struct SynthIce40Pass : public ScriptPass
                log("This command runs synthesis for iCE40 FPGAs.\n");
                log("\n");
                log("    -top <module>\n");
-               log("        use the specified module as top module (default='top')\n");
+               log("        use the specified module as top module\n");
                log("\n");
                log("    -blif <file>\n");
                log("        write the design to the specified BLIF file. writing of an output file\n");