+2018-10-03 Tamar Christina <tamar.christina@arm.com>
+
+ * testsuite/gas/aarch64/sve-movprfx_1.d: New test.
+ * testsuite/gas/aarch64/sve-movprfx_1.s: New test.
+ * testsuite/gas/aarch64/sve-movprfx_10.d: New test.
+ * testsuite/gas/aarch64/sve-movprfx_10.l: New test.
+ * testsuite/gas/aarch64/sve-movprfx_10.s: New test.
+ * testsuite/gas/aarch64/sve-movprfx_11.d: New test.
+ * testsuite/gas/aarch64/sve-movprfx_11.s: New test.
+ * testsuite/gas/aarch64/sve-movprfx_12.d: New test.
+ * testsuite/gas/aarch64/sve-movprfx_12.s: New test.
+ * testsuite/gas/aarch64/sve-movprfx_13.d: New test.
+ * testsuite/gas/aarch64/sve-movprfx_13.l: New test.
+ * testsuite/gas/aarch64/sve-movprfx_13.s: New test.
+ * testsuite/gas/aarch64/sve-movprfx_14.d: New test.
+ * testsuite/gas/aarch64/sve-movprfx_14.l: New test.
+ * testsuite/gas/aarch64/sve-movprfx_14.s: New test.
+ * testsuite/gas/aarch64/sve-movprfx_15.d: New test.
+ * testsuite/gas/aarch64/sve-movprfx_15.l: New test.
+ * testsuite/gas/aarch64/sve-movprfx_15.s: New test.
+ * testsuite/gas/aarch64/sve-movprfx_16.d: New test.
+ * testsuite/gas/aarch64/sve-movprfx_16.s: New test.
+ * testsuite/gas/aarch64/sve-movprfx_17.d: New test.
+ * testsuite/gas/aarch64/sve-movprfx_17.l: New test.
+ * testsuite/gas/aarch64/sve-movprfx_17.s: New test.
+ * testsuite/gas/aarch64/sve-movprfx_18.d: New test.
+ * testsuite/gas/aarch64/sve-movprfx_18.l: New test.
+ * testsuite/gas/aarch64/sve-movprfx_18.s: New test.
+ * testsuite/gas/aarch64/sve-movprfx_19.d: New test.
+ * testsuite/gas/aarch64/sve-movprfx_19.s: New test.
+ * testsuite/gas/aarch64/sve-movprfx_2.d: New test.
+ * testsuite/gas/aarch64/sve-movprfx_2.l: New test.
+ * testsuite/gas/aarch64/sve-movprfx_2.s: New test.
+ * testsuite/gas/aarch64/sve-movprfx_20.d: New test.
+ * testsuite/gas/aarch64/sve-movprfx_20.l: New test.
+ * testsuite/gas/aarch64/sve-movprfx_20.s: New test.
+ * testsuite/gas/aarch64/sve-movprfx_21.d: New test.
+ * testsuite/gas/aarch64/sve-movprfx_21.s: New test.
+ * testsuite/gas/aarch64/sve-movprfx_22.d: New test.
+ * testsuite/gas/aarch64/sve-movprfx_22.l: New test.
+ * testsuite/gas/aarch64/sve-movprfx_22.s: New test.
+ * testsuite/gas/aarch64/sve-movprfx_23.d: New test.
+ * testsuite/gas/aarch64/sve-movprfx_23.l: New test.
+ * testsuite/gas/aarch64/sve-movprfx_23.s: New test.
+ * testsuite/gas/aarch64/sve-movprfx_24.d: New test.
+ * testsuite/gas/aarch64/sve-movprfx_24.l: New test.
+ * testsuite/gas/aarch64/sve-movprfx_24.s: New test.
+ * testsuite/gas/aarch64/sve-movprfx_25.d: New test.
+ * testsuite/gas/aarch64/sve-movprfx_25.l: New test.
+ * testsuite/gas/aarch64/sve-movprfx_25.s: New test.
+ * testsuite/gas/aarch64/sve-movprfx_26.d: New test.
+ * testsuite/gas/aarch64/sve-movprfx_26.l: New test.
+ * testsuite/gas/aarch64/sve-movprfx_26.s: New test.
+ * testsuite/gas/aarch64/sve-movprfx_3.d: New test.
+ * testsuite/gas/aarch64/sve-movprfx_3.l: New test.
+ * testsuite/gas/aarch64/sve-movprfx_3.s: New test.
+ * testsuite/gas/aarch64/sve-movprfx_4.d: New test.
+ * testsuite/gas/aarch64/sve-movprfx_4.l: New test.
+ * testsuite/gas/aarch64/sve-movprfx_4.s: New test.
+ * testsuite/gas/aarch64/sve-movprfx_5.d: New test.
+ * testsuite/gas/aarch64/sve-movprfx_5.s: New test.
+ * testsuite/gas/aarch64/sve-movprfx_6.d: New test.
+ * testsuite/gas/aarch64/sve-movprfx_6.l: New test.
+ * testsuite/gas/aarch64/sve-movprfx_6.s: New test.
+ * testsuite/gas/aarch64/sve-movprfx_7.d: New test.
+ * testsuite/gas/aarch64/sve-movprfx_7.l: New test.
+ * testsuite/gas/aarch64/sve-movprfx_7.s: New test.
+ * testsuite/gas/aarch64/sve-movprfx_8.d: New test.
+ * testsuite/gas/aarch64/sve-movprfx_8.l: New test.
+ * testsuite/gas/aarch64/sve-movprfx_8.s: New test.
+ * testsuite/gas/aarch64/sve-movprfx_9.d: New test.
+ * testsuite/gas/aarch64/sve-movprfx_9.l: New test.
+ * testsuite/gas/aarch64/sve-movprfx_9.s: New test.
+
2018-10-03 Tamar Christina <tamar.christina@arm.com>
* testsuite/gas/aarch64/sve-movprfx.d: New test.
--- /dev/null
+#source: sve-movprfx_1.s
+#as: -march=armv8-a+sve -I$srcdir/$subdir
+#objdump: -Dr -M notes
+
+.* file format .*
+
+Disassembly of section .*:
+
+0+ <.*>:
+[^:]+: 2598e3e0 ptrue p0.s
+[^:]+: 04912461 movprfx z1.s, p1/m, z3.s
+[^:]+: 0497a441 neg z1.s, p1/m, z2.s
+[^:]+: d65f03c0 ret
--- /dev/null
+/* correct usage of movprfx. No diagnosis. */
+ .text
+ .arch armv8-a+sve
+
+f:
+ ptrue p0.s
+ movprfx z1.s, p1/m, z3.s
+ neg z1.s, p1/m, z2.s
+ ret
--- /dev/null
+#source: sve-movprfx_10.s
+#warning_output: sve-movprfx_10.l
+#as: -march=armv8-a+sve -I$srcdir/$subdir
+#objdump: -Dr -M notes
+
+.* file format .*
+
+Disassembly of section .*:
+
+0+ <.*>:
+[^:]+: 2598e3e0 ptrue p0.s
+[^:]+: 04912401 movprfx z1.s, p1/m, z0.s
+[^:]+: 04d7a441 neg z1.d, p1/m, z2.d // note: register size not compatible with previous `movprfx' at operand 1
+[^:]+: d65f03c0 ret
--- /dev/null
+[^:]*: Assembler messages:
+.*: Warning: register size not compatible with previous `movprfx' at operand 1 -- `neg z1.d,p1/m,z2.d'
--- /dev/null
+/* incorrect usage of movprfx, register size is different.
+ Diagnosis required. */
+ .text
+ .arch armv8-a+sve
+
+f:
+ ptrue p0.s
+ movprfx z1.s, p1/M, z0.s
+ neg z1.d, p1/m, z2.d
+ ret
--- /dev/null
+#source: sve-movprfx_11.s
+#as: -march=armv8-a+sve -I$srcdir/$subdir
+#objdump: -Dr -M notes
+
+.* file format .*
+
+Disassembly of section .*:
+
+0+ <.*>:
+[^:]+: 2598e3e0 ptrue p0.s
+[^:]+: 0420bc01 movprfx z1, z0
+[^:]+: 04d7a041 neg z1.d, p0/m, z2.d
+[^:]+: d65f03c0 ret
--- /dev/null
+/* Correct usage of movprfx, unpredicated movprfx, any register size allowed for
+ instruction at PC+4. No diagnosis required. */
+ .text
+ .arch armv8-a+sve
+
+f:
+ ptrue p0.s
+ movprfx z1, z0
+ neg z1.d, p0/m, z2.d
+ ret
--- /dev/null
+#source: sve-movprfx_12.s
+#as: -march=armv8-a+sve -I$srcdir/$subdir
+#objdump: -Dr -M notes
+
+.* file format .*
+
+Disassembly of section .*:
+
+0+ <.*>:
+[^:]+: 2598e3e0 ptrue p0.s
+[^:]+: 04902461 movprfx z1.s, p1/z, z3.s
+[^:]+: 0497a441 neg z1.s, p1/m, z2.s
+[^:]+: d65f03c0 ret
--- /dev/null
+/* correct usage of movprfx. No diagnosis. */
+ .text
+ .arch armv8-a+sve
+
+f:
+ ptrue p0.s
+ movprfx z1.s, p1/z, z3.s
+ neg z1.s, p1/m, z2.s
+ ret
--- /dev/null
+#source: sve-movprfx_13.s
+#warning_output: sve-movprfx_13.l
+#as: -march=armv8-a+sve -I$srcdir/$subdir
+#objdump: -Dr -M notes
+
+.* file format .*
+
+Disassembly of section .*:
+
+0+ <.*>:
+[^:]+: 2598e3e0 ptrue p0.s
+[^:]+: 0420bc01 movprfx z1, z0
+
+0+8 <.*>:
+[^:]+: 0497a021 neg z1.s, p0/m, z1.s // note: output register of preceding `movprfx' used as input at operand 3
+[^:]+: d65f03c0 ret
+
--- /dev/null
+[^:]*: Assembler messages:
+.*: Warning: output register of preceding `movprfx' used as input at operand 3 -- `neg z1.s,p0/m,z1.s'
--- /dev/null
+/* Prefixed register used in valid sve instruction at PC+4. Label does not
+ change flow. Diagnostic required due to register used as input. */
+ .text
+ .arch armv8-a+sve
+
+f:
+ ptrue p0.s
+ movprfx z1, z0
+bar:
+ neg z1.s, p0/m, z1.s
+ ret
--- /dev/null
+#source: sve-movprfx_14.s
+#warning_output: sve-movprfx_14.l
+#as: -march=armv8-a+sve -I$srcdir/$subdir
+#objdump: -Dr -M notes
+
+.* file format .*
+
+Disassembly of section .*:
+
+0+ <.*>:
+[^:]+: 2598e3e0 ptrue p0.s
+[^:]+: 04912461 movprfx z1.s, p1/m, z3.s
+[^:]+: 0497a041 neg z1.s, p0/m, z2.s // note: predicate register differs from that in preceding `movprfx' at operand 2
+[^:]+: d65f03c0 ret
+
--- /dev/null
+[^:]*: Assembler messages:
+.*: Warning: predicate register differs from that in preceding `movprfx' at operand 2 -- `neg z1.s,p0/m,z2.s'
--- /dev/null
+/* incorrect usage of movprfx, predicate register not the same as movprfx.
+ Diagnosis required. */
+ .text
+ .arch armv8-a+sve
+
+f:
+ ptrue p0.s
+ movprfx z1.s, p1/m, z3.s
+ neg z1.s, p0/m, z2.s
+ ret
--- /dev/null
+#source: sve-movprfx_15.s
+#warning_output: sve-movprfx_15.l
+#as: -march=armv8-a+sve -I$srcdir/$subdir
+#objdump: -Dr -M notes
+
+.* file format .*
+
+Disassembly of section .*:
+
+0+ <.*>:
+[^:]+: 2598e3e0 ptrue p0.s
+[^:]+: 04912461 movprfx z1.s, p1/m, z3.s
+[^:]+: 04623061 orr z1.d, z3.d, z2.d // note: SVE `movprfx' compatible instruction expected
+[^:]+: d65f03c0 ret
--- /dev/null
+[^:]*: Assembler messages:
+.*: Warning: SVE `movprfx' compatible instruction expected -- `orr z1.d,z3.d,z2.d'
--- /dev/null
+/* incorrect usage of movprfx, predicated instruction not followed by predicated
+ instruction at PC+4. Diagnosis required. */
+ .text
+ .arch armv8-a+sve
+
+f:
+ ptrue p0.s
+ movprfx z1.s, p1/m, z3.s
+ orr z1.d, z3.d, z2.d
+ ret
--- /dev/null
+#source: sve-movprfx_16.s
+#as: -march=armv8-a+sve -I$srcdir/$subdir
+#objdump: -Dr -M notes
+
+.* file format .*
+
+Disassembly of section .*:
+
+0+ <.*>:
+[^:]+: 2598e3e0 ptrue p0.s
+[^:]+: 04912461 movprfx z1.s, p1/m, z3.s
+[^:]+: 6589a441 fcvt z1.s, p1/m, z2.h
+[^:]+: d65f03c0 ret
--- /dev/null
+/* movprfx's dest register must be the same width. Correct usage. No
+ diagnosis. */
+ .text
+ .arch armv8-a+sve
+
+f:
+ ptrue p0.s
+ movprfx z1.s, p1/m, z3.s
+ fcvt z1.s, p1/m, z2.h
+ ret
--- /dev/null
+#source: sve-movprfx_17.s
+#warning_output: sve-movprfx_17.l
+#as: -march=armv8-a+sve -I$srcdir/$subdir
+#objdump: -Dr -M notes
+
+.* file format .*
+
+Disassembly of section .*:
+
+0+ <.*>:
+[^:]+: 2598e3e0 ptrue p0.s
+[^:]+: 04912461 movprfx z1.s, p1/m, z3.s
+[^:]+: 65c9a441 fcvt z1.d, p1/m, z2.h // note: register size not compatible with previous `movprfx' at operand 1
+[^:]+: d65f03c0 ret
--- /dev/null
+[^:]*: Assembler messages:
+.*: Warning: register size not compatible with previous `movprfx' at operand 1 -- `fcvt z1.d,p1/m,z2.h'
--- /dev/null
+/* movprfx's dest register must be the wider of the two. Incorrect usage.
+ Diagnosis required. */
+ .text
+ .arch armv8-a+sve
+
+f:
+ ptrue p0.s
+ movprfx z1.s, p1/m, z3.s
+ fcvt z1.d, p1/m, z2.h
+ ret
--- /dev/null
+#source: sve-movprfx_18.s
+#warning_output: sve-movprfx_18.l
+#as: -march=armv8-a+sve -I$srcdir/$subdir
+#objdump: -Dr -M notes
+
+.* file format .*
+
+Disassembly of section .*:
+
+0+ <.*>:
+[^:]+: 2598e3e0 ptrue p0.s
+[^:]+: 04912461 movprfx z1.s, p1/m, z3.s
+[^:]+: 25a0c141 add z1.s, z1.s, #10 // note: predicated instruction expected after `movprfx'
+[^:]+: d65f03c0 ret
--- /dev/null
+[^:]*: Assembler messages:
+.*: Warning: predicated instruction expected after `movprfx' -- `add z1.s,z1.s,#10'
--- /dev/null
+/* predicated movprfx must be used with a predicated SVE instruction at PC+4.
+ Diagnosis required. */
+ .text
+ .arch armv8-a+sve
+
+f:
+ ptrue p0.s
+ movprfx z1.s, p1/m, z3.s
+ add z1.s, z1.s, #10
+ ret
--- /dev/null
+#source: sve-movprfx_19.s
+#as: -march=armv8-a+sve -I$srcdir/$subdir
+#objdump: -Dr -M notes
+
+.* file format .*
+
+Disassembly of section .*:
+
+0+ <.*>:
+[^:]+: 2598e3e0 ptrue p0.s
+[^:]+: 0420bc61 movprfx z1, z3
+[^:]+: 04800441 add z1.s, p1/m, z1.s, z2.s
+[^:]+: d65f03c0 ret
--- /dev/null
+/* unpredicated movprfx can be used with a predicated SVE instruction at PC+4
+ with a merging predicate. No diagnosis required. */
+ .text
+ .arch armv8-a+sve
+
+f:
+ ptrue p0.s
+ movprfx z1, z3
+ add z1.s, p1/m, z1.s, z2.s
+ ret
--- /dev/null
+#source: sve-movprfx_2.s
+#warning_output: sve-movprfx_2.l
+#as: -march=armv8-a+sve -I$srcdir/$subdir
+#objdump: -Dr -M notes
+
+.* file format .*
+
+Disassembly of section .*:
+
+0+ <.*>:
+[^:]+: 2598e3e0 ptrue p0.s
+[^:]+: 0420bc01 movprfx z1, z0
+[^:]+: 0497a042 neg z2.s, p0/m, z2.s // note: output register of preceding `movprfx' not used in current instruction at operand 1
+[^:]+: d65f03c0 ret
--- /dev/null
+[^:]*: Assembler messages:
+.*: Warning: output register of preceding `movprfx' not used in current instruction at operand 1 -- `neg z2.s,p0/m,z2.s'
--- /dev/null
+/* Prefixed register not used in valid sve instruction at PC+4.
+ Diagnostic required. */
+ .text
+ .arch armv8-a+sve
+
+f:
+ ptrue p0.s
+ movprfx z1, z0
+ neg z2.s, p0/m, z2.s
+ ret
--- /dev/null
+#source: sve-movprfx_20.s
+#warning_output: sve-movprfx_20.l
+#as: -march=armv8-a+sve -I$srcdir/$subdir
+#objdump: -Dr -M notes
+
+.* file format .*
+
+Disassembly of section .*:
+
+0+ <.*>:
+[^:]+: 2598e3e0 ptrue p0.s
+[^:]+: 0420bc61 movprfx z1, z3
+[^:]+: 04a20041 add z1.s, z2.s, z2.s // note: SVE `movprfx' compatible instruction expected
+[^:]+: d65f03c0 ret
--- /dev/null
+[^:]*: Assembler messages:
+.*: Warning: SVE `movprfx' compatible instruction expected -- `add z1.s,z2.s,z2.s'
--- /dev/null
+/* unpredicated movprfx cannot be used with a unpredicated SVE instruction at
+ PC+4 that is not valid for use following a movprfx.
+ Diagnosis required. */
+ .text
+ .arch armv8-a+sve
+
+f:
+ ptrue p0.s
+ movprfx z1, z3
+ add z1.s, z2.s, z2.s
+ ret
--- /dev/null
+#source: sve-movprfx_21.s
+#as: -march=armv8-a+sve -I$srcdir/$subdir
+#objdump: -Dr -M notes
+
+.* file format .*
+
+Disassembly of section .*:
+
+0+ <.*>:
+[^:]+: 2598e3e0 ptrue p0.s
+[^:]+: 0420bc61 movprfx z1, z3
+[^:]+: 04800441 add z1.s, p1/m, z1.s, z2.s
+[^:]+: d65f03c0 ret
--- /dev/null
+/* movprfx dest register can be used in destructive operations where required.
+ Valid usage. No diagnosis required. */
+ .text
+ .arch armv8-a+sve
+
+f:
+ ptrue p0.s
+ movprfx z1, z3
+ add z1.s, p1/m, z1.s, z2.s
+ ret
--- /dev/null
+#source: sve-movprfx_22.s
+#warning_output: sve-movprfx_22.l
+#as: -march=armv8-a+sve -I$srcdir/$subdir
+#objdump: -Dr -M notes
+
+.* file format .*
+
+Disassembly of section .*:
+
+0+ <.*>:
+[^:]+: 2598e3e0 ptrue p0.s
+[^:]+: 0420bc61 movprfx z1, z3
+[^:]+: 04800421 add z1.s, p1/m, z1.s, z1.s // note: output register of preceding `movprfx' used as input at operand 4
+[^:]+: d65f03c0 ret
--- /dev/null
+[^:]*: Assembler messages:
+.*: Warning: output register of preceding `movprfx' used as input at operand 4 -- `add z1.s,p1/m,z1.s,z1.s'
--- /dev/null
+/* movprfx dest register can be used in destructive operations where required,
+ but no where else. Invalid usage. Diagnosis required. */
+ .text
+ .arch armv8-a+sve
+
+f:
+ ptrue p0.s
+ movprfx z1, z3
+ add z1.s, p1/m, z1.s, z1.s
+ ret
--- /dev/null
+#source: sve-movprfx_23.s
+#warning_output: sve-movprfx_23.l
+#as: -march=armv8-a+sve -I$srcdir/$subdir
+#objdump: -Dr -M notes
+
+.* file format .*
+
+Disassembly of section .*:
+
+0+ <.*>:
+[^:]+: 04512461 movprfx z1.h, p1/m, z3.h
+[^:]+: 256c8021 incp z1.h, p1 // note: merging predicate expected due to preceding `movprfx' at operand 2
+[^:]+: 04912461 movprfx z1.s, p1/m, z3.s
+[^:]+: 25ac8021 incp z1.s, p1 // note: merging predicate expected due to preceding `movprfx' at operand 2
+[^:]+: 04d12461 movprfx z1.d, p1/m, z3.d
+[^:]+: 25ec8021 incp z1.d, p1 // note: merging predicate expected due to preceding `movprfx' at operand 2
+[^:]+: 04512461 movprfx z1.h, p1/m, z3.h
+[^:]+: 256d8021 decp z1.h, p1 // note: merging predicate expected due to preceding `movprfx' at operand 2
+[^:]+: 04912461 movprfx z1.s, p1/m, z3.s
+[^:]+: 25ad8021 decp z1.s, p1 // note: merging predicate expected due to preceding `movprfx' at operand 2
+[^:]+: 04d12461 movprfx z1.d, p1/m, z3.d
+[^:]+: 25ed8021 decp z1.d, p1 // note: merging predicate expected due to preceding `movprfx' at operand 2
+[^:]+: 04512461 movprfx z1.h, p1/m, z3.h
+[^:]+: 25688021 sqincp z1.h, p1 // note: merging predicate expected due to preceding `movprfx' at operand 2
+[^:]+: 04912461 movprfx z1.s, p1/m, z3.s
+[^:]+: 25a88021 sqincp z1.s, p1 // note: merging predicate expected due to preceding `movprfx' at operand 2
+[^:]+: 04d12461 movprfx z1.d, p1/m, z3.d
+[^:]+: 25e88021 sqincp z1.d, p1 // note: merging predicate expected due to preceding `movprfx' at operand 2
+[^:]+: 04512461 movprfx z1.h, p1/m, z3.h
+[^:]+: 256a8021 sqdecp z1.h, p1 // note: merging predicate expected due to preceding `movprfx' at operand 2
+[^:]+: 04912461 movprfx z1.s, p1/m, z3.s
+[^:]+: 25aa8021 sqdecp z1.s, p1 // note: merging predicate expected due to preceding `movprfx' at operand 2
+[^:]+: 04d12461 movprfx z1.d, p1/m, z3.d
+[^:]+: 25ea8021 sqdecp z1.d, p1 // note: merging predicate expected due to preceding `movprfx' at operand 2
+[^:]+: 04112461 movprfx z1.b, p1/m, z3.b
+[^:]+: 05288421 clasta z1.b, p1, z1.b, z1.b // note: merging predicate expected due to preceding `movprfx' at operand 2
+[^:]+: 04512461 movprfx z1.h, p1/m, z3.h
+[^:]+: 05688421 clasta z1.h, p1, z1.h, z1.h // note: merging predicate expected due to preceding `movprfx' at operand 2
+[^:]+: 04912461 movprfx z1.s, p1/m, z3.s
+[^:]+: 05a88421 clasta z1.s, p1, z1.s, z1.s // note: merging predicate expected due to preceding `movprfx' at operand 2
+[^:]+: 04d12461 movprfx z1.d, p1/m, z3.d
+[^:]+: 05e88421 clasta z1.d, p1, z1.d, z1.d // note: merging predicate expected due to preceding `movprfx' at operand 2
+[^:]+: 04112461 movprfx z1.b, p1/m, z3.b
+[^:]+: 05298421 clastb z1.b, p1, z1.b, z1.b // note: merging predicate expected due to preceding `movprfx' at operand 2
+[^:]+: 04512461 movprfx z1.h, p1/m, z3.h
+[^:]+: 05698421 clastb z1.h, p1, z1.h, z1.h // note: merging predicate expected due to preceding `movprfx' at operand 2
+[^:]+: 04912461 movprfx z1.s, p1/m, z3.s
+[^:]+: 05a98421 clastb z1.s, p1, z1.s, z1.s // note: merging predicate expected due to preceding `movprfx' at operand 2
+[^:]+: 04d12461 movprfx z1.d, p1/m, z3.d
+[^:]+: 05e98421 clastb z1.d, p1, z1.d, z1.d // note: merging predicate expected due to preceding `movprfx' at operand 2
+[^:]+: d65f03c0 ret
--- /dev/null
+[^:]*: Assembler messages:
+.*: Warning: merging predicate expected due to preceding `movprfx' at operand 2 -- `incp z1.h,p1'
+.*: Warning: merging predicate expected due to preceding `movprfx' at operand 2 -- `incp z1.s,p1'
+.*: Warning: merging predicate expected due to preceding `movprfx' at operand 2 -- `incp z1.d,p1'
+.*: Warning: merging predicate expected due to preceding `movprfx' at operand 2 -- `decp z1.h,p1'
+.*: Warning: merging predicate expected due to preceding `movprfx' at operand 2 -- `decp z1.s,p1'
+.*: Warning: merging predicate expected due to preceding `movprfx' at operand 2 -- `decp z1.d,p1'
+.*: Warning: merging predicate expected due to preceding `movprfx' at operand 2 -- `sqincp z1.h,p1'
+.*: Warning: merging predicate expected due to preceding `movprfx' at operand 2 -- `sqincp z1.s,p1'
+.*: Warning: merging predicate expected due to preceding `movprfx' at operand 2 -- `sqincp z1.d,p1'
+.*: Warning: merging predicate expected due to preceding `movprfx' at operand 2 -- `sqdecp z1.h,p1'
+.*: Warning: merging predicate expected due to preceding `movprfx' at operand 2 -- `sqdecp z1.s,p1'
+.*: Warning: merging predicate expected due to preceding `movprfx' at operand 2 -- `sqdecp z1.d,p1'
+.*: Warning: merging predicate expected due to preceding `movprfx' at operand 2 -- `clasta z1.b,p1,z1.b,z1.b'
+.*: Warning: merging predicate expected due to preceding `movprfx' at operand 2 -- `clasta z1.h,p1,z1.h,z1.h'
+.*: Warning: merging predicate expected due to preceding `movprfx' at operand 2 -- `clasta z1.s,p1,z1.s,z1.s'
+.*: Warning: merging predicate expected due to preceding `movprfx' at operand 2 -- `clasta z1.d,p1,z1.d,z1.d'
+.*: Warning: merging predicate expected due to preceding `movprfx' at operand 2 -- `clastb z1.b,p1,z1.b,z1.b'
+.*: Warning: merging predicate expected due to preceding `movprfx' at operand 2 -- `clastb z1.h,p1,z1.h,z1.h'
+.*: Warning: merging predicate expected due to preceding `movprfx' at operand 2 -- `clastb z1.s,p1,z1.s,z1.s'
+.*: Warning: merging predicate expected due to preceding `movprfx' at operand 2 -- `clastb z1.d,p1,z1.d,z1.d'
--- /dev/null
+/* Instructions not allowed to be used with predicated movprfx. Invalid usage.
+ Diagnosis required. */
+ .text
+ .arch armv8-a+sve
+
+ /* All of these should be invalid because the predicated movprfx is used
+ with an unpredicated instruction. */
+
+ .macro test_sametwo inst
+ .irp sz, h,s,d
+ movprfx z1.\sz, p1/m, z3.\sz
+ \inst z1.\sz, p1
+ .endr
+ .endm
+
+ .macro test_samethree inst
+ .irp sz, b,h,s,d
+ movprfx z1.\sz, p1/m, z3.\sz
+ \inst z1.\sz, p1, z1.\sz, z1.\sz
+ .endr
+ .endm
+
+
+f:
+ test_sametwo incp
+ test_sametwo decp
+
+ test_sametwo sqincp
+ test_sametwo sqdecp
+
+ test_samethree clasta
+ test_samethree clastb
+ ret
+
--- /dev/null
+#source: sve-movprfx_24.s
+#warning_output: sve-movprfx_24.l
+#as: -march=armv8-a+sve -I$srcdir/$subdir
+#objdump: -Dr -M notes
+
+.* file format .*
+
+Disassembly of section .*:
+
+0+ <.*>:
+[^:]+: 04d12461 movprfx z1.d, p1/m, z3.d
+[^:]+: 04db0441 bic z1.d, p1/m, z1.d, z2.d
+[^:]+: 04d12461 movprfx z1.d, p1/m, z3.d
+[^:]+: 04e23021 bic z1.d, z1.d, z2.d // note: SVE `movprfx' compatible instruction expected
+[^:]+: 0420bc61 movprfx z1, z3
+[^:]+: 04e23021 bic z1.d, z1.d, z2.d // note: SVE `movprfx' compatible instruction expected
+[^:]+: 04d12461 movprfx z1.d, p1/m, z3.d
+[^:]+: 0583e7a1 and z1.d, z1.d, #0xfffffffffffffff3 // note: predicated instruction expected after `movprfx'
+[^:]+: 0420bc61 movprfx z1, z3
+[^:]+: 0583e7a1 and z1.d, z1.d, #0xfffffffffffffff3
+[^:]+: 0420bc61 movprfx z1, z3
+[^:]+: 0543e7a1 eor z1.d, z1.d, #0xfffffffffffffff3
+[^:]+: 0420bc61 movprfx z1, z3
+[^:]+: 0503f021 orr z1.d, z1.d, #0xc
+[^:]+: d65f03c0 ret
--- /dev/null
+[^:]*: Assembler messages:
+.*: Warning: SVE `movprfx' compatible instruction expected -- `bic z1.D,z1.D,z2.D'
+.*: Warning: SVE `movprfx' compatible instruction expected -- `bic z1.D,z1.D,z2.D'
+.*: Warning: predicated instruction expected after `movprfx' -- `bic z1.D,z1.D,#12'
--- /dev/null
+/* Only predicated vector BIC is allowed following a movprfx, and some pseudo
+ instructions should be allowed due to the instructions they alias.
+ Has invalid usages. Diagnosis required. */
+ .text
+ .arch armv8-a+sve
+
+f:
+ /* OK, vectored predicated. */
+ movprfx z1.D, p1/m, z3.D
+ bic z1.D, p1/M, z1.D, z2.D
+
+ /* Not OK, vectored unpredicated. */
+ movprfx z1.D, p1/m, z3.D
+ bic z1.D, z1.D, z2.D
+
+ /* Not OK, vectored unpredicated. */
+ movprfx z1, z3
+ bic z1.D, z1.D, z2.D
+
+ /* Not OK, immediate form, unpredicated. */
+ movprfx z1.D, p1/m, z3.D
+ bic z1.D, z1.D, #12
+
+ /* OK, immediate form alias of AND which is allowed. */
+ movprfx z1, z3
+ bic z1.D, z1.D, #12
+
+ /* OK, immediate form alias of EOR which is allowed. */
+ movprfx z1, z3
+ eon z1.D, z1.D, #12
+
+ /* OK, immediate form alias of ORR which is allowed. */
+ movprfx z1, z3
+ orr z1.D, z1.D, #12
+ ret
+
--- /dev/null
+#source: sve-movprfx_25.s
+#warning_output: sve-movprfx_25.l
+#as: -march=armv8-a+sve -I$srcdir/$subdir
+#objdump: -Dr -M notes
+
+.* file format .*
+
+Disassembly of section .*:
+
+0+ <.*>:
+[^:]+: 04d12461 movprfx z1.d, p1/m, z3.d
+[^:]+: 05d14181 mov z1.d, p1/m, #12
+[^:]+: 04d12461 movprfx z1.d, p1/m, z3.d
+[^:]+: 05d14001 mov z1.d, p1/m, #0
+[^:]+: 04d12461 movprfx z1.d, p1/m, z3.d
+[^:]+: 05d14001 mov z1.d, p1/m, #0
+[^:]+: 04d12461 movprfx z1.d, p1/m, z3.d
+[^:]+: 05d94181 mov z1.d, p9/m, #12 // note: predicate register differs from that in preceding `movprfx' at operand 2
+[^:]+: 04d12461 movprfx z1.d, p1/m, z3.d
+[^:]+: 05d10181 mov z1.d, p1/z, #12 // note: merging predicate expected due to preceding `movprfx' at operand 2
+[^:]+: 04d12461 movprfx z1.d, p1/m, z3.d
+[^:]+: 05e8a441 mov z1.d, p1/m, x2
+[^:]+: 04d12461 movprfx z1.d, p1/m, z3.d
+[^:]+: 05e8a421 mov z1.d, p1/m, x1 // note: output register of preceding `movprfx' used as input at operand 3
+[^:]+: 04d12461 movprfx z1.d, p1/m, z3.d
+[^:]+: 05e08441 mov z1.d, p1/m, d2
+[^:]+: 04d12461 movprfx z1.d, p1/m, z3.d
+[^:]+: 05e08421 mov z1.d, p1/m, d1 // note: output register of preceding `movprfx' used as input at operand 3
+[^:]+: d65f03c0 ret
--- /dev/null
+[^:]*: Assembler messages:
+.*: Warning: predicate register differs from that in preceding `movprfx' at operand 2 -- `cpy z1.d,p9/m,#12'
+.*: Warning: merging predicate expected due to preceding `movprfx' at operand 2 -- `cpy z1.d,p1/z,#12'
+.*: Warning: output register of preceding `movprfx' used as input at operand 3 -- `cpy z1.d,p1/m,x1'
+.*: Warning: output register of preceding `movprfx' used as input at operand 3 -- `cpy z1.d,p1/m,d1'
--- /dev/null
+/* Checks that CPY is allowed after a movprfx, special case in that SIMD&Scalar
+ version is also valid and Pg is 4 bits rather than 3.
+ Has invalid usages. Diagnosis required. */
+ .text
+ .arch armv8-a+sve
+
+f:
+ /* OK, immediate predicated, alias mov. */
+ movprfx z1.d, p1/m, z3.d
+ cpy z1.d, p1/m, #12
+
+ /* OK, immediate predicated, alias mov, fmov. */
+ movprfx z1.d, p1/m, z3.d
+ cpy z1.d, p1/m, #0
+
+ /* OK, immediate predicated, alias mov. */
+ movprfx z1.d, p1/m, z3.d
+ fmov z1.d, p1/m, #0
+
+ /* Not OK, immediate predicated, but different predicate registers. */
+ movprfx z1.d, p1/m, z3.d
+ cpy z1.d, p9/m, #12
+
+ /* Not OK, zeroing predicate. */
+ movprfx z1.d, p1/m, z3.d
+ cpy z1.d, p1/z, #12
+
+ /* OK, scalar predicated, alias mov. */
+ movprfx z1.d, p1/m, z3.d
+ cpy z1.d, p1/m, x2
+
+ /* Not OK, scalar but register z1 and x1 are architecturally the same. */
+ movprfx z1.d, p1/m, z3.d
+ cpy z1.d, p1/m, x1
+
+ /* OK, SIMD&FP predicated, alias mov */
+ movprfx z1.d, p1/m, z3.d
+ cpy z1.d, p1/m, d2
+
+ /* Not OK, SIMD&FP predicated, but register d1 is architecturally the
+ same. */
+ movprfx z1.d, p1/m, z3.d
+ cpy z1.d, p1/m, d1
+ ret
+
--- /dev/null
+#source: sve-movprfx_26.s
+#warning_output: sve-movprfx_26.l
+#as: -march=armv8-a+sve -I$srcdir/$subdir
+#objdump: -Dr -M notes
+
+.* file format .*
+
+Disassembly of section .*:
+
+0+ <.*>:
+[^:]+: 04912420 movprfx z0.s, p1/m, z1.s
+[^:]+: 65caa440 fcvt z0.s, p1/m, z2.d // note: register size not compatible with previous `movprfx' at operand 1
+[^:]+: 04d12420 movprfx z0.d, p1/m, z1.d
+[^:]+: 65caa440 fcvt z0.s, p1/m, z2.d
+[^:]+: 04912420 movprfx z0.s, p1/m, z1.s
+[^:]+: 65cba440 fcvt z0.d, p1/m, z2.s // note: register size not compatible with previous `movprfx' at operand 1
+[^:]+: 04d12420 movprfx z0.d, p1/m, z1.d
+[^:]+: 65cba440 fcvt z0.d, p1/m, z2.s
+[^:]+: 04112420 movprfx z0.b, p1/m, z1.b
+[^:]+: 041b8440 lsl z0.b, p1/m, z0.b, z2.d
+[^:]+: 04d12420 movprfx z0.d, p1/m, z1.d
+[^:]+: 041b8440 lsl z0.b, p1/m, z0.b, z2.d // note: register size not compatible with previous `movprfx' at operand 1
+[^:]+: d65f03c0 ret
--- /dev/null
+[^:]*: Assembler messages:
+.*: Warning: register size not compatible with previous `movprfx' at operand 1 -- `fcvt Z0.S,P1/M,Z2.D'
+.*: Warning: register size not compatible with previous `movprfx' at operand 1 -- `fcvt Z0.D,P1/M,Z2.S'
+.*: Warning: register size not compatible with previous `movprfx' at operand 1 -- `lsl Z0.B,P1/M,Z0.B,Z2.D'
\ No newline at end of file
--- /dev/null
+/* Checks the special cases for FCVT and LSL.
+ Has invalid usages. Diagnosis required. */
+ .text
+ .arch armv8-a+sve
+
+f:
+ /* Not OK, 64-bit operation, upper 32-bits cleared. */
+ movprfx Z0.S, P1/M, Z1.S
+ fcvt Z0.S, P1/M, Z2.D
+
+ /* OK, 64-bit operation, upper 32-bits cleared. */
+ movprfx Z0.D, P1/M, Z1.D
+ fcvt Z0.S, P1/M, Z2.D
+
+ /* Not OK, 64-bit operation ignoring 32-bits. */
+ movprfx Z0.S, P1/M, Z1.S
+ fcvt Z0.D, P1/M, Z2.S
+
+ /* OK, 64-bit operation ignoring 32-bits. */
+ movprfx Z0.D, P1/M, Z1.D
+ fcvt Z0.D, P1/M, Z2.S
+
+ /* OK, 8-bit operation. */
+ movprfx Z0.B, P1/M, Z1.B
+ lsl Z0.B, P1/M, Z0.B, Z2.D
+
+ /* Not Ok, destination register sizes don't match. */
+ movprfx Z0.D, P1/M, Z1.D
+ lsl Z0.B, P1/M, Z0.B, Z2.D
+ ret
+
--- /dev/null
+#source: sve-movprfx_3.s
+#warning_output: sve-movprfx_3.l
+#as: -march=armv8-a+sve -I$srcdir/$subdir
+#objdump: -Dr -M notes
+
+.* file format .*
+
+Disassembly of section .*:
+
+0+ <.*>:
+[^:]+: 2598e3e0 ptrue p0.s
+[^:]+: 0420bc01 movprfx z1, z0
+[^:]+: 0497a021 neg z1.s, p0/m, z1.s // note: output register of preceding `movprfx' used as input at operand 3
+[^:]+: d65f03c0 ret
--- /dev/null
+[^:]*: Assembler messages:
+.*: Warning: output register of preceding `movprfx' used as input at operand 3 -- `neg z1.s,p0/m,z1.s'
--- /dev/null
+/* Prefixed register used as input on valid sve instruction at PC+4.
+ Diagnostic required. */
+ .text
+ .arch armv8-a+sve
+
+f:
+ ptrue p0.s
+ movprfx z1, z0
+ neg z1.s, p0/m, z1.s
+ ret
--- /dev/null
+#source: sve-movprfx_4.s
+#warning_output: sve-movprfx_4.l
+#as: -march=armv8-a+sve -I$srcdir/$subdir
+#objdump: -Dr -M notes
+
+.* file format .*
+
+Disassembly of section .*:
+
+0+ <.*>:
+[^:]+: 2598e3e0 ptrue p0.s
+[^:]+: 0420bc01 movprfx z1, z0
--- /dev/null
+[^:]*: Assembler messages:
+.*: Warning: previous `movprfx' sequence has not been closed
--- /dev/null
+/* Prefixed register not used, movprfx last instruction.
+ Diagnostic required. */
+ .text
+ .arch armv8-a+sve
+
+f:
+ ptrue p0.s
+ movprfx z1, z0
--- /dev/null
+#source: sve-movprfx_5.s
+#as: -march=armv8-a+sve -I$srcdir/$subdir
+#objdump: -Dr -M notes
+
+.* file format .*
+
+Disassembly of section .*:
+
+0+ <.*>:
+[^:]+: 2598e3e0 ptrue p0.s
+[^:]+: 0420bc01 movprfx z1, z0
+
+0+8 <.*>:
+[^:]+: 0497a041 neg z1.s, p0/m, z2.s
+[^:]+: d65f03c0 ret
--- /dev/null
+/* Prefixed register used in valid sve instruction at PC+4. Label does not
+ change flow. No Diagnostic. */
+ .text
+ .arch armv8-a+sve
+
+f:
+ ptrue p0.s
+ movprfx z1, z0
+bar:
+ neg z1.s, p0/m, z2.s
+ ret
--- /dev/null
+#source: sve-movprfx_6.s
+#warning_output: sve-movprfx_6.l
+#as: -march=armv8-a+sve -I$srcdir/$subdir
+#objdump: -Dr -M notes
+
+.* file format .*
+
+Disassembly of section .*:
+
+0+ <.*>:
+[^:]+: 2598e3e0 ptrue p0.s
+[^:]+: 0420bc01 movprfx z1, z0
+[^:]+: 0420bc62 movprfx z2, z3 // note: instruction opens new dependency sequence without ending previous one
+[^:]+: 0497a042 neg z2.s, p0/m, z2.s // note: output register of preceding `movprfx' used as input at operand 3
+[^:]+: d65f03c0 ret
--- /dev/null
+[^:]*: Assembler messages:
+.*: Warning: instruction opens new dependency sequence without ending previous one -- `movprfx z2,z3'
+.*: Warning: output register of preceding `movprfx' used as input at operand 3 -- `neg z2.s,p0/m,z2.s'
--- /dev/null
+/* Prefixed register used in valid sve instruction at PC+4, but used as input
+ as well. Prefix block opened twice without closing first one.
+ Two diagnosis required. */
+ .text
+ .arch armv8-a+sve
+
+f:
+ ptrue p0.s
+ movprfx z1, z0
+ movprfx z2, z3
+ neg z2.s, p0/m, z2.s
+ ret
--- /dev/null
+#source: sve-movprfx_7.s
+#warning_output: sve-movprfx_7.l
+#as: -march=armv8-a+sve -I$srcdir/$subdir
+#objdump: -Dr -M notes
+
+.* file format .*
+
+Disassembly of section .*:
+
+0+ <.*>:
+[^:]+: 2598e3e0 ptrue p0.s
+[^:]+: 0420bc01 movprfx z1, z0
+
+Disassembly of section .*:
+
+0+ <.*>:
+[^:]+: d65f03c0 ret // note: previous `movprfx' sequence not closed
\ No newline at end of file
--- /dev/null
+[^:]*: Assembler messages:
+.*: Warning: previous `movprfx' sequence has not been closed
--- /dev/null
+/* New section started without sequence closed. Diagnostic required. */
+ .text
+ .arch armv8-a+sve
+
+f:
+ ptrue p0.s
+ movprfx z1, z0
+ .section foo
+g:
+ ret
--- /dev/null
+#source: sve-movprfx_8.s
+#warning_output: sve-movprfx_8.l
+#as: -march=armv8-a+sve -I$srcdir/$subdir
+#objdump: -Dr -M notes
+
+.* file format .*
+
+Disassembly of section .*:
+
+0+ <.*>:
+[^:]+: 2598e3e0 ptrue p0.s
+[^:]+: 0420bc01 movprfx z1, z0
+
+Disassembly of section .*:
+
+0+ <.*>:
+[^:]+: 0497a041 neg z1.s, p0/m, z2.s // note: previous `movprfx' sequence not closed
+[^:]+: d65f03c0 ret
--- /dev/null
+[^:]*: Assembler messages:
+.*: Warning: previous `movprfx' sequence has not been closed
--- /dev/null
+/* New section started without sequence closed. Diagnostic required. */
+ .text
+ .arch armv8-a+sve
+
+f:
+ ptrue p0.s
+ movprfx z1, z0
+ .section foo
+ neg z1.s, p0/m, z2.s
+ ret
--- /dev/null
+#source: sve-movprfx_9.s
+#warning_output: sve-movprfx_9.l
+#as: -march=armv8-a+sve -I$srcdir/$subdir
+#objdump: -Dr -M notes
+
+.* file format .*
+
+Disassembly of section .*:
+
+0+ <.*>:
+[^:]+: 2598e3e0 ptrue p0.s
+[^:]+: 0420bc01 movprfx z1, z0
+[^:]+: 910003e0 mov x0, sp // note: SVE instruction expected after `movprfx'
+[^:]+: 0497a042 neg z2.s, p0/m, z2.s
+[^:]+: d65f03c0 ret
--- /dev/null
+[^:]*: Assembler messages:
+.*: Warning: SVE instruction expected after `movprfx' -- `mov x0,sp'
--- /dev/null
+/* Instruction at PC+4 after prefix sequence opening is not an SVE instruction.
+ Diagnostic required. */
+ .text
+ .arch armv8-a+sve
+
+f:
+ ptrue p0.s
+ movprfx z1, z0
+ mov x0, sp
+ neg z2.s, p0/m, z2.s
+ ret
projects / binutils-gdb.git / commitdiff