cores/cpu: add riscv-none-embed toolchain support to riscv32 cpus

diff --git a/litex/soc/cores/cpu/minerva/core.py b/litex/soc/cores/cpu/minerva/core.py
index 7319454639ec1a102954cf0e2c12f8151f2555d5..05007cf5152422115109b7a5fc79ca6666260f74 100644 (file)
--- a/litex/soc/cores/cpu/minerva/core.py
+++ b/litex/soc/cores/cpu/minerva/core.py
@@ -22,7 +22,7 @@ class Minerva(Module):
 
     @property
     def gcc_triple(self):
-        return ("riscv64-unknown-elf", "riscv32-unknown-elf")
+        return ("riscv64-unknown-elf", "riscv32-unknown-elf", "riscv-none-embed")
 
     @property
     def gcc_flags(self):

diff --git a/litex/soc/cores/cpu/picorv32/core.py b/litex/soc/cores/cpu/picorv32/core.py
index 40b9c5b646181b8e39d182b2cca570929b3d44f7..7a3c5600e93cc5719292ccb1c988c152e68d7422 100644 (file)
--- a/litex/soc/cores/cpu/picorv32/core.py
+++ b/litex/soc/cores/cpu/picorv32/core.py
@@ -40,7 +40,7 @@ class PicoRV32(Module):
 
     @property
     def gcc_triple(self):
-        return ("riscv64-unknown-elf", "riscv32-unknown-elf")
+        return ("riscv64-unknown-elf", "riscv32-unknown-elf", "riscv-none-embed")
 
     @property
     def gcc_flags(self):

diff --git a/litex/soc/cores/cpu/vexriscv/core.py b/litex/soc/cores/cpu/vexriscv/core.py
index 2111375ba42973a94c73eeae3d6955d4dae5d684..6c6cc08b422a0b449d8f085b889afc273f20387b 100644 (file)
--- a/litex/soc/cores/cpu/vexriscv/core.py
+++ b/litex/soc/cores/cpu/vexriscv/core.py
@@ -84,7 +84,7 @@ class VexRiscv(Module, AutoCSR):
 
     @property
     def gcc_triple(self):
-        return ("riscv64-unknown-elf", "riscv32-unknown-elf")
+        return ("riscv64-unknown-elf", "riscv32-unknown-elf", "riscv-none-embed")
 
     @property
     def gcc_flags(self):