opcodes/ChangeLog

	* ppc-opc.c (powerpc_opcodes): Changed opcode for vabsdub,
	vabsduh, vabsduw, mviwsplt.
gas/testsuite/ChangeLog
	* gas/ppc/e6500.d: Changed opcode for vabsdub, vabsduh, vabsduw,
	mviwsplt.

diff --git a/gas/testsuite/ChangeLog b/gas/testsuite/ChangeLog
index dd4073ae65ca46228ca49407a08872bbaa7b63db..bf5c3fc1d67963fe4c265be247a00ce21be62a6d 100644 (file)
--- a/gas/testsuite/ChangeLog
+++ b/gas/testsuite/ChangeLog
@@ -1,3 +1,8 @@
+2012-08-20  Edmar Wienskoski  <edmar@freescale.com>
+
+       * gas/ppc/e6500.d: Changed opcode for vabsdub, vabsduh, vabsduw,
+       mviwsplt.
+
 2012-08-17  Nagajyothi Eggone  <nagajyothi.eggone@amd.com>
 
        * gas/i386/i386.exp: Run btver1 and btver2 test cases.
@@ -36,15 +41,15 @@
        * gas/mmix/err-fb-2.s: New test.
 
 2012-08-13  Ian Bolton  <ian.bolton@arm.com>
-            Laurent Desnogues  <laurent.desnogues@arm.com>
-            Jim MacArthur  <jim.macarthur@arm.com>
-            Marcus Shawcroft  <marcus.shawcroft@arm.com>
-            Nigel Stephens  <nigel.stephens@arm.com>
-            Ramana Radhakrishnan  <ramana.radhakrishnan@arm.com>
-            Richard Earnshaw  <rearnsha@arm.com>
-            Sofiane Naci  <sofiane.naci@arm.com>
-            Tejas Belagod  <tejas.belagod@arm.com>
-            Yufeng Zhang  <yufeng.zhang@arm.com>
+           Laurent Desnogues  <laurent.desnogues@arm.com>
+           Jim MacArthur  <jim.macarthur@arm.com>
+           Marcus Shawcroft  <marcus.shawcroft@arm.com>
+           Nigel Stephens  <nigel.stephens@arm.com>
+           Ramana Radhakrishnan  <ramana.radhakrishnan@arm.com>
+           Richard Earnshaw  <rearnsha@arm.com>
+           Sofiane Naci  <sofiane.naci@arm.com>
+           Tejas Belagod  <tejas.belagod@arm.com>
+           Yufeng Zhang  <yufeng.zhang@arm.com>
 
        * gas/aarch64: New directory.
        * gas/aarch64/aarch64.exp: New file.

diff --git a/gas/testsuite/gas/ppc/e6500.d b/gas/testsuite/gas/ppc/e6500.d
index 892f144cad2aae08f743760528d7fb9ff46c1911..079b35cffdb2bb5e6d9baea72c40118d49dc4a3c 100644 (file)
--- a/gas/testsuite/gas/ppc/e6500.d
+++ b/gas/testsuite/gas/ppc/e6500.d
@@ -7,11 +7,11 @@
 Disassembly of section \.text:
 
 0+00 <start>:
-   0:  10 01 10 c0     vabsdub v0,v1,v2
-   4:  10 01 11 00     vabsduh v0,v1,v2
-   8:  10 01 11 40     vabsduw v0,v1,v2
+   0:  10 01 14 03     vabsdub v0,v1,v2
+   4:  10 01 14 43     vabsduh v0,v1,v2
+   8:  10 01 14 83     vabsduw v0,v1,v2
    c:  7c 01 10 dc     mvidsplt v0,r1,r2
-  10:  7c 01 11 1c     mviwsplt v0,r1,r2
+  10:  7c 01 10 5c     mviwsplt v0,r1,r2
   14:  7c 00 12 0a     lvexbx  v0,0,r2
   18:  7c 01 12 0a     lvexbx  v0,r1,r2
   1c:  7c 00 12 4a     lvexhx  v0,0,r2

diff --git a/opcodes/ChangeLog b/opcodes/ChangeLog
index 240fcaed67a448dc5b25409a790a68cd2a44f0a6..dac1ed9db561d0e995db6c57f0ed3da8daa7e9c3 100644 (file)
--- a/opcodes/ChangeLog
+++ b/opcodes/ChangeLog
@@ -1,9 +1,14 @@
+2012-08-20  Edmar Wienskoski  <edmar@freescale.com>
+
+       * ppc-opc.c (powerpc_opcodes): Changed opcode for vabsdub,
+       vabsduh, vabsduw, mviwsplt.
+
 2012-08-17  Nagajyothi Eggone  <nagajyothi.eggone@amd.com>
 
        * i386-gen.c (cpu_flag_init): Add CPU_BTVER1_FLAGS and
        CPU_BTVER2_FLAGS.
 
-       * i386-opc.h: Update CpuPRFCHW comment. 
+       * i386-opc.h: Update CpuPRFCHW comment.
 
        * i386-opc.tbl: Enable prefetch instruction for CpuPRFCHW.
        * i386-init.h: Regenerated.
@@ -53,15 +58,15 @@
        the instruction word.
 
 2012-08-13  Ian Bolton  <ian.bolton@arm.com>
-            Laurent Desnogues  <laurent.desnogues@arm.com>
-            Jim MacArthur  <jim.macarthur@arm.com>
-            Marcus Shawcroft  <marcus.shawcroft@arm.com>
-            Nigel Stephens  <nigel.stephens@arm.com>
-            Ramana Radhakrishnan  <ramana.radhakrishnan@arm.com>
-            Richard Earnshaw  <rearnsha@arm.com>
-            Sofiane Naci  <sofiane.naci@arm.com>
-            Tejas Belagod  <tejas.belagod@arm.com>
-            Yufeng Zhang  <yufeng.zhang@arm.com>
+           Laurent Desnogues  <laurent.desnogues@arm.com>
+           Jim MacArthur  <jim.macarthur@arm.com>
+           Marcus Shawcroft  <marcus.shawcroft@arm.com>
+           Nigel Stephens  <nigel.stephens@arm.com>
+           Ramana Radhakrishnan  <ramana.radhakrishnan@arm.com>
+           Richard Earnshaw  <rearnsha@arm.com>
+           Sofiane Naci  <sofiane.naci@arm.com>
+           Tejas Belagod  <tejas.belagod@arm.com>
+           Yufeng Zhang  <yufeng.zhang@arm.com>
 
        * Makefile.am: Add AArch64.
        * Makefile.in: Regenerate.
@@ -160,8 +165,8 @@
        * po/POTFILES.in: Regenerate.
 
 2012-07-31  Chao-Ying Fu  <fu@mips.com>
-            Catherine Moore  <clm@codesourcery.com>
-            Maciej W. Rozycki  <macro@codesourcery.com>
+           Catherine Moore  <clm@codesourcery.com>
+           Maciej W. Rozycki  <macro@codesourcery.com>
 
        * micromips-opc.c (WR_a, RD_a, MOD_a): New macros.
        (DSP_VOLA): Likewise.
@@ -244,9 +249,9 @@
 2012-07-05  Sean Keys  <skeys@ipdatasys.com>
 
        * xgate-dis.c: Removed an IF statement that will
-        always be false due to overlapping operand masks.
-        * xgate-opc.c: Corrected 'com' opcode entry and
-        fixed spacing.
+       always be false due to overlapping operand masks.
+       * xgate-opc.c: Corrected 'com' opcode entry and
+       fixed spacing.
 
 2012-07-02  Roland McGrath  <mcgrathr@google.com>
 

diff --git a/opcodes/ppc-opc.c b/opcodes/ppc-opc.c
index ce89215053c6d5f1b7945dc134c63a236ace6fee..e2824eff4a820b40e869893caf146d952a45ac69 100644 (file)
--- a/opcodes/ppc-opc.c
+++ b/opcodes/ppc-opc.c
@@ -2858,14 +2858,12 @@ const struct powerpc_opcode powerpc_opcodes[] = {
 {"machhwsu",   XO (4,  76,0,0),XO_MASK,     MULHW|PPCVLE,  PPCNONE,    {RT, RA, RB}},
 {"machhwsu.",  XO (4,  76,0,1),XO_MASK,     MULHW|PPCVLE,  PPCNONE,    {RT, RA, RB}},
 {"ps_cmpo1",   X  (4,  96), X_MASK|(3<<21), PPCPS,     PPCNONE,        {BF, FRA, FRB}},
-{"vabsdub",    VX (4, 192),    VX_MASK,     PPCVEC2,   PPCNONE,        {VD, VA, VB}},
 {"vcmpeqfp",   VXR(4, 198,0),  VXR_MASK,    PPCVEC|PPCVLE, PPCNONE,    {VD, VA, VB}},
 {"vpkuwus",    VX (4, 206),    VX_MASK,     PPCVEC|PPCVLE, PPCNONE,    {VD, VA, VB}},
 {"machhws",    XO (4, 108,0,0),XO_MASK,     MULHW|PPCVLE, PPCNONE,     {RT, RA, RB}},
 {"machhws.",   XO (4, 108,0,1),XO_MASK,     MULHW|PPCVLE, PPCNONE,     {RT, RA, RB}},
 {"nmachhws",   XO (4, 110,0,0),XO_MASK,     MULHW|PPCVLE, PPCNONE,     {RT, RA, RB}},
 {"nmachhws.",  XO (4, 110,0,1),XO_MASK,     MULHW|PPCVLE, PPCNONE,     {RT, RA, RB}},
-{"vabsduh",    VX (4, 256),    VX_MASK,     PPCVEC2,   PPCNONE,        {VD, VA, VB}},
 {"vmaxsb",     VX (4, 258),    VX_MASK,     PPCVEC|PPCVLE, PPCNONE,    {VD, VA, VB}},
 {"vslb",       VX (4, 260),    VX_MASK,     PPCVEC|PPCVLE, PPCNONE,    {VD, VA, VB}},
 {"vmulosb",    VX (4, 264),    VX_MASK,     PPCVEC|PPCVLE, PPCNONE,    {VD, VA, VB}},
@@ -2878,7 +2876,6 @@ const struct powerpc_opcode powerpc_opcodes[] = {
 {"mulchwu.",   XRC(4, 136,1),  X_MASK,      MULHW|PPCVLE, PPCNONE,     {RT, RA, RB}},
 {"macchwu",    XO (4, 140,0,0),XO_MASK,     MULHW|PPCVLE, PPCNONE,     {RT, RA, RB}},
 {"macchwu.",   XO (4, 140,0,1),XO_MASK,     MULHW|PPCVLE, PPCNONE,     {RT, RA, RB}},
-{"vabsduw",    VX (4, 320),    VX_MASK,     PPCVEC2,   PPCNONE,        {VD, VA, VB}},
 {"vmaxsh",     VX (4, 322),    VX_MASK,     PPCVEC|PPCVLE, PPCNONE,    {VD, VA, VB}},
 {"vslh",       VX (4, 324),    VX_MASK,     PPCVEC|PPCVLE, PPCNONE,    {VD, VA, VB}},
 {"vmulosh",    VX (4, 328),    VX_MASK,     PPCVEC|PPCVLE, PPCNONE,    {VD, VA, VB}},
@@ -3142,6 +3139,7 @@ const struct powerpc_opcode powerpc_opcodes[] = {
 {"nmaclhws.",  XO (4, 494,0,1),XO_MASK,     MULHW|PPCVLE, PPCNONE,     {RT, RA, RB}},
 {"vsububm",    VX (4,1024),    VX_MASK,     PPCVEC|PPCVLE, PPCNONE,    {VD, VA, VB}},
 {"vavgub",     VX (4,1026),    VX_MASK,     PPCVEC|PPCVLE, PPCNONE,    {VD, VA, VB}},
+{"vabsdub",    VX (4,1027),    VX_MASK,     PPCVEC2,   PPCNONE,        {VD, VA, VB}},
 {"evmhessf",   VX (4,1027),    VX_MASK,     PPCSPE|PPCVLE, PPCNONE,    {RS, RA, RB}},
 {"vand",       VX (4,1028),    VX_MASK,     PPCVEC|PPCVLE, PPCNONE,    {VD, VA, VB}},
 {"vcmpequb.",  VXR(4,   6,1),  VXR_MASK,    PPCVEC|PPCVLE, PPCNONE,    {VD, VA, VB}},
@@ -3170,6 +3168,7 @@ const struct powerpc_opcode powerpc_opcodes[] = {
 {"evmhosmfa",  VX (4,1071),    VX_MASK,     PPCSPE|PPCVLE, PPCNONE,    {RS, RA, RB}},
 {"vsubuhm",    VX (4,1088),    VX_MASK,     PPCVEC|PPCVLE, PPCNONE,    {VD, VA, VB}},
 {"vavguh",     VX (4,1090),    VX_MASK,     PPCVEC|PPCVLE, PPCNONE,    {VD, VA, VB}},
+{"vabsduh",    VX (4,1091),    VX_MASK,     PPCVEC2,   PPCNONE,        {VD, VA, VB}},
 {"vandc",      VX (4,1092),    VX_MASK,     PPCVEC|PPCVLE, PPCNONE,    {VD, VA, VB}},
 {"vcmpequh.",  VXR(4,  70,1),  VXR_MASK,    PPCVEC|PPCVLE, PPCNONE,    {VD, VA, VB}},
 {"udi1fcm.",   APU(4, 547,0), APU_MASK, PPC405|PPC440, PPC476,         {URT, URA, URB}},
@@ -3202,6 +3201,7 @@ const struct powerpc_opcode powerpc_opcodes[] = {
 {"evmwsmfa",   VX (4,1147),    VX_MASK,     PPCSPE|PPCVLE, PPCNONE,    {RS, RA, RB}},
 {"vsubuwm",    VX (4,1152),    VX_MASK,     PPCVEC|PPCVLE, PPCNONE,    {VD, VA, VB}},
 {"vavguw",     VX (4,1154),    VX_MASK,     PPCVEC|PPCVLE, PPCNONE,    {VD, VA, VB}},
+{"vabsduw",    VX (4,1155),    VX_MASK,     PPCVEC2,   PPCNONE,        {VD, VA, VB}},
 {"vor",                VX (4,1156),    VX_MASK,     PPCVEC|PPCVLE, PPCNONE,    {VD, VA, VB}},
 {"vcmpequw.",  VXR(4, 134,1),  VXR_MASK,    PPCVEC|PPCVLE, PPCNONE,    {VD, VA, VB}},
 {"udi2fcm.",   APU(4, 579,0), APU_MASK, PPC405|PPC440, PPC476,         {URT, URA, URB}},
@@ -4286,6 +4286,8 @@ const struct powerpc_opcode powerpc_opcodes[] = {
 {"lvehx",      X(31,39),       X_MASK,      PPCVEC|PPCVLE, PPCNONE,    {VD, RA0, RB}},
 {"lhfcmx",     APU(31,39,0),   APU_MASK,    PPC405,    PPCNONE,        {FCRT, RA, RB}},
 
+{"mviwsplt",   X(31,46),       X_MASK,      PPCVEC2,   PPCNONE,        {VD, RA, RB}},
+
 {"iselgt",     X(31,47),       X_MASK,      PPCISEL,   PPCNONE,        {RT, RA0, RB}},
 
 {"lvewx",      X(31,71),       X_MASK,      PPCVEC|PPCVLE, PPCNONE,    {VD, RA0, RB}},
@@ -4410,8 +4412,6 @@ const struct powerpc_opcode powerpc_opcodes[] = {
 {"adde.",      XO(31,138,0,1), XO_MASK,     PPCCOM|PPCVLE, PPCNONE,    {RT, RA, RB}},
 {"ae.",                XO(31,138,0,1), XO_MASK,     PWRCOM,    PPCNONE,        {RT, RA, RB}},
 
-{"mviwsplt",   X(31,142),      X_MASK,      PPCVEC2,   PPCNONE,        {VD, RA, RB}},
-
 {"dcbtstlse",  X(31,142),      X_MASK,      PPCCHLK,   E500MC,         {CT, RA0, RB}},
 
 {"mtcr",       XFXM(31,144,0xff,0), XRARB_MASK, COM,   PPCNONE,        {RS}},