MIPS/BFD: Correct register index calculation in BZ16_REG

For the 3-bit register encodings of { 0, 1, 2, 3, 4, 5, 6, 7 } return
the 5-bit encodings of { 16, 17, 2, 3, 4, 5, 6, 7 } respectively rather
than { 24, 25, 2, 3, 4, 5, 6, 7 }.

	bfd/
	* elfxx-mips.c (BZ16_REG): Correct calculation.

diff --git a/bfd/ChangeLog b/bfd/ChangeLog
index 9c813bacc4941e4e66bc1f775ff74732e2cfc094..2e4f3b3c8cfb6666d5caae177a4cf704ce11db32 100644 (file)
--- a/bfd/ChangeLog
+++ b/bfd/ChangeLog
@@ -1,3 +1,7 @@
+2016-01-24  Maciej W. Rozycki  <macro@imgtec.com>
+
+       * elfxx-mips.c (BZ16_REG): Correct calculation.
+
 2016-01-21  Nick Clifton  <nickc@redhat.com>
 
        * elf32-arc.c (ADD_RELA): Fix compile time warning errors by

diff --git a/bfd/elfxx-mips.c b/bfd/elfxx-mips.c
index 4ece8197986d37aa8cea4c703dfcfa2f078aaadc..176970a82c3f8398aa1a6d3839753a0fad494120 100644 (file)
--- a/bfd/elfxx-mips.c
+++ b/bfd/elfxx-mips.c
@@ -13110,7 +13110,7 @@ static const struct opcode_descriptor bz_insns_16[] = {
 
 /* Switch between a 5-bit register index and its 3-bit shorthand.  */
 
-#define BZ16_REG(opcode) ((((((opcode) >> 7) & 7) + 0x1e) & 0x17) + 2)
+#define BZ16_REG(opcode) ((((((opcode) >> 7) & 7) + 0x1e) & 0xf) + 2)
 #define BZ16_REG_FIELD(r) \
   (((2 <= (r) && (r) <= 7) ? (r) : ((r) - 16)) << 7)