re PR target/84534 (several powerpc test cases fail starting with r257915)
authorPeter Bergner <bergner@vnet.ibm.com>
Fri, 2 Mar 2018 02:54:40 +0000 (20:54 -0600)
committerPeter Bergner <bergner@gcc.gnu.org>
Fri, 2 Mar 2018 02:54:40 +0000 (20:54 -0600)
PR target/84534
* gcc.target/powerpc/vec-setup-be-long.c: Add dg-xfail-run-if on
powerpc64le*-*-linux*.
* gcc.target/powerpc/vsx-vector-6-le.c: Do not count xxlor's.
* gcc.target/powerpc/vsx-vector-6-le.p9.c: Likewise.

From-SVN: r258122

gcc/testsuite/ChangeLog
gcc/testsuite/gcc.target/powerpc/vec-setup-be-long.c
gcc/testsuite/gcc.target/powerpc/vsx-vector-6-le.c
gcc/testsuite/gcc.target/powerpc/vsx-vector-6-le.p9.c

index 62fde2d5bbd2d3d8bbc2717e7fcde6ae107d6f4b..ae399f45a70aa227f7f4370d01a7b8601274d81d 100644 (file)
@@ -1,3 +1,11 @@
+2018-03-01  Peter Bergner  <bergner@vnet.ibm.com>
+
+       PR target/84534
+       * gcc.target/powerpc/vec-setup-be-long.c: Add dg-xfail-run-if on
+       powerpc64le*-*-linux*.
+       * gcc.target/powerpc/vsx-vector-6-le.c: Do not count xxlor's.
+       * gcc.target/powerpc/vsx-vector-6-le.p9.c: Likewise.
+
 2018-03-01  Martin Sebor  <msebor@redhat.com>
 
        PR c++/84294
index 691b378698fb4086ffedc827df4ee67067b51cc8..75d864eee518818c5ddd96266c9e496624d6b7e8 100644 (file)
@@ -1,4 +1,7 @@
+/* Per PR78303, we are deprecating usage of -maltivec=be on little endian,
+   so XFAIL this test until support is actually removed.  */
 /* { dg-do run { target { powerpc64le*-*-linux* } } } */
+/* { dg-xfail-run-if "PR78303 and PR84534" { powerpc64le*-*-linux* } } */
 /* { dg-require-effective-target vsx_hw } */
 /* Disable warnings to squelch deprecation message about -maltivec=be.  */
 /* { dg-options "-w -O2 -mvsx -maltivec=be" } */
index c3f795cbc153d2030a4fb8601a27bef1f5b875d2..fe7eeb12ff96ecabd1abbbe906c436400a2667b2 100644 (file)
@@ -9,7 +9,11 @@
 /* { dg-final { scan-assembler-times "xvabsdp" 1 } } */
 /* { dg-final { scan-assembler-times "xvadddp" 1 } } */
 /* { dg-final { scan-assembler-times "xxlnor" 8 } } */
-/* { dg-final { scan-assembler-times "xxlor" 30 } } */
+/* We generate xxlor instructions for many reasons other than or'ing vector
+   operands or calling __builtin_vec_or(), which  means we cannot rely on
+   their usage counts being stable.  Therefore, we just ensure at least one
+   xxlor instruction was generated.  */
+/* { dg-final { scan-assembler "xxlor" } } */
 /* { dg-final { scan-assembler-times "xvcmpeqdp" 5 } } */
 /* { dg-final { scan-assembler-times "xvcmpgtdp" 8 } } */
 /* { dg-final { scan-assembler-times "xvcmpgedp" 6 } } */
index 290d4b4813593c57f65ba1df33fccaf4c8840907..c2427b8cdb60362598ee6608e99d3d338fd01b1e 100644 (file)
@@ -9,7 +9,11 @@
 /* { dg-final { scan-assembler-times "xvabsdp" 1 } } */
 /* { dg-final { scan-assembler-times "xvadddp" 1 } } */
 /* { dg-final { scan-assembler-times "xxlnor" 7 } } */
-/* { dg-final { scan-assembler-times "xxlor" 20 } } */
+/* We generate xxlor instructions for many reasons other than or'ing vector
+   operands or calling __builtin_vec_or(), which  means we cannot rely on
+   their usage counts being stable.  Therefore, we just ensure at least one
+   xxlor instruction was generated.  */
+/* { dg-final { scan-assembler "xxlor" } } */
 /* { dg-final { scan-assembler-times "xvcmpeqdp" 5 } } */
 /* { dg-final { scan-assembler-times "xvcmpgtdp" 8 } } */
 /* { dg-final { scan-assembler-times "xvcmpgedp" 8 } } */