r600g: remove dummy function r600_bo_offset

Always returned 0.

diff --git a/src/gallium/drivers/r600/evergreen_state.c b/src/gallium/drivers/r600/evergreen_state.c
index bc6039dd40c72d99d61b5a90eaf928f994bc3c5b..c9eaf94a2ae92e26e01adbc38e9ba0d490df4645 100644 (file)
--- a/src/gallium/drivers/r600/evergreen_state.c
+++ b/src/gallium/drivers/r600/evergreen_state.c
@@ -1023,8 +1023,8 @@ static struct pipe_sampler_view *evergreen_create_sampler_view(struct pipe_conte
        rstate->val[1] = (S_030004_TEX_HEIGHT(texture->height0 - 1) |
                          S_030004_TEX_DEPTH(texture->depth0 - 1) |
                          S_030004_ARRAY_MODE(array_mode));
-       rstate->val[2] = (tmp->offset[0] + r600_bo_offset(bo[0])) >> 8;
-       rstate->val[3] = (tmp->offset[1] + r600_bo_offset(bo[1])) >> 8;
+       rstate->val[2] = tmp->offset[0] >> 8;
+       rstate->val[3] = tmp->offset[1] >> 8;
        rstate->val[4] = (word4 |
                          S_030010_SRF_MODE_ALL(V_030010_SRF_MODE_ZERO_CLAMP_MINUS_ONE) |
                          S_030010_ENDIAN_SWAP(endian) |
@@ -1354,7 +1354,7 @@ static void evergreen_cb(struct r600_pipe_context *rctx, struct r600_pipe_state
        /* FIXME handle enabling of CB beyond BASE8 which has different offset */
        r600_pipe_state_add_reg(rstate,
                                R_028C60_CB_COLOR0_BASE + cb * 0x3C,
-                               (offset +  r600_bo_offset(bo[0])) >> 8, 0xFFFFFFFF, bo[0]);
+                               offset >> 8, 0xFFFFFFFF, bo[0]);
        r600_pipe_state_add_reg(rstate,
                                R_028C78_CB_COLOR0_DIM + cb * 0x3C,
                                0x0, 0xFFFFFFFF, NULL);
@@ -1407,18 +1407,18 @@ static void evergreen_db(struct r600_pipe_context *rctx, struct r600_pipe_state
        stencil_format = r600_translate_stencilformat(state->zsbuf->texture->format);
 
        r600_pipe_state_add_reg(rstate, R_028048_DB_Z_READ_BASE,
-                               (offset + r600_bo_offset(rbuffer->bo)) >> 8, 0xFFFFFFFF, rbuffer->bo);
+                               offset >> 8, 0xFFFFFFFF, rbuffer->bo);
        r600_pipe_state_add_reg(rstate, R_028050_DB_Z_WRITE_BASE,
-                               (offset  + r600_bo_offset(rbuffer->bo)) >> 8, 0xFFFFFFFF, rbuffer->bo);
+                               offset >> 8, 0xFFFFFFFF, rbuffer->bo);
 
        if (stencil_format) {
                uint32_t stencil_offset;
 
                stencil_offset = ((surf->aligned_height * rtex->pitch_in_bytes[level]) + 255) & ~255;
                r600_pipe_state_add_reg(rstate, R_02804C_DB_STENCIL_READ_BASE,
-                                       (offset + stencil_offset + r600_bo_offset(rbuffer->bo)) >> 8, 0xFFFFFFFF, rbuffer->bo);
+                                       (offset + stencil_offset) >> 8, 0xFFFFFFFF, rbuffer->bo);
                r600_pipe_state_add_reg(rstate, R_028054_DB_STENCIL_WRITE_BASE,
-                                       (offset + stencil_offset + r600_bo_offset(rbuffer->bo)) >> 8, 0xFFFFFFFF, rbuffer->bo);
+                                       (offset + stencil_offset) >> 8, 0xFFFFFFFF, rbuffer->bo);
        }
 
        r600_pipe_state_add_reg(rstate, R_028008_DB_DEPTH_VIEW, 0x00000000, 0xFFFFFFFF, NULL);
@@ -2265,7 +2265,7 @@ void evergreen_pipe_shader_ps(struct pipe_context *ctx, struct r600_pipe_shader
 
        r600_pipe_state_add_reg(rstate,
                                R_028840_SQ_PGM_START_PS,
-                               (r600_bo_offset(shader->bo)) >> 8, 0xFFFFFFFF, shader->bo);
+                               0, 0xFFFFFFFF, shader->bo);
        r600_pipe_state_add_reg(rstate,
                                R_028844_SQ_PGM_RESOURCES_PS,
                                S_028844_NUM_GPRS(rshader->bc.ngpr) |
@@ -2339,7 +2339,7 @@ void evergreen_pipe_shader_vs(struct pipe_context *ctx, struct r600_pipe_shader
                                0x0, 0xFFFFFFFF, NULL);
        r600_pipe_state_add_reg(rstate,
                        R_02885C_SQ_PGM_START_VS,
-                       (r600_bo_offset(shader->bo)) >> 8, 0xFFFFFFFF, shader->bo);
+                       0, 0xFFFFFFFF, shader->bo);
 
        r600_pipe_state_add_reg(rstate,
                                R_03A200_SQ_LOOP_CONST_0 + (32 * 4), 0x01000FFF,
@@ -2356,7 +2356,7 @@ void evergreen_fetch_shader(struct pipe_context *ctx,
        r600_pipe_state_add_reg(rstate, R_0288A8_SQ_PGM_RESOURCES_FS,
                                0x00000000, 0xFFFFFFFF, NULL);
        r600_pipe_state_add_reg(rstate, R_0288A4_SQ_PGM_START_FS,
-                               (r600_bo_offset(ve->fetch_shader)) >> 8,
+                               0,
                                0xFFFFFFFF, ve->fetch_shader);
 }
 

diff --git a/src/gallium/drivers/r600/r600.h b/src/gallium/drivers/r600/r600.h
index d2b03418ede40df0d67a8a5d517b46e3dbfd080b..2e759c794090b7817e160bb5ee7ab9c0ecba09bf 100644 (file)
--- a/src/gallium/drivers/r600/r600.h
+++ b/src/gallium/drivers/r600/r600.h
@@ -105,11 +105,8 @@ struct r600_bo *r600_bo_handle(struct radeon *radeon,
 void *r600_bo_map(struct radeon *radeon, struct r600_bo *bo, unsigned usage, void *ctx);
 void r600_bo_unmap(struct radeon *radeon, struct r600_bo *bo);
 boolean r600_bo_get_winsys_handle(struct radeon *radeon, struct r600_bo *pb_bo,
-                               unsigned stride, struct winsys_handle *whandle);
-static INLINE unsigned r600_bo_offset(struct r600_bo *bo)
-{
-       return 0;
-}
+                                 unsigned stride, struct winsys_handle *whandle);
+
 void r600_bo_destroy(struct radeon *radeon, struct r600_bo *bo);
 
 /* this relies on the pipe_reference being the first member of r600_bo */

diff --git a/src/gallium/drivers/r600/r600_state.c b/src/gallium/drivers/r600/r600_state.c
index 1350a1cf565855910c011ab3f6718d24984c39ba..487b1df0052c42932bc181d2123dcccbdfbb6e02 100644 (file)
--- a/src/gallium/drivers/r600/r600_state.c
+++ b/src/gallium/drivers/r600/r600_state.c
@@ -1077,8 +1077,8 @@ static struct pipe_sampler_view *r600_create_sampler_view(struct pipe_context *c
        rstate->val[1] = (S_038004_TEX_HEIGHT(height - 1) |
                          S_038004_TEX_DEPTH(depth - 1) |
                          S_038004_DATA_FORMAT(format));
-       rstate->val[2] = (tmp->offset[offset_level] + r600_bo_offset(bo[0])) >> 8;
-       rstate->val[3] = (tmp->offset[offset_level+1] + r600_bo_offset(bo[1])) >> 8;
+       rstate->val[2] = tmp->offset[offset_level] >> 8;
+       rstate->val[3] = tmp->offset[offset_level+1] >> 8;
        rstate->val[4] = (word4 |
                          S_038010_SRF_MODE_ALL(V_038010_SRF_MODE_ZERO_CLAMP_MINUS_ONE) |
                          S_038010_REQUEST_SIZE(1) |
@@ -1441,7 +1441,7 @@ static void r600_cb(struct r600_pipe_context *rctx, struct r600_pipe_state *rsta
 
        r600_pipe_state_add_reg(rstate,
                                R_028040_CB_COLOR0_BASE + cb * 4,
-                               (offset + r600_bo_offset(bo[0])) >> 8, 0xFFFFFFFF, bo[0]);
+                               offset >> 8, 0xFFFFFFFF, bo[0]);
        r600_pipe_state_add_reg(rstate,
                                R_0280A0_CB_COLOR0_INFO + cb * 4,
                                color_info, 0xFFFFFFFF, bo[0]);
@@ -1455,10 +1455,10 @@ static void r600_cb(struct r600_pipe_context *rctx, struct r600_pipe_state *rsta
                                0x00000000, 0xFFFFFFFF, NULL);
        r600_pipe_state_add_reg(rstate,
                                R_0280E0_CB_COLOR0_FRAG + cb * 4,
-                               r600_bo_offset(bo[1]) >> 8, 0xFFFFFFFF, bo[1]);
+                               0, 0xFFFFFFFF, bo[1]);
        r600_pipe_state_add_reg(rstate,
                                R_0280C0_CB_COLOR0_TILE + cb * 4,
-                               r600_bo_offset(bo[2]) >> 8, 0xFFFFFFFF, bo[2]);
+                               0, 0xFFFFFFFF, bo[2]);
        r600_pipe_state_add_reg(rstate,
                                R_028100_CB_COLOR0_MASK + cb * 4,
                                0x00000000, 0xFFFFFFFF, NULL);
@@ -1492,7 +1492,7 @@ static void r600_db(struct r600_pipe_context *rctx, struct r600_pipe_state *rsta
        format = r600_translate_dbformat(state->zsbuf->texture->format);
 
        r600_pipe_state_add_reg(rstate, R_02800C_DB_DEPTH_BASE,
-                               (offset + r600_bo_offset(rbuffer->bo)) >> 8, 0xFFFFFFFF, rbuffer->bo);
+                               offset >> 8, 0xFFFFFFFF, rbuffer->bo);
        r600_pipe_state_add_reg(rstate, R_028000_DB_DEPTH_SIZE,
                                S_028000_PITCH_TILE_MAX(pitch) | S_028000_SLICE_TILE_MAX(slice),
                                0xFFFFFFFF, NULL);
@@ -2027,7 +2027,7 @@ void r600_pipe_shader_ps(struct pipe_context *ctx, struct r600_pipe_shader *shad
        r600_pipe_state_add_reg(rstate, R_0286D8_SPI_INPUT_Z, spi_input_z, 0xFFFFFFFF, NULL);
        r600_pipe_state_add_reg(rstate,
                                R_028840_SQ_PGM_START_PS,
-                               r600_bo_offset(shader->bo) >> 8, 0xFFFFFFFF, shader->bo);
+                               0, 0xFFFFFFFF, shader->bo);
        r600_pipe_state_add_reg(rstate,
                                R_028850_SQ_PGM_RESOURCES_PS,
                                S_028868_NUM_GPRS(rshader->bc.ngpr) |
@@ -2106,7 +2106,7 @@ void r600_pipe_shader_vs(struct pipe_context *ctx, struct r600_pipe_shader *shad
                        0x00000000, 0xFFFFFFFF, NULL);
        r600_pipe_state_add_reg(rstate,
                        R_028858_SQ_PGM_START_VS,
-                       r600_bo_offset(shader->bo) >> 8, 0xFFFFFFFF, shader->bo);
+                       0, 0xFFFFFFFF, shader->bo);
 
        r600_pipe_state_add_reg(rstate,
                                R_03E200_SQ_LOOP_CONST_0 + (32 * 4), 0x01000FFF,
@@ -2127,7 +2127,7 @@ void r600_fetch_shader(struct pipe_context *ctx,
        r600_pipe_state_add_reg(rstate, R_0288DC_SQ_PGM_CF_OFFSET_FS,
                                0x00000000, 0xFFFFFFFF, NULL);
        r600_pipe_state_add_reg(rstate, R_028894_SQ_PGM_START_FS,
-                               r600_bo_offset(ve->fetch_shader) >> 8,
+                               0,
                                0xFFFFFFFF, ve->fetch_shader);
 }
 

diff --git a/src/gallium/drivers/r600/r600_state_common.c b/src/gallium/drivers/r600/r600_state_common.c
index 408eaed491b2c79dcb1177a00f67c0c4d1909c8e..9f3ab89fdf7a89000594ac589a57b1ee7f4d4cf4 100644 (file)
--- a/src/gallium/drivers/r600/r600_state_common.c
+++ b/src/gallium/drivers/r600/r600_state_common.c
@@ -418,7 +418,6 @@ void r600_set_constant_buffer(struct pipe_context *ctx, uint shader, uint index,
        }
 
        r600_upload_const_buffer(rctx, &rbuffer, &offset);
-       offset += r600_bo_offset(rbuffer->r.bo);
 
        switch (shader) {
        case PIPE_SHADER_VERTEX:
@@ -518,7 +517,7 @@ static void r600_vertex_buffer_update(struct r600_pipe_context *rctx)
                }
                if (vertex_buffer == NULL || rbuffer == NULL)
                        continue;
-               offset += vertex_buffer->buffer_offset + r600_bo_offset(rbuffer->bo);
+               offset += vertex_buffer->buffer_offset;
 
                if (!rstate->id) {
                        if (rctx->chip_class >= EVERGREEN) {

diff --git a/src/gallium/winsys/r600/drm/evergreen_hw_context.c b/src/gallium/winsys/r600/drm/evergreen_hw_context.c
index 5729fdd632621861d37a381fee5189a311a899b7..98283ffbefcbf3f83a4510de369cfacee7ab309b 100644 (file)
--- a/src/gallium/winsys/r600/drm/evergreen_hw_context.c
+++ b/src/gallium/winsys/r600/drm/evergreen_hw_context.c
@@ -1202,7 +1202,7 @@ void evergreen_context_draw(struct r600_context *ctx, const struct r600_draw *dr
        pm4[3] = draw->vgt_num_instances;
        if (draw->indices) {
                pm4[4] = PKT3(PKT3_DRAW_INDEX, 3, ctx->predicate_drawing);
-               pm4[5] = draw->indices_bo_offset + r600_bo_offset(draw->indices);
+               pm4[5] = draw->indices_bo_offset;
                pm4[6] = 0;
                pm4[7] = draw->vgt_num_indices;
                pm4[8] = draw->vgt_draw_initiator;

diff --git a/src/gallium/winsys/r600/drm/r600_hw_context.c b/src/gallium/winsys/r600/drm/r600_hw_context.c
index f1150712b238477b7c102e464b2b529a7962a59f..35c086ae680764e2a97044bd593a6c40d5d39f77 100644 (file)
--- a/src/gallium/winsys/r600/drm/r600_hw_context.c
+++ b/src/gallium/winsys/r600/drm/r600_hw_context.c
@@ -1468,7 +1468,7 @@ void r600_context_draw(struct r600_context *ctx, const struct r600_draw *draw)
        pm4[3] = draw->vgt_num_instances;
        if (draw->indices) {
                pm4[4] = PKT3(PKT3_DRAW_INDEX, 3, ctx->predicate_drawing);
-               pm4[5] = draw->indices_bo_offset + r600_bo_offset(draw->indices);
+               pm4[5] = draw->indices_bo_offset;
                pm4[6] = 0;
                pm4[7] = draw->vgt_num_indices;
                pm4[8] = draw->vgt_draw_initiator;
@@ -1710,14 +1710,14 @@ void r600_query_begin(struct r600_context *ctx, struct r600_query *query)
        if (query->type == PIPE_QUERY_TIME_ELAPSED) {
                ctx->pm4[ctx->pm4_cdwords++] = PKT3(PKT3_EVENT_WRITE_EOP, 4, 0);
                ctx->pm4[ctx->pm4_cdwords++] = EVENT_TYPE(EVENT_TYPE_CACHE_FLUSH_AND_INV_TS_EVENT) | EVENT_INDEX(5);
-               ctx->pm4[ctx->pm4_cdwords++] = query->results_end + r600_bo_offset(query->buffer);
+               ctx->pm4[ctx->pm4_cdwords++] = query->results_end;
                ctx->pm4[ctx->pm4_cdwords++] = (3 << 29);
                ctx->pm4[ctx->pm4_cdwords++] = 0;
                ctx->pm4[ctx->pm4_cdwords++] = 0;
        } else {
                ctx->pm4[ctx->pm4_cdwords++] = PKT3(PKT3_EVENT_WRITE, 2, 0);
                ctx->pm4[ctx->pm4_cdwords++] = EVENT_TYPE(EVENT_TYPE_ZPASS_DONE) | EVENT_INDEX(1);
-               ctx->pm4[ctx->pm4_cdwords++] = query->results_end + r600_bo_offset(query->buffer);
+               ctx->pm4[ctx->pm4_cdwords++] = query->results_end;
                ctx->pm4[ctx->pm4_cdwords++] = 0;
        }
        ctx->pm4[ctx->pm4_cdwords++] = PKT3(PKT3_NOP, 0, 0);
@@ -1735,14 +1735,14 @@ void r600_query_end(struct r600_context *ctx, struct r600_query *query)
        if (query->type == PIPE_QUERY_TIME_ELAPSED) {
                ctx->pm4[ctx->pm4_cdwords++] = PKT3(PKT3_EVENT_WRITE_EOP, 4, 0);
                ctx->pm4[ctx->pm4_cdwords++] = EVENT_TYPE(EVENT_TYPE_CACHE_FLUSH_AND_INV_TS_EVENT) | EVENT_INDEX(5);
-               ctx->pm4[ctx->pm4_cdwords++] = query->results_end + 8 + r600_bo_offset(query->buffer);
+               ctx->pm4[ctx->pm4_cdwords++] = query->results_end + 8;
                ctx->pm4[ctx->pm4_cdwords++] = (3 << 29);
                ctx->pm4[ctx->pm4_cdwords++] = 0;
                ctx->pm4[ctx->pm4_cdwords++] = 0;
        } else {
                ctx->pm4[ctx->pm4_cdwords++] = PKT3(PKT3_EVENT_WRITE, 2, 0);
                ctx->pm4[ctx->pm4_cdwords++] = EVENT_TYPE(EVENT_TYPE_ZPASS_DONE) | EVENT_INDEX(1);
-               ctx->pm4[ctx->pm4_cdwords++] = query->results_end + 8 + r600_bo_offset(query->buffer);
+               ctx->pm4[ctx->pm4_cdwords++] = query->results_end + 8;
                ctx->pm4[ctx->pm4_cdwords++] = 0;
        }
        ctx->pm4[ctx->pm4_cdwords++] = PKT3(PKT3_NOP, 0, 0);
@@ -1789,7 +1789,7 @@ void r600_query_predication(struct r600_context *ctx, struct r600_query *query,
                /* emit predicate packets for all data blocks */
                while (results_base != query->results_end) {
                        ctx->pm4[ctx->pm4_cdwords++] = PKT3(PKT3_SET_PREDICATION, 1, 0);
-                       ctx->pm4[ctx->pm4_cdwords++] = results_base + r600_bo_offset(query->buffer);
+                       ctx->pm4[ctx->pm4_cdwords++] = results_base;
                        ctx->pm4[ctx->pm4_cdwords++] = op;
                        ctx->pm4[ctx->pm4_cdwords++] = PKT3(PKT3_NOP, 0, 0);
                        ctx->pm4[ctx->pm4_cdwords++] = 0;