hierarchy - proc reorder

diff --git a/tests/xilinx/.gitignore b/tests/xilinx/.gitignore
index 89879f209ac5c4d087995a91be8956501fa19be3..c99b79371ae7694a071eebe77063952c3810b2a4 100644 (file)
--- a/tests/xilinx/.gitignore
+++ b/tests/xilinx/.gitignore
@@ -2,4 +2,4 @@
 /*.out
 /run-test.mk
 /*_uut.v
-/test_macc
\ No newline at end of file
+/test_macc

diff --git a/tests/xilinx/add_sub.ys b/tests/xilinx/add_sub.ys
index 821341f2065f7c02c2217c594c2ca17128e35148..f06e7fa01180d3885649d9e03a3b88c7145345b2 100644 (file)
--- a/tests/xilinx/add_sub.ys
+++ b/tests/xilinx/add_sub.ys
@@ -1,5 +1,6 @@
 read_verilog add_sub.v
 hierarchy -top top
+proc
 equiv_opt -assert -map +/xilinx/cells_sim.v synth_xilinx # equivalency check
 design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
 cd top # Constrain all select calls below inside the top module

diff --git a/tests/xilinx/adffs.ys b/tests/xilinx/adffs.ys
index 9e8ba44ab78c89fe836c593022617693139e9761..1923b9802908f963d5ad35d707fa9ab38e5babe5 100644 (file)
--- a/tests/xilinx/adffs.ys
+++ b/tests/xilinx/adffs.ys
@@ -1,8 +1,8 @@
 read_verilog adffs.v
 design -save read
 
-proc
 hierarchy -top adff
+proc
 equiv_opt -async2sync  -assert -map +/xilinx/cells_sim.v synth_xilinx # equivalency check
 design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
 cd adff # Constrain all select calls below inside the top module
@@ -13,8 +13,8 @@ select -assert-none t:BUFG t:FDCE %% t:* %D
 
 
 design -load read
-proc
 hierarchy -top adffn
+proc
 equiv_opt -async2sync  -assert -map +/xilinx/cells_sim.v synth_xilinx # equivalency check
 design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
 cd adffn # Constrain all select calls below inside the top module
@@ -26,8 +26,8 @@ select -assert-none t:BUFG t:FDCE t:LUT1 %% t:* %D
 
 
 design -load read
-proc
 hierarchy -top dffs
+proc
 equiv_opt -async2sync  -assert -map +/xilinx/cells_sim.v synth_xilinx # equivalency check
 design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
 cd dffs # Constrain all select calls below inside the top module
@@ -39,8 +39,8 @@ select -assert-none t:BUFG t:FDRE t:LUT2 %% t:* %D
 
 
 design -load read
-proc
 hierarchy -top ndffnr
+proc
 equiv_opt -async2sync  -assert -map +/xilinx/cells_sim.v synth_xilinx # equivalency check
 design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
 cd ndffnr # Constrain all select calls below inside the top module

diff --git a/tests/xilinx/dffs.ys b/tests/xilinx/dffs.ys
index 2d48a816c0ffcbfd52c9888c756889f178b3e4aa..f1716dabb9303dcb55b8ce65805262538c54ad2a 100644 (file)
--- a/tests/xilinx/dffs.ys
+++ b/tests/xilinx/dffs.ys
@@ -1,8 +1,8 @@
 read_verilog dffs.v
 design -save read
 
-proc
 hierarchy -top dff
+proc
 equiv_opt -assert -map +/xilinx/cells_sim.v synth_xilinx # equivalency check
 design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
 cd dff # Constrain all select calls below inside the top module
@@ -13,8 +13,8 @@ select -assert-none t:BUFG t:FDRE %% t:* %D
 
 
 design -load read
-proc
 hierarchy -top dffe
+proc
 equiv_opt -assert -map +/xilinx/cells_sim.v synth_xilinx # equivalency check
 design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
 cd dffe # Constrain all select calls below inside the top module

diff --git a/tests/xilinx/latches.ys b/tests/xilinx/latches.ys
index 52e96834dc66ec60fef4474dcf51b214de37bfa4..3eb550a423ac4bced3b0d0869839739128163142 100644 (file)
--- a/tests/xilinx/latches.ys
+++ b/tests/xilinx/latches.ys
@@ -1,8 +1,8 @@
 read_verilog latches.v
 design -save read
 
-proc
 hierarchy -top latchp
+proc
 equiv_opt -async2sync -assert -map +/xilinx/cells_sim.v synth_xilinx # equivalency check
 design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
 cd latchp # Constrain all select calls below inside the top module
@@ -12,8 +12,8 @@ select -assert-none t:LDCE %% t:* %D
 
 
 design -load read
-proc
 hierarchy -top latchn
+proc
 equiv_opt -async2sync -assert -map +/xilinx/cells_sim.v synth_xilinx # equivalency check
 design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
 cd latchn # Constrain all select calls below inside the top module
@@ -24,8 +24,8 @@ select -assert-none t:LDCE t:LUT1 %% t:* %D
 
 
 design -load read
-proc
 hierarchy -top latchsr
+proc
 equiv_opt -async2sync -assert -map +/xilinx/cells_sim.v synth_xilinx # equivalency check
 design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
 cd latchsr # Constrain all select calls below inside the top module

diff --git a/tests/xilinx/logic.ys b/tests/xilinx/logic.ys
index e138ae6a315a51d140bf8ced22d76cdc574b2fba..9ae5993aa44a91eb91761ac56eccd54932841726 100644 (file)
--- a/tests/xilinx/logic.ys
+++ b/tests/xilinx/logic.ys
@@ -1,5 +1,6 @@
 read_verilog logic.v
 hierarchy -top top
+proc
 equiv_opt -assert -map +/xilinx/cells_sim.v synth_xilinx # equivalency check
 design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
 cd top # Constrain all select calls below inside the top module

diff --git a/tests/xilinx/macc.ys b/tests/xilinx/macc.ys
index 417a3b21b7fe7a87dea21e8538b3d8f1a140cb14..6e884b35a1d41c6049078d365ce1194312f77cb3 100644 (file)
--- a/tests/xilinx/macc.ys
+++ b/tests/xilinx/macc.ys
@@ -1,8 +1,8 @@
 read_verilog macc.v
 design -save read
 
-proc
 hierarchy -top macc
+proc
 #equiv_opt -assert -map +/xilinx/cells_sim.v synth_xilinx ### TODO
 equiv_opt -run :prove -map +/xilinx/cells_sim.v synth_xilinx
 miter -equiv -flatten -make_assert -make_outputs gold gate miter
@@ -15,8 +15,8 @@ select -assert-count 1 t:DSP48E1
 select -assert-none t:BUFG t:FDRE t:DSP48E1 %% t:* %D
 
 design -load read
-proc
 hierarchy -top macc2
+proc
 #equiv_opt -assert -map +/xilinx/cells_sim.v synth_xilinx ### TODO
 equiv_opt -run :prove -map +/xilinx/cells_sim.v synth_xilinx
 miter -equiv -flatten -make_assert -make_outputs gold gate miter

diff --git a/tests/xilinx/mul.ys b/tests/xilinx/mul.ys
index f5306e848efa8d563258f13919325f6288ed3c6d..66a06efdc9bcd78add69b8213c2e38f71cb0711c 100644 (file)
--- a/tests/xilinx/mul.ys
+++ b/tests/xilinx/mul.ys
@@ -1,5 +1,6 @@
 read_verilog mul.v
 hierarchy -top top
+proc
 equiv_opt -assert -map +/xilinx/cells_sim.v synth_xilinx # equivalency check
 design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
 cd top # Constrain all select calls below inside the top module

diff --git a/tests/xilinx/mul_unsigned.ys b/tests/xilinx/mul_unsigned.ys
index 77990bd686245f8a3a51e861dc1ead3f2f7876d9..62495b90cf423839a4adf375bf4252e6fcd29fb9 100644 (file)
--- a/tests/xilinx/mul_unsigned.ys
+++ b/tests/xilinx/mul_unsigned.ys
@@ -1,6 +1,7 @@
 read_verilog mul_unsigned.v
-proc
 hierarchy -top mul_unsigned
+proc
+
 equiv_opt -assert -map +/xilinx/cells_sim.v synth_xilinx # equivalency check
 design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
 cd mul_unsigned # Constrain all select calls below inside the top module

diff --git a/tests/xilinx/mux.ys b/tests/xilinx/mux.ys
index 4cdb12e47f4dd6e260d21d08ec71ed288cae634c..420dece4e072167b57b40271beb8443c0ee39392 100644 (file)
--- a/tests/xilinx/mux.ys
+++ b/tests/xilinx/mux.ys
@@ -1,8 +1,8 @@
 read_verilog mux.v
 design -save read
 
-proc
 hierarchy -top mux2
+proc
 equiv_opt -assert -map +/xilinx/cells_sim.v synth_xilinx # equivalency check
 design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
 cd mux2 # Constrain all select calls below inside the top module
@@ -12,8 +12,8 @@ select -assert-none t:LUT3 %% t:* %D
 
 
 design -load read
-proc
 hierarchy -top mux4
+proc
 equiv_opt -assert -map +/xilinx/cells_sim.v synth_xilinx # equivalency check
 design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
 cd mux4 # Constrain all select calls below inside the top module
@@ -23,8 +23,8 @@ select -assert-none t:LUT6 %% t:* %D
 
 
 design -load read
-proc
 hierarchy -top mux8
+proc
 equiv_opt -assert -map +/xilinx/cells_sim.v synth_xilinx # equivalency check
 design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
 cd mux8 # Constrain all select calls below inside the top module
@@ -35,8 +35,8 @@ select -assert-none t:LUT3 t:LUT6 %% t:* %D
 
 
 design -load read
-proc
 hierarchy -top mux16
+proc
 equiv_opt -assert -map +/xilinx/cells_sim.v synth_xilinx # equivalency check
 design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
 cd mux16 # Constrain all select calls below inside the top module