int total_count = 0;
for (auto module : design->selected_modules()) {
+ SigMap sigmap(module);
+ FfInitVals initvals(&sigmap, module);
for (auto &mem : Mem::get_selected_memories(module)) {
bool changed = false;
for (auto &port : mem.wr_ports) {
}
if (mem.wr_ports.empty() && mem.inits.empty()) {
+ // The whole memory array will contain
+ // only State::Sx, but the embedded read
+ // registers could have reset or init values.
+ // They will probably be optimized away by
+ // opt_dff later.
+ for (int i = 0; i < GetSize(mem.rd_ports); i++) {
+ mem.extract_rdff(i, &initvals);
+ auto &port = mem.rd_ports[i];
+ module->connect(port.data, Const(State::Sx, GetSize(port.data)));
+ }
mem.remove();
total_count++;
}