genX(emit_urb_setup)(struct anv_device *device, struct anv_batch *batch,
const struct gen_l3_config *l3_config,
VkShaderStageFlags active_stages,
- const unsigned entry_size[4])
+ const unsigned entry_size[4],
+ enum gen_urb_deref_block_size *deref_block_size)
{
const struct gen_device_info *devinfo = &device->info;
active_stages &
VK_SHADER_STAGE_TESSELLATION_EVALUATION_BIT,
active_stages & VK_SHADER_STAGE_GEOMETRY_BIT,
- entry_size, entries, start, NULL);
+ entry_size, entries, start, deref_block_size);
#if GEN_GEN == 7 && !GEN_IS_HASWELL
/* From the IVB PRM Vol. 2, Part 1, Section 3.2.1:
}
static void
-emit_urb_setup(struct anv_pipeline *pipeline)
+emit_urb_setup(struct anv_pipeline *pipeline,
+ enum gen_urb_deref_block_size *deref_block_size)
{
unsigned entry_size[4];
for (int i = MESA_SHADER_VERTEX; i <= MESA_SHADER_GEOMETRY; i++) {
genX(emit_urb_setup)(pipeline->device, &pipeline->batch,
pipeline->urb.l3_config,
- pipeline->active_stages, entry_size);
+ pipeline->active_stages, entry_size,
+ deref_block_size);
}
static void
const VkPipelineMultisampleStateCreateInfo *ms_info,
const VkPipelineRasterizationLineStateCreateInfoEXT *line_info,
const struct anv_render_pass *pass,
- const struct anv_subpass *subpass)
+ const struct anv_subpass *subpass,
+ enum gen_urb_deref_block_size urb_deref_block_size)
{
struct GENX(3DSTATE_SF) sf = {
GENX(3DSTATE_SF_header),
#endif
#if GEN_GEN >= 12
- sf.DerefBlockSize = PerPolyDerefMode;
+ sf.DerefBlockSize = urb_deref_block_size;
#endif
const struct brw_vue_prog_data *last_vue_prog_data =
vk_find_struct_const(pCreateInfo->pRasterizationState->pNext,
PIPELINE_RASTERIZATION_LINE_STATE_CREATE_INFO_EXT);
- emit_urb_setup(pipeline);
+ enum gen_urb_deref_block_size urb_deref_block_size;
+ emit_urb_setup(pipeline, &urb_deref_block_size);
assert(pCreateInfo->pVertexInputState);
emit_vertex_input(pipeline, pCreateInfo->pVertexInputState);
assert(pCreateInfo->pRasterizationState);
emit_rs_state(pipeline, pCreateInfo->pInputAssemblyState,
pCreateInfo->pRasterizationState,
- ms_info, line_info, pass, subpass);
+ ms_info, line_info, pass, subpass,
+ urb_deref_block_size);
emit_ms_state(pipeline, ms_info);
emit_ds_state(pipeline, ds_info, pass, subpass);
emit_cb_state(pipeline, cb_info, ms_info);