#include "dev/x86/intdev.hh"
-void
-X86ISA::IntDevice::IntMasterPort::sendMessage(ApicList apics,
- TriggerIntMessage message,
- bool timing)
-{
- ApicList::iterator apicIt;
- for (apicIt = apics.begin(); apicIt != apics.end(); apicIt++) {
- PacketPtr pkt = buildIntRequest(*apicIt, message);
- if (timing) {
- schedTimingReq(pkt, curTick() + latency);
- // The target handles cleaning up the packet in timing mode.
- } else {
- // ignore the latency involved in the atomic transaction
- sendAtomic(pkt);
- assert(pkt->isResponse());
- // also ignore the latency in handling the response
- recvResponse(pkt);
- }
- }
-}
-
void
X86ISA::IntDevice::init()
{
#include "arch/x86/intmessage.hh"
#include "arch/x86/x86_traits.hh"
-#include "mem/mport.hh"
+#include "mem/tport.hh"
#include "sim/sim_object.hh"
-namespace X86ISA {
+namespace X86ISA
+{
template <class Device>
class IntSlavePort : public SimpleTimingPort
typedef std::list<int> ApicList;
-class IntDevice
+template <class Device>
+class IntMasterPort : public QueuedMasterPort
{
- protected:
+ ReqPacketQueue reqQueue;
+ SnoopRespPacketQueue snoopRespQueue;
+
+ Device* device;
+ Tick latency;
- class IntMasterPort : public MessageMasterPort
+ public:
+ IntMasterPort(const std::string& _name, SimObject* _parent,
+ Device* dev, Tick _latency) :
+ QueuedMasterPort(_name, _parent, reqQueue, snoopRespQueue),
+ reqQueue(*_parent, *this), snoopRespQueue(*_parent, *this),
+ device(dev), latency(_latency)
{
- IntDevice* device;
- Tick latency;
- public:
- IntMasterPort(const std::string& _name, SimObject* _parent,
- IntDevice* dev, Tick _latency) :
- MessageMasterPort(_name, _parent), device(dev), latency(_latency)
- {
- }
+ }
- Tick recvResponse(PacketPtr pkt)
- {
- return device->recvResponse(pkt);
+ bool
+ recvTimingResp(PacketPtr pkt) override
+ {
+ return device->recvResponse(pkt);
+ }
+
+ // This is x86 focused, so if this class becomes generic, this would
+ // need to be moved into a subclass.
+ void
+ sendMessage(X86ISA::ApicList apics, TriggerIntMessage message, bool timing)
+ {
+ for (auto id: apics) {
+ PacketPtr pkt = buildIntRequest(id, message);
+ if (timing) {
+ schedTimingReq(pkt, curTick() + latency);
+ // The target handles cleaning up the packet in timing mode.
+ } else {
+ // ignore the latency involved in the atomic transaction
+ sendAtomic(pkt);
+ assert(pkt->isResponse());
+ // also ignore the latency in handling the response
+ device->recvResponse(pkt);
+ }
}
+ }
+};
- // This is x86 focused, so if this class becomes generic, this would
- // need to be moved into a subclass.
- void sendMessage(ApicList apics,
- TriggerIntMessage message, bool timing);
- };
+class IntDevice
+{
+ protected:
- IntMasterPort intMasterPort;
+ IntMasterPort<IntDevice> intMasterPort;
public:
IntDevice(SimObject * parent, Tick latency = 0) :
virtual void init();
- virtual Tick
+ virtual bool
recvResponse(PacketPtr pkt)
{
panic("recvResponse not implemented.\n");
- return 0;
}
};