Fix handling of init attributes with strange width

diff --git a/passes/opt/opt_merge.cc b/passes/opt/opt_merge.cc
index 97989d2710e37d99986058255b8ed55643b05d13..07e4dd39ffcb4a63774510e82f9b1f0edda8d03d 100644 (file)
--- a/passes/opt/opt_merge.cc
+++ b/passes/opt/opt_merge.cc
@@ -280,8 +280,12 @@ struct OptMergeWorker
 
                dff_init_map.set(module);
                for (auto &it : module->wires_)
-                       if (it.second->attributes.count("\\init") != 0)
-                               dff_init_map.add(it.second, it.second->attributes.at("\\init"));
+                       if (it.second->attributes.count("\\init") != 0) {
+                               Const initval = it.second->attributes.at("\\init");
+                               for (int i = 0; i < GetSize(initval) && i < GetSize(it.second); i++)
+                                       if (initval[i] == State::S0 || initval[i] == State::S1)
+                                               dff_init_map.add(SigBit(it.second, i), initval[i]);
+                       }
 
                bool did_something = true;
                while (did_something)

diff --git a/passes/opt/opt_rmdff.cc b/passes/opt/opt_rmdff.cc
index 00094738c980ce5fb01e0cfba73b237435476b28..0eefd6a86cf71b9a129ec7e9e86912fbe8c9a142 100644 (file)
--- a/passes/opt/opt_rmdff.cc
+++ b/passes/opt/opt_rmdff.cc
@@ -244,7 +244,9 @@ struct OptRmdffPass : public Pass {
                        {
                                if (wire->attributes.count("\\init") != 0) {
                                        Const initval = wire->attributes.at("\\init");
-                                       dff_init_map.add(wire, initval);
+                                       for (int i = 0; i < GetSize(initval) && i < GetSize(wire); i++)
+                                               if (initval[i] == State::S0 || initval[i] == State::S1)
+                                                       dff_init_map.add(SigBit(wire, i), initval[i]);
                                        for (int i = 0; i < GetSize(wire); i++) {
                                                SigBit wire_bit(wire, i), mapped_bit = assign_map(wire_bit);
                                                if (mapped_bit.wire) {