[AArch64] Force __builtin_aarch64_fp[sc]r argument into a REG

The testcase triggered an ICE because the builtin expansion
code passed the output of expand_normal directly to the SET_FP[SC]R
generator, without forcing it into a register first.

gcc/
	* config/aarch64/aarch64-builtins.c (aarch64_expand_builtin): Force
	__builtin_aarch64_fp[sc]r arguments into a register.

gcc/testsuite/
	* gcc.target/aarch64/fpcr_fpsr_1.c: New file.

From-SVN: r228116

diff --git a/gcc/ChangeLog b/gcc/ChangeLog
index fbc353d381d0c5305a2f622cd66f28ce2ac2d092..97b6cdc4fe779b1bf31e2784a231e82fab7784c6 100644 (file)
--- a/gcc/ChangeLog
+++ b/gcc/ChangeLog
@@ -1,3 +1,8 @@
+2015-09-25  Richard Sandiford  <richard.sandiford@arm.com>
+
+       * config/aarch64/aarch64-builtins.c (aarch64_expand_builtin): Force
+       __builtin_aarch64_fp[sc]r arguments into a register.
+
 2015-09-25  H.J. Lu  <hongjiu.lu@intel.com>
 
        * config.gcc (x86_archs): Replace lakemount with lakemont.

diff --git a/gcc/config/aarch64/aarch64-builtins.c b/gcc/config/aarch64/aarch64-builtins.c
index 4ed2a8b6cb0be534065ec833942368fadb86451b..80916a9fca230a88f56a4dc615cb82b0bff31afa 100644 (file)
--- a/gcc/config/aarch64/aarch64-builtins.c
+++ b/gcc/config/aarch64/aarch64-builtins.c
@@ -1171,7 +1171,7 @@ aarch64_expand_builtin (tree exp,
          icode = (fcode == AARCH64_BUILTIN_SET_FPSR) ?
            CODE_FOR_set_fpsr : CODE_FOR_set_fpcr;
          arg0 = CALL_EXPR_ARG (exp, 0);
-         op0 = expand_normal (arg0);
+         op0 = force_reg (SImode, expand_normal (arg0));
          pat = GEN_FCN (icode) (op0);
        }
       emit_insn (pat);

diff --git a/gcc/testsuite/ChangeLog b/gcc/testsuite/ChangeLog
index 325a692f15a4038337dbd72fa3294a4b21565746..07858088f7db8c3625a96740f22418d15d389371 100644 (file)
--- a/gcc/testsuite/ChangeLog
+++ b/gcc/testsuite/ChangeLog
@@ -1,3 +1,7 @@
+2015-09-25  Richard Sandiford  <richard.sandiford@arm.com>
+
+       * gcc.target/aarch64/fpcr_fpsr_1.c: New file.
+
 2015-09-25  H.J. Lu  <hongjiu.lu@intel.com>
 
        * gcc.target/i386/pr66749.c (dg-options): Replace

diff --git a/gcc/testsuite/gcc.target/aarch64/fpcr_fpsr_1.c b/gcc/testsuite/gcc.target/aarch64/fpcr_fpsr_1.c
new file mode 100644 (file)
index 0000000..29aa1f4
--- /dev/null
+++ b/gcc/testsuite/gcc.target/aarch64/fpcr_fpsr_1.c
@@ -0,0 +1,26 @@
+/* { dg-do compile } */
+/* { dg-options "-O2" } */
+
+void
+f1 (int *x)
+{
+  __builtin_aarch64_set_fpsr (*x);
+}
+
+void
+f2 (int *x)
+{
+  __builtin_aarch64_set_fpcr (*x);
+}
+
+void
+f3 (int *x)
+{
+  *x = __builtin_aarch64_get_fpsr ();
+}
+
+void
+f4 (int *x)
+{
+  *x = __builtin_aarch64_get_fpcr ();
+}