Merge remote-tracking branch 'origin/master' into eddie/cleanup

diff --cc backends/firrtl/firrtl.cc
Simple merge

diff --cc frontends/ast/simplify.cc
Simple merge

diff --cc kernel/rtlil.h
Simple merge

diff --cc passes/opt/opt_expr.cc
index ef4b8b57a0bc8b9cfc76e1f83594ec5fd21aecf6,acdc399376bb5e2ede80c7bfcec9825b4ecbfdab..b2dc9a44817bcd2f78d5dbba426b688545fb82a1
--- 1/passes/opt/opt_expr.cc
--- 2/passes/opt/opt_expr.cc
+++ b/passes/opt/opt_expr.cc
@@@ -640,10 -641,38 +640,35 @@@ void replace_const_cells(RTLIL::Design 
                                        did_something = true;
                                }
                        }
+ 
+                       if (cell->type.in("$add", "$sub")) {
+                               RTLIL::SigSpec sig_a = assign_map(cell->getPort("\\A"));
+                               RTLIL::SigSpec sig_b = assign_map(cell->getPort("\\B"));
+                               RTLIL::SigSpec sig_y = cell->getPort("\\Y");
+                               bool sub = cell->type == "$sub";
+ 
+                               int i;
+                               for (i = 0; i < GetSize(sig_y); i++) {
+                                       if (sig_b.at(i, State::Sx) == State::S0 && sig_a.at(i, State::Sx) != State::Sx)
+                                               module->connect(sig_y[i], sig_a[i]);
+                                       else if (!sub && sig_a.at(i, State::Sx) == State::S0 && sig_b.at(i, State::Sx) != State::Sx)
+                                               module->connect(sig_y[i], sig_b[i]);
+                                       else
+                                               break;
+                               }
+                               if (i > 0) {
+                                       cover_list("opt.opt_expr.fine", "$add", "$sub", cell->type.str());
+                                       cell->setPort("\\A", sig_a.extract_end(i));
+                                       cell->setPort("\\B", sig_b.extract_end(i));
+                                       cell->setPort("\\Y", sig_y.extract_end(i));
+                                       cell->fixup_parameters();
+                                       did_something = true;
+                               }
+                       }
                }
  
 -              if (cell->type == "$reduce_xor" || cell->type == "$reduce_xnor" || cell->type == "$shift" || cell->type == "$shiftx" ||
 -                              cell->type == "$shl" || cell->type == "$shr" || cell->type == "$sshl" || cell->type == "$sshr" ||
 -                              cell->type == "$lt" || cell->type == "$le" || cell->type == "$ge" || cell->type == "$gt" ||
 -                              cell->type == "$neg" || cell->type == "$add" || cell->type == "$sub" ||
 -                              cell->type == "$mul" || cell->type == "$div" || cell->type == "$mod" || cell->type == "$pow")
 +              if (cell->type.in("$reduce_xor", "$reduce_xnor", "$shift", "$shiftx", "$shl", "$shr", "$sshl", "$sshr",
 +                                      "$lt", "$le", "$ge", "$gt", "$neg", "$add", "$sub", "$mul", "$div", "$mod", "$pow"))
                {
                        RTLIL::SigSpec sig_a = assign_map(cell->getPort("\\A"));
                        RTLIL::SigSpec sig_b = cell->hasPort("\\B") ? assign_map(cell->getPort("\\B")) : RTLIL::SigSpec();

diff --cc passes/techmap/abc.cc
Simple merge