Use Pins/DiffPairs(assert_width) where appropriate.

diff --git a/nmigen_boards/dev/flash.py b/nmigen_boards/dev/flash.py
index 9cb8d90b975e6a586a9bca62a68661f47600706e..817b6d40d00b5d8255236c086729825ca42e3a49 100644 (file)
--- a/nmigen_boards/dev/flash.py
+++ b/nmigen_boards/dev/flash.py
@@ -11,25 +11,27 @@ def SPIFlashResources(*args, cs, clk, mosi, miso, wp=None, hold=None, attrs=None
     if attrs is not None:
         io_all.append(attrs)
     io_all.append(Subsignal("cs",  PinsN(cs, dir="o")))
-    io_all.append(Subsignal("clk", Pins(clk, dir="o")))
+    io_all.append(Subsignal("clk", Pins(clk, dir="o", assert_width=1)))
 
     io_1x = list(io_all)
-    io_1x.append(Subsignal("mosi", Pins(mosi, dir="o")))
-    io_1x.append(Subsignal("miso", Pins(miso, dir="i")))
+    io_1x.append(Subsignal("mosi", Pins(mosi, dir="o", assert_width=1)))
+    io_1x.append(Subsignal("miso", Pins(miso, dir="i", assert_width=1)))
     if wp is not None and hold is not None:
-        io_1x.append(Subsignal("wp",   PinsN(wp,   dir="o")))
-        io_1x.append(Subsignal("hold", PinsN(hold, dir="o")))
+        io_1x.append(Subsignal("wp",   PinsN(wp,   dir="o", assert_width=1)))
+        io_1x.append(Subsignal("hold", PinsN(hold, dir="o", assert_width=1)))
     resources.append(Resource.family(*args, default_name="spi_flash", ios=io_1x,
                                      name_suffix="1x"))
 
     io_2x = list(io_all)
-    io_2x.append(Subsignal("dq", Pins(" ".join([mosi, miso]), dir="io")))
+    io_2x.append(Subsignal("dq", Pins(" ".join([mosi, miso]), dir="io",
+                                      assert_width=2)))
     resources.append(Resource.family(*args, default_name="spi_flash", ios=io_2x,
                                      name_suffix="2x"))
 
     if wp is not None and hold is not None:
         io_4x = list(io_all)
-        io_4x.append(Subsignal("dq", Pins(" ".join([mosi, miso, wp, hold]), dir="io")))
+        io_4x.append(Subsignal("dq", Pins(" ".join([mosi, miso, wp, hold]), dir="io",
+                                          assert_width=4)))
         resources.append(Resource.family(*args, default_name="spi_flash", ios=io_4x,
                                          name_suffix="4x"))
 

diff --git a/nmigen_boards/dev/sram.py b/nmigen_boards/dev/sram.py
index 4e2cd9102322d5d399306ce4cb4e730dbe2c4727..4eb4eca723db19ac1632d7a4d7f7e179e432c1a4 100644 (file)
--- a/nmigen_boards/dev/sram.py
+++ b/nmigen_boards/dev/sram.py
@@ -6,9 +6,9 @@ __all__ = ["SRAMResource"]
 
 def SRAMResource(*args, cs, oe, we, a, d, dm=None, attrs=None):
     io = []
-    io.append(Subsignal("cs", PinsN(cs, dir="o")))
-    io.append(Subsignal("oe", PinsN(oe, dir="o")))
-    io.append(Subsignal("we", PinsN(we, dir="o")))
+    io.append(Subsignal("cs", PinsN(cs, dir="o", assert_width=1)))
+    io.append(Subsignal("oe", PinsN(oe, dir="o", assert_width=1)))
+    io.append(Subsignal("we", PinsN(we, dir="o", assert_width=1)))
     io.append(Subsignal("a", Pins(a, dir="o")))
     io.append(Subsignal("d", Pins(d, dir="io")))
     if dm is not None:

diff --git a/nmigen_boards/dev/uart.py b/nmigen_boards/dev/uart.py
index ba2c1b04059401450bc8ed87b6d8ca6c427125cb..706e50c813d75f8c20575ad2f0abb2fb002c7b65 100644 (file)
--- a/nmigen_boards/dev/uart.py
+++ b/nmigen_boards/dev/uart.py
@@ -7,20 +7,20 @@ __all__ = ["UARTResource", "IrDAResource"]
 def UARTResource(*args, rx, tx, rts=None, cts=None, dtr=None, dsr=None, dcd=None, ri=None,
                  attrs=None):
     io = []
-    io.append(Subsignal("rx", Pins(rx, dir="i")))
-    io.append(Subsignal("tx", Pins(tx, dir="o")))
+    io.append(Subsignal("rx", Pins(rx, dir="i", assert_width=1)))
+    io.append(Subsignal("tx", Pins(tx, dir="o", assert_width=1)))
     if rts is not None:
-        io.append(Subsignal("rts", Pins(rts, dir="o")))
+        io.append(Subsignal("rts", Pins(rts, dir="o", assert_width=1)))
     if cts is not None:
-        io.append(Subsignal("cts", Pins(cts, dir="i")))
+        io.append(Subsignal("cts", Pins(cts, dir="i", assert_width=1)))
     if dtr is not None:
-        io.append(Subsignal("dtr", Pins(dtr, dir="o")))
+        io.append(Subsignal("dtr", Pins(dtr, dir="o", assert_width=1)))
     if dsr is not None:
-        io.append(Subsignal("dsr", Pins(dsr, dir="i")))
+        io.append(Subsignal("dsr", Pins(dsr, dir="i", assert_width=1)))
     if dcd is not None:
-        io.append(Subsignal("dcd", Pins(dcd, dir="i")))
+        io.append(Subsignal("dcd", Pins(dcd, dir="i", assert_width=1)))
     if ri is not None:
-        io.append(Subsignal("ri", Pins(ri, dir="i")))
+        io.append(Subsignal("ri", Pins(ri, dir="i", assert_width=1)))
     if attrs is not None:
         io.append(attrs)
     return Resource.family(*args, default_name="uart", ios=io)
@@ -31,12 +31,12 @@ def IrDAResource(number, *, rx, tx, en=None, sd=None, attrs=None):
     # be specified, and it is mapped to a logic level en subsignal.
     assert (en is not None) ^ (sd is not None)
     io = []
-    io.append(Subsignal("rx", Pins(rx, dir="i")))
-    io.append(Subsignal("tx", Pins(tx, dir="o")))
+    io.append(Subsignal("rx", Pins(rx, dir="i", assert_width=1)))
+    io.append(Subsignal("tx", Pins(tx, dir="o", assert_width=1)))
     if en is not None:
-        io.append(Subsignal("en", Pins(en, dir="o")))
+        io.append(Subsignal("en", Pins(en, dir="o", assert_width=1)))
     if sd is not None:
-        io.append(Subsignal("en", PinsN(sd, dir="o")))
+        io.append(Subsignal("en", PinsN(sd, dir="o", assert_width=1)))
     if attrs is not None:
         io.append(attrs)
     return Resource("irda", number, *io)