r600g: move sampler/ubo index registers before temp reg

temp_reg needs to be last, as we increment things
away from it, otherwise on cayman some tests were overwriting
the index regs.

Fixes 2 piglit with ARB_gpu_shader5 forced on cayman.

Reviewed-by: Glenn Kennard <glenn.kennard@gmail.com>
Signed-off-by: Dave Airlie <airlied@redhat.com>

diff --git a/src/gallium/drivers/r600/r600_shader.c b/src/gallium/drivers/r600/r600_shader.c
index af7622e9b3417249c2cf16d7ebb757216a92050c..1a72bf6e77e2ada2bb04d37aa5be7dd47f32affd 100644 (file)
--- a/src/gallium/drivers/r600/r600_shader.c
+++ b/src/gallium/drivers/r600/r600_shader.c
@@ -1931,15 +1931,14 @@ static int r600_shader_from_tgsi(struct r600_context *rctx,
        ctx.file_offset[TGSI_FILE_IMMEDIATE] = V_SQ_ALU_SRC_LITERAL;
        ctx.bc->ar_reg = ctx.file_offset[TGSI_FILE_TEMPORARY] +
                        ctx.info.file_max[TGSI_FILE_TEMPORARY] + 1;
+       ctx.bc->index_reg[0] = ctx.bc->ar_reg + 1;
+       ctx.bc->index_reg[1] = ctx.bc->ar_reg + 2;
+
        if (ctx.type == TGSI_PROCESSOR_GEOMETRY) {
-               ctx.gs_export_gpr_treg = ctx.bc->ar_reg + 1;
-               ctx.temp_reg = ctx.bc->ar_reg + 2;
-               ctx.bc->index_reg[0] = ctx.bc->ar_reg + 3;
-               ctx.bc->index_reg[1] = ctx.bc->ar_reg + 4;
+               ctx.gs_export_gpr_treg = ctx.bc->ar_reg + 3;
+               ctx.temp_reg = ctx.bc->ar_reg + 4;
        } else {
-               ctx.temp_reg = ctx.bc->ar_reg + 1;
-               ctx.bc->index_reg[0] = ctx.bc->ar_reg + 2;
-               ctx.bc->index_reg[1] = ctx.bc->ar_reg + 3;
+               ctx.temp_reg = ctx.bc->ar_reg + 3;
        }
 
        shader->max_arrays = 0;