Improved handling of private names in opt_clean and rename commands

diff --git a/passes/cmds/rename.cc b/passes/cmds/rename.cc
index 906256a1c760735bd62dc621fe48cf7c186785bc..a582de56d67ef31b59181924b58b0cc54c3ca3f0 100644 (file)
--- a/passes/cmds/rename.cc
+++ b/passes/cmds/rename.cc
@@ -63,6 +63,12 @@ struct RenamePass : public Pass {
                log("Rename the specified object. Note that selection patterns are not supported\n");
                log("by this command.\n");
                log("\n");
+               log("\n");
+               log("    rename -enumerate [selection]\n");
+               log("\n");
+               log("Assign short auto-generated names to all selected wires and cells with private\n");
+               log("names.\n");
+               log("\n");
        }
        virtual void execute(std::vector<std::string> args, RTLIL::Design *design)
        {
@@ -72,17 +78,43 @@ struct RenamePass : public Pass {
                for (argidx = 1; argidx < args.size(); argidx++)
                {
                        std::string arg = args[argidx];
-                       //if (arg == "-enumerate") {
-                       //      flag_enumerate = true;
-                       //      continue;
-                       //}
+                       if (arg == "-enumerate") {
+                               flag_enumerate = true;
+                               continue;
+                       }
                        break;
                }
 
                if (flag_enumerate)
                {
                        extra_args(args, argidx, design);
-                       log_cmd_error("Sorry: Enumeration mode is not implemented at the moment.\n");
+
+                       for (auto &mod : design->modules)
+                       {
+                               int counter = 0;
+
+                               RTLIL::Module *module = mod.second;
+                               if (!design->selected(module))
+                                       continue;
+
+                               std::map<RTLIL::IdString, RTLIL::Wire*> new_wires;
+                               for (auto &it : module->wires) {
+                                       if (it.first[0] == '$' && design->selected(module, it.second))
+                                               do it.second->name = stringf("\\_%d_", counter++);
+                                               while (module->count_id(it.second->name) > 0);
+                                       new_wires[it.second->name] = it.second;
+                               }
+                               module->wires.swap(new_wires);
+
+                               std::map<RTLIL::IdString, RTLIL::Cell*> new_cells;
+                               for (auto &it : module->cells) {
+                                       if (it.first[0] == '$' && design->selected(module, it.second))
+                                               do it.second->name = stringf("\\_%d_", counter++);
+                                               while (module->count_id(it.second->name) > 0);
+                                       new_cells[it.second->name] = it.second;
+                               }
+                               module->cells.swap(new_cells);
+                       }
                }
                else
                {

diff --git a/passes/opt/opt_clean.cc b/passes/opt/opt_clean.cc
index 983e5d5fa33efa8265407b6edbc3aa95cc36f66e..c6ca8c25aa244938740d29203ec3f3764e4bb027 100644 (file)
--- a/passes/opt/opt_clean.cc
+++ b/passes/opt/opt_clean.cc
@@ -122,10 +122,10 @@ static bool check_public_name(RTLIL::IdString id)
 {
        if (id[0] == '$')
                return false;
-#if 0
+       if (id.substr(0, 2) == "\\_" && (id[id.size()-1] == '_' || id.find("_[") != std::string::npos))
+               return false;
        if (id.find(".$") != std::string::npos)
                return false;
-#endif
        return true;
 }