\f
;; Add instructions
-;; %%% define_expand from the very first?
;; %%% splits for addsidi3
; [(set (match_operand:DI 0 "nonimmediate_operand" "")
; (plus:DI (match_operand:DI 1 "general_operand" "")
(const_string "alu")))
(set_attr "mode" "DI")])
-(define_insn "*adddi_3"
+(define_insn "*adddi_3_rex64"
[(set (reg 17)
(compare (neg:DI (match_operand:DI 2 "x86_64_general_operand" "rme"))
(match_operand:DI 1 "x86_64_general_operand" "%0")))
(clobber (match_scratch:DI 0 "=r"))]
- "ix86_match_ccmode (insn, CCZmode)
+ "TARGET_64BIT
+ && ix86_match_ccmode (insn, CCZmode)
&& (GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != MEM)
/* Current assemblers are broken and do not allow @GOTOFF in
ought but a memory context. */
; when negated.
; Also carry flag is reversed compared to cmp, so this converison is valid
; only for comparisons not depending on it.
-(define_insn "*adddi_4"
+(define_insn "*adddi_4_rex64"
[(set (reg 17)
(compare (match_operand:DI 1 "nonimmediate_operand" "0")
(match_operand:DI 2 "x86_64_immediate_operand" "e")))
(clobber (match_scratch:DI 0 "=rm"))]
- "ix86_match_ccmode (insn, CCGCmode)"
+ "TARGET_64BIT
+ && ix86_match_ccmode (insn, CCGCmode)"
"*
{
switch (get_attr_type (insn))
(const_string "alu")))
(set_attr "mode" "DI")])
-(define_insn "*adddi_5"
+(define_insn "*adddi_5_rex64"
[(set (reg 17)
(compare
(plus:DI (match_operand:DI 1 "nonimmediate_operand" "%0")
(match_operand:DI 2 "x86_64_general_operand" "rme"))
(const_int 0)))
(clobber (match_scratch:DI 0 "=r"))]
- "ix86_match_ccmode (insn, CCGOCmode)
+ "TARGET_64BIT
+ && ix86_match_ccmode (insn, CCGOCmode)
&& (GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != MEM)
/* Current assemblers are broken and do not allow @GOTOFF in
ought but a memory context. */
\f
;; Negation instructions
-;; %%% define_expand from the very first?
-
(define_expand "negdi2"
[(parallel [(set (match_operand:DI 0 "nonimmediate_operand" "")
(neg:DI (match_operand:DI 1 "nonimmediate_operand" "")))
"TARGET_64BIT"
"if (!ix86_expand_int_movcc (operands)) FAIL; DONE;")
-(define_insn "x86_movsicc_0_m1_rex64"
+(define_insn "x86_movdicc_0_m1_rex64"
[(set (match_operand:DI 0 "register_operand" "=r")
(if_then_else:DI (ltu (reg:CC 17) (const_int 0))
(const_int -1)
(const_int 0)))
(clobber (reg:CC 17))]
"TARGET_64BIT"
- "sbb{l}\\t%0, %0"
+ "sbb{q}\\t%0, %0"
; Since we don't have the proper number of operands for an alu insn,
; fill in all the blanks.
[(set_attr "type" "alu")
[(set_attr "type" "icmov")
(set_attr "mode" "DI")])
-
(define_expand "movsicc"
[(set (match_operand:SI 0 "register_operand" "")
(if_then_else:SI (match_operand 1 "comparison_operator" "")