boards/targets: SDRAM modules are now litedram.modules

diff --git a/litex/boards/targets/de0nano.py b/litex/boards/targets/de0nano.py
index 7fb9d625824ee1bd07e21fd8ef06bc5851187130..17da0e72554d38ba26da86557c9238311afa2d4f 100755 (executable)
--- a/litex/boards/targets/de0nano.py
+++ b/litex/boards/targets/de0nano.py
@@ -8,7 +8,7 @@ from litex.boards.platforms import de0nano
 from litex.soc.integration.soc_sdram import *
 from litex.soc.integration.builder import *
 
-from litedram.settings import IS42S16160
+from litedram.modules import IS42S16160
 from litedram.phy import GENSDRPHY
 
 

diff --git a/litex/boards/targets/kc705.py b/litex/boards/targets/kc705.py
index 65500af7c91ccfb19c0e5f72bc713937b211efd6..9139be8e085d61952781c774c6da30427a3346bb 100755 (executable)
--- a/litex/boards/targets/kc705.py
+++ b/litex/boards/targets/kc705.py
@@ -11,7 +11,7 @@ from litex.soc.integration.soc_core import mem_decoder
 from litex.soc.integration.soc_sdram import *
 from litex.soc.integration.builder import *
 
-from litedram.settings import MT8JTF12864
+from litedram.modules import MT8JTF12864
 from litedram.phy import k7ddrphy
 
 from liteeth.phy import LiteEthPHY

diff --git a/litex/boards/targets/minispartan6.py b/litex/boards/targets/minispartan6.py
index 04443bdeabe3df4ef5d83b0267808622f1595cde..7c6223671358b8d00f51f52cf7070fee2f512ddd 100755 (executable)
--- a/litex/boards/targets/minispartan6.py
+++ b/litex/boards/targets/minispartan6.py
@@ -10,7 +10,7 @@ from litex.boards.platforms import minispartan6
 from litex.soc.integration.soc_sdram import *
 from litex.soc.integration.builder import *
 
-from litedram.settings import AS4C16M16
+from litedram.modules import AS4C16M16
 from litedram.phy import GENSDRPHY
 
 

diff --git a/litex/boards/targets/sim.py b/litex/boards/targets/sim.py
index b18996eaf06977def14d1e10479969d8ffa4443d..0d08311293ad6cbfa732f8b1cc57cae9829eb56d 100755 (executable)
--- a/litex/boards/targets/sim.py
+++ b/litex/boards/targets/sim.py
@@ -12,7 +12,7 @@ from litex.soc.integration.builder import *
 from litex.soc.cores import uart
 from litex.soc.integration.soc_core import mem_decoder
 
-from litedram.settings import PhySettings, IS42S16160
+from litedram.modules import PhySettings, IS42S16160
 from litedram.model import SDRAMPHYModel
 
 from liteeth.phy.model import LiteEthPHYModel