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Add shregmap -tech xilinx test
authorEddie Hung <eddie@fpgeh.com>
Wed, 12 Jun 2019 15:34:06 +0000 (08:34 -0700)
committerEddie Hung <eddie@fpgeh.com>
Thu, 22 Aug 2019 23:16:54 +0000 (16:16 -0700)
tests/various/shregmap.ys patch | blob | history

diff --git a/tests/various/shregmap.ys b/tests/various/shregmap.ys
index 0e5fe882b9d5caa470b998ea3db6caec6a741703..a717c54f1564abb02d21c46c2423db9065f1e3f6 100644 (file)
--- a/tests/various/shregmap.ys
+++ b/tests/various/shregmap.ys
@@ -64,3 +64,4 @@ sat -verify -prove-asserts -show-ports -seq 5 miter
 
 # design -load gate
 # stat
+