Added syntax for structure oriented extMachInsts.

--HG--
extra : convert_revision : 4a30c58019ad8e3dd8dffb4c4c08eb6914e5c5be

diff --git a/src/arch/isa_parser.py b/src/arch/isa_parser.py
index 21860a2e17a2c2622b374414b2b78b5400143ef6..da17f5a9ddc57ed8fdba12dd5d0d2d54c118bea2 100755 (executable)
--- a/src/arch/isa_parser.py
+++ b/src/arch/isa_parser.py
@@ -363,6 +363,17 @@ def p_def_bitfield_1(t):
     hash_define = '#undef %s\n#define %s\t%s\n' % (t[4], t[4], expr)
     t[0] = GenCode(header_output = hash_define)
 
+# alternate form for structure member: 'def bitfield <ID> <ID>'
+def p_def_bitfield_2(t):
+    'def_bitfield : DEF nothing BITFIELD ID ID SEMI'
+    expr = 'machInst.%s' % t[5]
+    hash_define = '#undef %s\n#define %s\t%s\n' % (t[4], t[4], expr)
+    t[0] = GenCode(header_output = hash_define)
+
+def p_nothing(t):
+    'nothing : empty'
+    t[0] = ''
+
 def p_opt_signed_0(t):
     'opt_signed : SIGNED'
     t[0] = t[1]