sse.md ("mov<mode>_internal"): Use <sseinsnmode> mode attribute for TARGET_AVX512VL.

/gcc
        * config/i386/sse.md ("mov<mode>_internal"): Use <sseinsnmode>
	mode attribute for TARGET_AVX512VL.

	* config/i386/i386.opt (mprefer-avx256): New option.
	* config/i386/i386.c (ix86_target_string): Add -mprefer-avx256
	to flag_opts.
	(ix86_preferred_simd_mode): Return 256-bit AVX modes
	for TARGET_PREFER_AVX256.
	* doc/invoke.texi (x86 Options): Document -mprefer-avx256.

/testsuite

        * gcc.target/i386/avx512f-constant-set.c: New test.

	* g++.dg/ext/pr57362.C: Test __attribute__((target("prefer-avx256"))).
	* gcc.target/i386/avx512f-prefer.c: New test.

From-SVN: r253089

diff --git a/gcc/ChangeLog b/gcc/ChangeLog
index 26c388b35656f0e259192af77a98fae1f8ef9cf1..75b309c4d1d98b936f87e16e5768bf5c0ab3bd7d 100644 (file)
--- a/gcc/ChangeLog
+++ b/gcc/ChangeLog
@@ -1,3 +1,17 @@
+2017-09-22  Sergey Shalnov  <sergey.shalnov@intel.com>
+
+        * config/i386/sse.md ("mov<mode>_internal"): Use <sseinsnmode>
+       mode attribute for TARGET_AVX512VL.
+
+2017-09-21  Sergey Shalnov  <sergey.shalnov@intel.com>
+
+       * config/i386/i386.opt (mprefer-avx256): New option.
+       * config/i386/i386.c (ix86_target_string): Add -mprefer-avx256
+       to flag_opts.
+       (ix86_preferred_simd_mode): Return 256-bit AVX modes
+       for TARGET_PREFER_AVX256.
+       * doc/invoke.texi (x86 Options): Document -mprefer-avx256.
+
 2017-09-21  Jeff Law  <law@redhat.com>
 
        * config/i386/i386.c (ix86_adjust_stack_and_probe_stack_clash):

diff --git a/gcc/config/i386/i386.c b/gcc/config/i386/i386.c
index 270ee5578723826ee42e9de8a3d3864134a9a00b..5e8f58c5e9f817fd360210da34b05a01b8b8cd81 100644 (file)
--- a/gcc/config/i386/i386.c
+++ b/gcc/config/i386/i386.c
@@ -4751,6 +4751,7 @@ ix86_target_string (HOST_WIDE_INT isa, HOST_WIDE_INT isa2,
     { "-mavx256-split-unaligned-load", MASK_AVX256_SPLIT_UNALIGNED_LOAD },
     { "-mavx256-split-unaligned-store",        MASK_AVX256_SPLIT_UNALIGNED_STORE },
     { "-mprefer-avx128",               MASK_PREFER_AVX128 },
+    { "-mprefer-avx256",               MASK_PREFER_AVX256 },
     { "-mcall-ms2sysv-xlogues",                MASK_CALL_MS2SYSV_XLOGUES }
   };
 
@@ -51848,20 +51849,39 @@ ix86_preferred_simd_mode (scalar_mode mode)
   switch (mode)
     {
     case E_QImode:
-      return TARGET_AVX512BW ? V64QImode :
-       (TARGET_AVX && !TARGET_PREFER_AVX128) ? V32QImode : V16QImode;
+      if (TARGET_AVX512BW && !TARGET_PREFER_AVX256)
+       return V64QImode;
+      else if (TARGET_AVX && !TARGET_PREFER_AVX128)
+       return V32QImode;
+      else
+       return V16QImode;
+
     case E_HImode:
-      return TARGET_AVX512BW ? V32HImode :
-       (TARGET_AVX && !TARGET_PREFER_AVX128) ? V16HImode : V8HImode;
+      if (TARGET_AVX512BW && !TARGET_PREFER_AVX256)
+       return V32HImode;
+      else if (TARGET_AVX && !TARGET_PREFER_AVX128)
+       return V16HImode;
+      else
+       return V8HImode;
+
     case E_SImode:
-      return TARGET_AVX512F ? V16SImode :
-       (TARGET_AVX && !TARGET_PREFER_AVX128) ? V8SImode : V4SImode;
+      if (TARGET_AVX512F && !TARGET_PREFER_AVX256)
+       return V16SImode;
+      else if (TARGET_AVX && !TARGET_PREFER_AVX128)
+       return V8SImode;
+      else
+       return V4SImode;
+
     case E_DImode:
-      return TARGET_AVX512F ? V8DImode :
-       (TARGET_AVX && !TARGET_PREFER_AVX128) ? V4DImode : V2DImode;
+      if (TARGET_AVX512F && !TARGET_PREFER_AVX256)
+       return V8DImode;
+      else if (TARGET_AVX && !TARGET_PREFER_AVX128)
+       return V4DImode;
+      else
+       return V2DImode;
 
     case E_SFmode:
-      if (TARGET_AVX512F)
+      if (TARGET_AVX512F && !TARGET_PREFER_AVX256)
        return V16SFmode;
       else if (TARGET_AVX && !TARGET_PREFER_AVX128)
        return V8SFmode;
@@ -51869,7 +51889,7 @@ ix86_preferred_simd_mode (scalar_mode mode)
        return V4SFmode;
 
     case E_DFmode:
-      if (TARGET_AVX512F)
+      if (TARGET_AVX512F && !TARGET_PREFER_AVX256)
        return V8DFmode;
       else if (TARGET_AVX && !TARGET_PREFER_AVX128)
        return V4DFmode;
@@ -51889,8 +51909,14 @@ ix86_preferred_simd_mode (scalar_mode mode)
 static unsigned int
 ix86_autovectorize_vector_sizes (void)
 {
-  return TARGET_AVX512F ? 64 | 32 | 16 :
-    (TARGET_AVX && !TARGET_PREFER_AVX128) ? 32 | 16 : 0;
+  unsigned int bytesizes = 0;
+
+  if (TARGET_AVX512F && !TARGET_PREFER_AVX256)
+    bytesizes |= (64 | 32 | 16);
+  else if (TARGET_AVX && !TARGET_PREFER_AVX128)
+    bytesizes |= (32 | 16);
+
+  return bytesizes;
 }
 
 /* Implemenation of targetm.vectorize.get_mask_mode.  */

diff --git a/gcc/config/i386/i386.opt b/gcc/config/i386/i386.opt
index 81bbc1e2170a1e37b4d79843c4b9aa0fc0843c8b..1c76b71dd577cab4127e65b152c8ceced8027e8b 100644 (file)
--- a/gcc/config/i386/i386.opt
+++ b/gcc/config/i386/i386.opt
@@ -588,9 +588,13 @@ Do dispatch scheduling if processor is bdver1, bdver2, bdver3, bdver4
 or znver1 and Haifa scheduling is selected.
 
 mprefer-avx128
-Target Report Mask(PREFER_AVX128) SAVE
+Target Report Mask(PREFER_AVX128) Save
 Use 128-bit AVX instructions instead of 256-bit AVX instructions in the auto-vectorizer.
 
+mprefer-avx256
+Target Report Mask(PREFER_AVX256) Save
+Use 256-bit AVX instructions instead of 512-bit AVX instructions in the auto-vectorizer.
+
 ;; ISA support
 
 m32

diff --git a/gcc/config/i386/sse.md b/gcc/config/i386/sse.md
index d61afcff0f4e4c5da299e4d94204229adfd7c7ed..0c26bd13d019caa8360cdd02ec0735a73163edfc 100644 (file)
--- a/gcc/config/i386/sse.md
+++ b/gcc/config/i386/sse.md
@@ -978,7 +978,7 @@
    (set (attr "mode")
        (cond [(and (eq_attr "alternative" "1")
                    (match_test "TARGET_AVX512VL"))
-                (const_string "XI")
+                (const_string "<sseinsnmode>")
               (and (match_test "<MODE_SIZE> == 16")
                    (ior (match_test "TARGET_SSE_PACKED_SINGLE_INSN_OPTIMAL")
                         (and (eq_attr "alternative" "3")

diff --git a/gcc/doc/invoke.texi b/gcc/doc/invoke.texi
index db843edd427e381cd9cb7fe67f74e6772acc1b73..5e39c0efeb9b8b6ffc5b1bc7b154c6b3d9eed375 100644 (file)
--- a/gcc/doc/invoke.texi
+++ b/gcc/doc/invoke.texi
@@ -1194,7 +1194,7 @@ See RS/6000 and PowerPC Options.
 -mincoming-stack-boundary=@var{num} @gol
 -mcld  -mcx16  -msahf  -mmovbe  -mcrc32 @gol
 -mrecip  -mrecip=@var{opt} @gol
--mvzeroupper  -mprefer-avx128 @gol
+-mvzeroupper  -mprefer-avx128 -mprefer-avx256 @gol
 -mmmx  -msse  -msse2  -msse3  -mssse3  -msse4.1  -msse4.2  -msse4  -mavx @gol
 -mavx2  -mavx512f  -mavx512pf  -mavx512er  -mavx512cd  -mavx512vl @gol
 -mavx512bw  -mavx512dq  -mavx512ifma  -mavx512vbmi  -msha  -maes @gol
@@ -25858,6 +25858,11 @@ intrinsics.
 This option instructs GCC to use 128-bit AVX instructions instead of
 256-bit AVX instructions in the auto-vectorizer.
 
+@item -mprefer-avx256
+@opindex mprefer-avx256
+This option instructs GCC to use 256-bit AVX instructions instead of
+512-bit AVX instructions in the auto-vectorizer.
+
 @item -mcx16
 @opindex mcx16
 This option enables GCC to generate @code{CMPXCHG16B} instructions in 64-bit

diff --git a/gcc/testsuite/ChangeLog b/gcc/testsuite/ChangeLog
index 04f0c1866359a39437a4b92ef54792241d1f89be..6f25855cdb1289ee73c1951f9eda8c89634d80aa 100644 (file)
--- a/gcc/testsuite/ChangeLog
+++ b/gcc/testsuite/ChangeLog
@@ -1,3 +1,12 @@
+2017-09-22  Sergey Shalnov  <sergey.shalnov@intel.com>
+
+        * gcc.target/i386/avx512f-constant-set.c: New test.
+
+2017-09-21  Sergey Shalnov  <sergey.shalnov@intel.com>
+
+       * g++.dg/ext/pr57362.C: Test __attribute__((target("prefer-avx256"))).
+       * gcc.target/i386/avx512f-prefer.c: New test.
+
 2017-09-21  Rainer Orth  <ro@CeBiTec.Uni-Bielefeld.DE>
 
        * lib/target-supports.exp

diff --git a/gcc/testsuite/g++.dg/ext/pr57362.C b/gcc/testsuite/g++.dg/ext/pr57362.C
index 71c53d3761817e7be1b09a98a9ba8827226ca162..3613b63a13728ba64b2e0cd3fa47760dc9a5ed1e 100644 (file)
--- a/gcc/testsuite/g++.dg/ext/pr57362.C
+++ b/gcc/testsuite/g++.dg/ext/pr57362.C
@@ -81,6 +81,8 @@ __attribute__((target("dispatch-scheduler")))
 int foo(void) { return 1; }
 __attribute__((target("prefer-avx128")))
 int foo(void) { return 1; }
+__attribute__((target("prefer-avx256")))
+int foo(void) { return 1; }
 __attribute__((target("32")))
 int foo(void) { return 1; }
 __attribute__((target("64")))

diff --git a/gcc/testsuite/gcc.target/i386/avx512f-constant-set.c b/gcc/testsuite/gcc.target/i386/avx512f-constant-set.c
new file mode 100644 (file)
index 0000000..022627c
--- /dev/null
+++ b/gcc/testsuite/gcc.target/i386/avx512f-constant-set.c
@@ -0,0 +1,11 @@
+/* { dg-do compile } */
+/* { dg-options "-O3 -march=skylake-avx512" } */
+/* { dg-final { scan-assembler-not "%zmm\[0-9\]+" } } */
+
+void
+avx512f_test (short *table)
+{
+  int i;
+  for (i = 0; i < 128; ++i)
+    table[i] = -1;
+}

diff --git a/gcc/testsuite/gcc.target/i386/avx512f-prefer.c b/gcc/testsuite/gcc.target/i386/avx512f-prefer.c
new file mode 100644 (file)
index 0000000..defe51e
--- /dev/null
+++ b/gcc/testsuite/gcc.target/i386/avx512f-prefer.c
@@ -0,0 +1,18 @@
+/* { dg-do compile } */
+/* { dg-options "-O3 -march=skylake-avx512 -mprefer-avx256" } */
+/* { dg-final { scan-assembler-not "%zmm\[0-9\]+" } } */
+/* { dg-final { scan-assembler "vmulpd" } } */
+
+#define N 1024
+
+double a[N], b[N], c[N];
+
+void
+avx512f_test (void)
+{
+  int i;
+
+  for (i = 0; i < N; i++)
+    c[i] = a[i] * b[i];
+}
+