re PR target/81616 (Update -mtune=generic for the current Intel and AMD processors)

	PR target/81616
	* athlon.md: Disable for generic.
	* haswell.md: Enable for generic.
	* i386.c (ix86_sched_init_global): Add core hooks for generic.
	* x86-tune-sched.c (ix86_issue_rate): Increase issue rate for generic
	to 4.
	(ix86_adjust_cost): Move generic to haswell path.

From-SVN: r255395

diff --git a/gcc/ChangeLog b/gcc/ChangeLog
index 57ef007e21eb1acad143d73eb5f89fbda1e34beb..3510252f045acfa41b093bfc31038ebcd401764d 100644 (file)
--- a/gcc/ChangeLog
+++ b/gcc/ChangeLog
@@ -1,3 +1,13 @@
+2017-12-01  Jan Hubicka  <hubicka@ucw.cz>
+
+       PR target/81616
+       * athlon.md: Disable for generic.
+       * haswell.md: Enable for generic.
+       * i386.c (ix86_sched_init_global): Add core hooks for generic.
+       * x86-tune-sched.c (ix86_issue_rate): Increase issue rate for generic
+       to 4.
+       (ix86_adjust_cost): Move generic to haswell path.
+
 2017-12-04  Eric Botcazou  <ebotcazou@adacore.com>
 
        * config/sparc/sparc.c (sparc_do_work_around_errata): Use mem_ref

diff --git a/gcc/config/i386/athlon.md b/gcc/config/i386/athlon.md
index 4e34ede6aefb86524e8ce290bdae26248d752d7c..daabff24367641b8de5c70caadbbec60afa7109d 100644 (file)
--- a/gcc/config/i386/athlon.md
+++ b/gcc/config/i386/athlon.md
@@ -151,11 +151,11 @@
 
 ;; Jump instructions are executed in the branch unit completely transparent to us
 (define_insn_reservation "athlon_branch" 0
-                        (and (eq_attr "cpu" "athlon,k8,generic,amdfam10")
+                        (and (eq_attr "cpu" "athlon,k8,amdfam10")
                              (eq_attr "type" "ibr"))
                         "athlon-direct,athlon-ieu")
 (define_insn_reservation "athlon_call" 0
-                        (and (eq_attr "cpu" "athlon,k8,generic")
+                        (and (eq_attr "cpu" "athlon,k8")
                              (eq_attr "type" "call,callv"))
                         "athlon-vector,athlon-ieu")
 (define_insn_reservation "athlon_call_amdfam10" 0
@@ -166,15 +166,15 @@
 ;; Latency of push operation is 3 cycles, but ESP value is available
 ;; earlier
 (define_insn_reservation "athlon_push" 2
-                        (and (eq_attr "cpu" "athlon,k8,generic,amdfam10")
+                        (and (eq_attr "cpu" "athlon,k8,amdfam10")
                              (eq_attr "type" "push"))
                         "athlon-direct,athlon-agu,athlon-store")
 (define_insn_reservation "athlon_pop" 4
-                        (and (eq_attr "cpu" "athlon,k8,generic")
+                        (and (eq_attr "cpu" "athlon,k8")
                              (eq_attr "type" "pop"))
                         "athlon-vector,athlon-load,athlon-ieu")
 (define_insn_reservation "athlon_pop_k8" 3
-                        (and (eq_attr "cpu" "k8,generic")
+                        (and (eq_attr "cpu" "k8")
                              (eq_attr "type" "pop"))
                         "athlon-double,(athlon-ieu+athlon-load)")
 (define_insn_reservation "athlon_pop_amdfam10" 3
@@ -186,13 +186,13 @@
                              (eq_attr "type" "leave"))
                         "athlon-vector,(athlon-ieu+athlon-load)")
 (define_insn_reservation "athlon_leave_k8" 3
-                        (and (eq_attr "cpu" "k8,generic,amdfam10")
+                        (and (eq_attr "cpu" "k8,amdfam10")
                              (eq_attr "type" "leave"))
                         "athlon-double,(athlon-ieu+athlon-load)")
 
 ;; Lea executes in AGU unit with 2 cycles latency.
 (define_insn_reservation "athlon_lea" 2
-                        (and (eq_attr "cpu" "athlon,k8,generic")
+                        (and (eq_attr "cpu" "athlon,k8")
                              (eq_attr "type" "lea"))
                         "athlon-direct,athlon-agu,nothing")
 ;; Lea executes in AGU unit with 1 cycle latency on AMDFAM10
@@ -209,13 +209,13 @@
                         "athlon-vector,athlon-ieu0,athlon-mult,nothing,nothing,athlon-ieu0")
 ;; ??? Widening multiply is vector or double.
 (define_insn_reservation "athlon_imul_k8_DI" 4
-                        (and (eq_attr "cpu" "k8,generic,amdfam10")
+                        (and (eq_attr "cpu" "k8,amdfam10")
                              (and (eq_attr "type" "imul")
                                   (and (eq_attr "mode" "DI")
                                        (eq_attr "memory" "none,unknown"))))
                         "athlon-direct0,athlon-ieu0,athlon-mult,nothing,athlon-ieu0")
 (define_insn_reservation "athlon_imul_k8" 3
-                        (and (eq_attr "cpu" "k8,generic,amdfam10")
+                        (and (eq_attr "cpu" "k8,amdfam10")
                              (and (eq_attr "type" "imul")
                                   (eq_attr "memory" "none,unknown")))
                         "athlon-direct0,athlon-ieu0,athlon-mult,athlon-ieu0")
@@ -231,13 +231,13 @@
                                   (eq_attr "memory" "load,both")))
                         "athlon-vector,athlon-load,athlon-ieu,athlon-mult,nothing,nothing,athlon-ieu")
 (define_insn_reservation "athlon_imul_mem_k8_DI" 7
-                        (and (eq_attr "cpu" "k8,generic,amdfam10")
+                        (and (eq_attr "cpu" "k8,amdfam10")
                              (and (eq_attr "type" "imul")
                                   (and (eq_attr "mode" "DI")
                                        (eq_attr "memory" "load,both"))))
                         "athlon-vector,athlon-load,athlon-ieu,athlon-mult,nothing,athlon-ieu")
 (define_insn_reservation "athlon_imul_mem_k8" 6
-                        (and (eq_attr "cpu" "k8,generic,amdfam10")
+                        (and (eq_attr "cpu" "k8,amdfam10")
                              (and (eq_attr "type" "imul")
                                   (eq_attr "memory" "load,both")))
                         "athlon-vector,athlon-load,athlon-ieu,athlon-mult,athlon-ieu")
@@ -251,12 +251,12 @@
 ;; Using the same heuristics for amdfam10 as K8 with idiv
 
 (define_insn_reservation "athlon_idiv" 6
-                        (and (eq_attr "cpu" "athlon,k8,generic,amdfam10")
+                        (and (eq_attr "cpu" "athlon,k8,amdfam10")
                              (and (eq_attr "type" "idiv")
                                   (eq_attr "memory" "none,unknown")))
                         "athlon-vector,(athlon-ieu0*6+(athlon-fpsched,athlon-fvector))")
 (define_insn_reservation "athlon_idiv_mem" 9
-                        (and (eq_attr "cpu" "athlon,k8,generic,amdfam10")
+                        (and (eq_attr "cpu" "athlon,k8,amdfam10")
                              (and (eq_attr "type" "idiv")
                                   (eq_attr "memory" "load,both")))
                         "athlon-vector,((athlon-load,athlon-ieu0*6)+(athlon-fpsched,athlon-fvector))")
@@ -264,13 +264,13 @@
 ;; as idiv to create smaller automata.  This probably does not matter much.
 ;; Using the same heuristics for amdfam10 as K8 with idiv
 (define_insn_reservation "athlon_str" 6
-                        (and (eq_attr "cpu" "athlon,k8,generic,amdfam10")
+                        (and (eq_attr "cpu" "athlon,k8,amdfam10")
                              (and (eq_attr "type" "str")
                                   (eq_attr "memory" "load,both,store")))
                         "athlon-vector,athlon-load,athlon-ieu0*6")
 
 (define_insn_reservation "athlon_idirect" 1
-                        (and (eq_attr "cpu" "athlon,k8,generic")
+                        (and (eq_attr "cpu" "athlon,k8")
                              (and (eq_attr "athlon_decode" "direct")
                                   (and (eq_attr "unit" "integer,unknown")
                                        (eq_attr "memory" "none,unknown"))))
@@ -282,7 +282,7 @@
                                        (eq_attr "memory" "none,unknown"))))
                         "athlon-direct,athlon-ieu")
 (define_insn_reservation "athlon_ivector" 2
-                        (and (eq_attr "cpu" "athlon,k8,generic")
+                        (and (eq_attr "cpu" "athlon,k8")
                              (and (eq_attr "athlon_decode" "vector")
                                   (and (eq_attr "unit" "integer,unknown")
                                        (eq_attr "memory" "none,unknown"))))
@@ -295,13 +295,13 @@
                         "athlon-vector,athlon-ieu,athlon-ieu")
 
 (define_insn_reservation "athlon_idirect_loadmov" 3
-                        (and (eq_attr "cpu" "athlon,k8,generic,amdfam10")
+                        (and (eq_attr "cpu" "athlon,k8,amdfam10")
                              (and (eq_attr "type" "imov")
                                   (eq_attr "memory" "load")))
                         "athlon-direct,athlon-load")
 
 (define_insn_reservation "athlon_idirect_load" 4
-                        (and (eq_attr "cpu" "athlon,k8,generic")
+                        (and (eq_attr "cpu" "athlon,k8")
                              (and (eq_attr "athlon_decode" "direct")
                                   (and (eq_attr "unit" "integer,unknown")
                                        (eq_attr "memory" "load"))))
@@ -313,7 +313,7 @@
                                        (eq_attr "memory" "load"))))
                         "athlon-direct,athlon-load,athlon-ieu")
 (define_insn_reservation "athlon_ivector_load" 6
-                        (and (eq_attr "cpu" "athlon,k8,generic")
+                        (and (eq_attr "cpu" "athlon,k8")
                              (and (eq_attr "athlon_decode" "vector")
                                   (and (eq_attr "unit" "integer,unknown")
                                        (eq_attr "memory" "load"))))
@@ -326,13 +326,13 @@
                         "athlon-vector,athlon-load,athlon-ieu,athlon-ieu")
 
 (define_insn_reservation "athlon_idirect_movstore" 1
-                        (and (eq_attr "cpu" "athlon,k8,generic,amdfam10")
+                        (and (eq_attr "cpu" "athlon,k8,amdfam10")
                              (and (eq_attr "type" "imov")
                                   (eq_attr "memory" "store")))
                         "athlon-direct,athlon-agu,athlon-store")
 
 (define_insn_reservation "athlon_idirect_both" 4
-                        (and (eq_attr "cpu" "athlon,k8,generic")
+                        (and (eq_attr "cpu" "athlon,k8")
                              (and (eq_attr "athlon_decode" "direct")
                                   (and (eq_attr "unit" "integer,unknown")
                                        (eq_attr "memory" "both"))))
@@ -349,7 +349,7 @@
                          athlon-store")
 
 (define_insn_reservation "athlon_ivector_both" 6
-                        (and (eq_attr "cpu" "athlon,k8,generic")
+                        (and (eq_attr "cpu" "athlon,k8")
                              (and (eq_attr "athlon_decode" "vector")
                                   (and (eq_attr "unit" "integer,unknown")
                                        (eq_attr "memory" "both"))))
@@ -368,7 +368,7 @@
                          athlon-store")
 
 (define_insn_reservation "athlon_idirect_store" 1
-                        (and (eq_attr "cpu" "athlon,k8,generic")
+                        (and (eq_attr "cpu" "athlon,k8")
                              (and (eq_attr "athlon_decode" "direct")
                                   (and (eq_attr "unit" "integer,unknown")
                                        (eq_attr "memory" "store"))))
@@ -383,7 +383,7 @@
                          athlon-store")
 
 (define_insn_reservation "athlon_ivector_store" 2
-                        (and (eq_attr "cpu" "athlon,k8,generic")
+                        (and (eq_attr "cpu" "athlon,k8")
                              (and (eq_attr "athlon_decode" "vector")
                                   (and (eq_attr "unit" "integer,unknown")
                                        (eq_attr "memory" "store"))))
@@ -405,7 +405,7 @@
                                        (eq_attr "mode" "XF"))))
                         "athlon-vector,athlon-fpload2,athlon-fvector*9")
 (define_insn_reservation "athlon_fldxf_k8" 13
-                        (and (eq_attr "cpu" "k8,generic,amdfam10")
+                        (and (eq_attr "cpu" "k8,amdfam10")
                              (and (eq_attr "type" "fmov")
                                   (and (eq_attr "memory" "load")
                                        (eq_attr "mode" "XF"))))
@@ -417,7 +417,7 @@
                                   (eq_attr "memory" "load")))
                         "athlon-direct,athlon-fpload,athlon-fany")
 (define_insn_reservation "athlon_fld_k8" 2
-                        (and (eq_attr "cpu" "k8,generic,amdfam10")
+                        (and (eq_attr "cpu" "k8,amdfam10")
                              (and (eq_attr "type" "fmov")
                                   (eq_attr "memory" "load")))
                         "athlon-direct,athlon-fploadk8,athlon-fstore")
@@ -429,7 +429,7 @@
                                        (eq_attr "mode" "XF"))))
                         "athlon-vector,(athlon-fpsched+athlon-agu),(athlon-store2+(athlon-fvector*7))")
 (define_insn_reservation "athlon_fstxf_k8" 8
-                        (and (eq_attr "cpu" "k8,generic,amdfam10")
+                        (and (eq_attr "cpu" "k8,amdfam10")
                              (and (eq_attr "type" "fmov")
                                   (and (eq_attr "memory" "store,both")
                                        (eq_attr "mode" "XF"))))
@@ -440,16 +440,16 @@
                                   (eq_attr "memory" "store,both")))
                         "athlon-direct,(athlon-fpsched+athlon-agu),(athlon-fstore+athlon-store)")
 (define_insn_reservation "athlon_fst_k8" 2
-                        (and (eq_attr "cpu" "k8,generic,amdfam10")
+                        (and (eq_attr "cpu" "k8,amdfam10")
                              (and (eq_attr "type" "fmov")
                                   (eq_attr "memory" "store,both")))
                         "athlon-direct,(athlon-fpsched+athlon-agu),(athlon-fstore+athlon-store)")
 (define_insn_reservation "athlon_fist" 4
-                        (and (eq_attr "cpu" "athlon,k8,generic,amdfam10")
+                        (and (eq_attr "cpu" "athlon,k8,amdfam10")
                              (eq_attr "type" "fistp,fisttp"))
                         "athlon-direct,(athlon-fpsched+athlon-agu),(athlon-fstore+athlon-store)")
 (define_insn_reservation "athlon_fmov" 2
-                        (and (eq_attr "cpu" "athlon,k8,generic,amdfam10")
+                        (and (eq_attr "cpu" "athlon,k8,amdfam10")
                              (eq_attr "type" "fmov"))
                         "athlon-direct,athlon-fpsched,athlon-faddmul")
 (define_insn_reservation "athlon_fadd_load" 4
@@ -458,12 +458,12 @@
                                   (eq_attr "memory" "load")))
                         "athlon-direct,athlon-fpload,athlon-fadd")
 (define_insn_reservation "athlon_fadd_load_k8" 6
-                        (and (eq_attr "cpu" "k8,generic,amdfam10")
+                        (and (eq_attr "cpu" "k8,amdfam10")
                              (and (eq_attr "type" "fop")
                                   (eq_attr "memory" "load")))
                         "athlon-direct,athlon-fploadk8,athlon-fadd")
 (define_insn_reservation "athlon_fadd" 4
-                        (and (eq_attr "cpu" "athlon,k8,generic,amdfam10")
+                        (and (eq_attr "cpu" "athlon,k8,amdfam10")
                              (eq_attr "type" "fop"))
                         "athlon-direct,athlon-fpsched,athlon-fadd")
 (define_insn_reservation "athlon_fmul_load" 4
@@ -472,16 +472,16 @@
                                   (eq_attr "memory" "load")))
                         "athlon-direct,athlon-fpload,athlon-fmul")
 (define_insn_reservation "athlon_fmul_load_k8" 6
-                        (and (eq_attr "cpu" "k8,generic,amdfam10")
+                        (and (eq_attr "cpu" "k8,amdfam10")
                              (and (eq_attr "type" "fmul")
                                   (eq_attr "memory" "load")))
                         "athlon-direct,athlon-fploadk8,athlon-fmul")
 (define_insn_reservation "athlon_fmul" 4
-                        (and (eq_attr "cpu" "athlon,k8,generic,amdfam10")
+                        (and (eq_attr "cpu" "athlon,k8,amdfam10")
                              (eq_attr "type" "fmul"))
                         "athlon-direct,athlon-fpsched,athlon-fmul")
 (define_insn_reservation "athlon_fsgn" 2
-                        (and (eq_attr "cpu" "athlon,k8,generic,amdfam10")
+                        (and (eq_attr "cpu" "athlon,k8,amdfam10")
                              (eq_attr "type" "fsgn"))
                         "athlon-direct,athlon-fpsched,athlon-fmul")
 (define_insn_reservation "athlon_fdiv_load" 24
@@ -490,7 +490,7 @@
                                   (eq_attr "memory" "load")))
                         "athlon-direct,athlon-fpload,athlon-fmul")
 (define_insn_reservation "athlon_fdiv_load_k8" 13
-                        (and (eq_attr "cpu" "k8,generic,amdfam10")
+                        (and (eq_attr "cpu" "k8,amdfam10")
                              (and (eq_attr "type" "fdiv")
                                   (eq_attr "memory" "load")))
                         "athlon-direct,athlon-fploadk8,athlon-fmul")
@@ -499,16 +499,16 @@
                              (eq_attr "type" "fdiv"))
                         "athlon-direct,athlon-fpsched,athlon-fmul")
 (define_insn_reservation "athlon_fdiv_k8" 11
-                        (and (eq_attr "cpu" "k8,generic,amdfam10")
+                        (and (eq_attr "cpu" "k8,amdfam10")
                              (eq_attr "type" "fdiv"))
                         "athlon-direct,athlon-fpsched,athlon-fmul")
 (define_insn_reservation "athlon_fpspc_load" 103
-                        (and (eq_attr "cpu" "athlon,k8,generic,amdfam10")
+                        (and (eq_attr "cpu" "athlon,k8,amdfam10")
                              (and (eq_attr "type" "fpspc")
                                   (eq_attr "memory" "load")))
                         "athlon-vector,athlon-fpload,athlon-fvector")
 (define_insn_reservation "athlon_fpspc" 100
-                        (and (eq_attr "cpu" "athlon,k8,generic,amdfam10")
+                        (and (eq_attr "cpu" "athlon,k8,amdfam10")
                              (eq_attr "type" "fpspc"))
                         "athlon-vector,athlon-fpsched,athlon-fvector")
 (define_insn_reservation "athlon_fcmov_load" 7
@@ -521,12 +521,12 @@
                              (eq_attr "type" "fcmov"))
                         "athlon-vector,athlon-fpsched,athlon-fvector")
 (define_insn_reservation "athlon_fcmov_load_k8" 17
-                        (and (eq_attr "cpu" "k8,generic,amdfam10")
+                        (and (eq_attr "cpu" "k8,amdfam10")
                              (and (eq_attr "type" "fcmov")
                                   (eq_attr "memory" "load")))
                         "athlon-vector,athlon-fploadk8,athlon-fvector")
 (define_insn_reservation "athlon_fcmov_k8" 15
-                        (and (eq_attr "cpu" "k8,generic,amdfam10")
+                        (and (eq_attr "cpu" "k8,amdfam10")
                              (eq_attr "type" "fcmov"))
                         "athlon-vector,athlon-fpsched,athlon-fvector")
 ;; fcomi is vector decoded by uses only one pipe.
@@ -537,13 +537,13 @@
                                        (eq_attr "memory" "load"))))
                         "athlon-vector,athlon-fpload,athlon-fadd")
 (define_insn_reservation "athlon_fcomi_load_k8" 5
-                        (and (eq_attr "cpu" "k8,generic,amdfam10")
+                        (and (eq_attr "cpu" "k8,amdfam10")
                              (and (eq_attr "type" "fcmp")
                                   (and (eq_attr "athlon_decode" "vector")
                                        (eq_attr "memory" "load"))))
                         "athlon-vector,athlon-fploadk8,athlon-fadd")
 (define_insn_reservation "athlon_fcomi" 3
-                        (and (eq_attr "cpu" "athlon,k8,generic,amdfam10")
+                        (and (eq_attr "cpu" "athlon,k8,amdfam10")
                              (and (eq_attr "athlon_decode" "vector")
                                   (eq_attr "type" "fcmp")))
                         "athlon-vector,athlon-fpsched,athlon-fadd")
@@ -553,18 +553,18 @@
                                   (eq_attr "memory" "load")))
                         "athlon-direct,athlon-fpload,athlon-fadd")
 (define_insn_reservation "athlon_fcom_load_k8" 4
-                        (and (eq_attr "cpu" "k8,generic,amdfam10")
+                        (and (eq_attr "cpu" "k8,amdfam10")
                              (and (eq_attr "type" "fcmp")
                                   (eq_attr "memory" "load")))
                         "athlon-direct,athlon-fploadk8,athlon-fadd")
 (define_insn_reservation "athlon_fcom" 2
-                        (and (eq_attr "cpu" "athlon,k8,generic,amdfam10")
+                        (and (eq_attr "cpu" "athlon,k8,amdfam10")
                              (eq_attr "type" "fcmp"))
                         "athlon-direct,athlon-fpsched,athlon-fadd")
 ;; Never seen by the scheduler because we still don't do post reg-stack
 ;; scheduling.
 ;(define_insn_reservation "athlon_fxch" 2
-;                       (and (eq_attr "cpu" "athlon,k8,generic,amdfam10")
+;                       (and (eq_attr "cpu" "athlon,k8,amdfam10")
 ;                            (eq_attr "type" "fxch"))
 ;                       "athlon-direct,athlon-fpsched,athlon-fany")
 
@@ -580,13 +580,8 @@
                              (and (eq_attr "type" "ssemov")
                                   (match_operand:DF 1 "memory_operand")))
                         "athlon-direct,athlon-fploadk8,athlon-fstore")
-(define_insn_reservation "athlon_movsd_load_generic" 2
-                        (and (eq_attr "cpu" "generic")
-                             (and (eq_attr "type" "ssemov")
-                                  (match_operand:DF 1 "memory_operand")))
-                        "athlon-double,athlon-fploadk8,(athlon-fstore+athlon-fmul)")
 (define_insn_reservation "athlon_movaps_load_k8" 2
-                        (and (eq_attr "cpu" "k8,generic")
+                        (and (eq_attr "cpu" "k8")
                              (and (eq_attr "type" "ssemov")
                                   (and (eq_attr "mode" "V4SF,V2DF,TI")
                                        (eq_attr "memory" "load"))))
@@ -604,7 +599,7 @@
                                        (eq_attr "memory" "load"))))
                         "athlon-vector,athlon-fpload,(athlon-fany*2)")
 (define_insn_reservation "athlon_movss_load_k8" 1
-                        (and (eq_attr "cpu" "k8,generic")
+                        (and (eq_attr "cpu" "k8")
                              (and (eq_attr "type" "ssemov")
                                   (and (eq_attr "mode" "SF,DI")
                                        (eq_attr "memory" "load"))))
@@ -615,7 +610,7 @@
                                   (eq_attr "memory" "load")))
                         "athlon-direct,athlon-fpload,athlon-fany")
 (define_insn_reservation "athlon_mmxsseld_k8" 2
-                        (and (eq_attr "cpu" "k8,generic")
+                        (and (eq_attr "cpu" "k8")
                              (and (eq_attr "type" "mmxmov,ssemov")
                                   (eq_attr "memory" "load")))
                         "athlon-direct,athlon-fploadk8,athlon-fstore")
@@ -637,19 +632,19 @@
                                   (eq_attr "memory" "load")))
                         "athlon-direct,athlon-fploadk8, athlon-fany")
 (define_insn_reservation "athlon_mmxssest" 3
-                        (and (eq_attr "cpu" "k8,generic")
+                        (and (eq_attr "cpu" "k8")
                              (and (eq_attr "type" "mmxmov,ssemov")
                                   (and (eq_attr "mode" "V4SF,V2DF,TI")
                                        (eq_attr "memory" "store,both"))))
                         "athlon-vector,(athlon-fpsched+athlon-agu),((athlon-fstore+athlon-store2)*2)")
 (define_insn_reservation "athlon_mmxssest_k8" 3
-                        (and (eq_attr "cpu" "k8,generic")
+                        (and (eq_attr "cpu" "k8")
                              (and (eq_attr "type" "mmxmov,ssemov")
                                   (and (eq_attr "mode" "V4SF,V2DF,TI")
                                        (eq_attr "memory" "store,both"))))
                         "athlon-double,(athlon-fpsched+athlon-agu),((athlon-fstore+athlon-store2)*2)")
 (define_insn_reservation "athlon_mmxssest_short" 2
-                        (and (eq_attr "cpu" "athlon,k8,generic")
+                        (and (eq_attr "cpu" "athlon,k8")
                              (and (eq_attr "type" "mmxmov,ssemov")
                                   (eq_attr "memory" "store,both")))
                         "athlon-direct,(athlon-fpsched+athlon-agu),(athlon-fstore+athlon-store)")
@@ -673,7 +668,7 @@
                                   (eq_attr "memory" "store,both")))
                         "athlon-direct,(athlon-fpsched+athlon-agu),(athlon-fstore+athlon-store)")
 (define_insn_reservation "athlon_movaps_k8" 2
-                        (and (eq_attr "cpu" "k8,generic")
+                        (and (eq_attr "cpu" "k8")
                              (and (eq_attr "type" "ssemov")
                                   (eq_attr "mode" "V4SF,V2DF,TI")))
                         "athlon-double,athlon-fpsched,((athlon-faddmul+athlon-faddmul) | (athlon-faddmul, athlon-faddmul))")
@@ -683,25 +678,25 @@
                                   (eq_attr "mode" "V4SF,V2DF,TI")))
                         "athlon-vector,athlon-fpsched,(athlon-faddmul+athlon-faddmul)")
 (define_insn_reservation "athlon_mmxssemov" 2
-                        (and (eq_attr "cpu" "athlon,k8,generic")
+                        (and (eq_attr "cpu" "athlon,k8")
                              (eq_attr "type" "mmxmov,ssemov"))
                         "athlon-direct,athlon-fpsched,athlon-faddmul")
 (define_insn_reservation "athlon_mmxmul_load" 4
-                        (and (eq_attr "cpu" "athlon,k8,generic")
+                        (and (eq_attr "cpu" "athlon,k8")
                              (and (eq_attr "type" "mmxmul")
                                   (eq_attr "memory" "load")))
                         "athlon-direct,athlon-fpload,athlon-fmul")
 (define_insn_reservation "athlon_mmxmul" 3
-                        (and (eq_attr "cpu" "athlon,k8,generic")
+                        (and (eq_attr "cpu" "athlon,k8")
                              (eq_attr "type" "mmxmul"))
                         "athlon-direct,athlon-fpsched,athlon-fmul")
 (define_insn_reservation "athlon_mmx_load" 3
-                        (and (eq_attr "cpu" "athlon,k8,generic")
+                        (and (eq_attr "cpu" "athlon,k8")
                              (and (eq_attr "unit" "mmx")
                                   (eq_attr "memory" "load")))
                         "athlon-direct,athlon-fpload,athlon-faddmul")
 (define_insn_reservation "athlon_mmx" 2
-                        (and (eq_attr "cpu" "athlon,k8,generic")
+                        (and (eq_attr "cpu" "athlon,k8")
                              (eq_attr "unit" "mmx"))
                         "athlon-direct,athlon-fpsched,athlon-faddmul")
 ;; SSE operations are handled by the i387 unit as well.  The latency
@@ -713,7 +708,7 @@
                                   (eq_attr "memory" "load")))
                         "athlon-vector,athlon-fpload2,(athlon-fmul*2)")
 (define_insn_reservation "athlon_sselog_load_k8" 5
-                        (and (eq_attr "cpu" "k8,generic")
+                        (and (eq_attr "cpu" "k8")
                              (and (eq_attr "type" "sselog,sselog1,sseshuf,sseshuf1")
                                   (eq_attr "memory" "load")))
                         "athlon-double,athlon-fpload2k8,(athlon-fmul*2)")
@@ -727,7 +722,7 @@
                              (eq_attr "type" "sselog,sselog1,sseshuf,sseshuf1"))
                         "athlon-vector,athlon-fpsched,athlon-fmul*2")
 (define_insn_reservation "athlon_sselog_k8" 3
-                        (and (eq_attr "cpu" "k8,generic")
+                        (and (eq_attr "cpu" "k8")
                              (eq_attr "type" "sselog,sselog1,sseshuf,sseshuf1"))
                         "athlon-double,athlon-fpsched,athlon-fmul")
 (define_insn_reservation "athlon_sselog_amdfam10" 2
@@ -743,13 +738,13 @@
                                        (eq_attr "memory" "load"))))
                         "athlon-direct,athlon-fpload,athlon-fadd")
 (define_insn_reservation "athlon_ssecmp_load_k8" 4
-                        (and (eq_attr "cpu" "k8,generic,amdfam10")
+                        (and (eq_attr "cpu" "k8,amdfam10")
                              (and (eq_attr "type" "ssecmp")
                                   (and (eq_attr "mode" "SF,DF,DI,TI")
                                        (eq_attr "memory" "load"))))
                         "athlon-direct,athlon-fploadk8,athlon-fadd")
 (define_insn_reservation "athlon_ssecmp" 2
-                        (and (eq_attr "cpu" "athlon,k8,generic,amdfam10")
+                        (and (eq_attr "cpu" "athlon,k8,amdfam10")
                              (and (eq_attr "type" "ssecmp")
                                   (eq_attr "mode" "SF,DF,DI,TI")))
                         "athlon-direct,athlon-fpsched,athlon-fadd")
@@ -759,7 +754,7 @@
                                   (eq_attr "memory" "load")))
                         "athlon-vector,athlon-fpload2,(athlon-fadd*2)")
 (define_insn_reservation "athlon_ssecmpvector_load_k8" 5
-                        (and (eq_attr "cpu" "k8,generic")
+                        (and (eq_attr "cpu" "k8")
                              (and (eq_attr "type" "ssecmp")
                                   (eq_attr "memory" "load")))
                         "athlon-double,athlon-fpload2k8,(athlon-fadd*2)")
@@ -773,7 +768,7 @@
                              (eq_attr "type" "ssecmp"))
                         "athlon-vector,athlon-fpsched,(athlon-fadd*2)")
 (define_insn_reservation "athlon_ssecmpvector_k8" 3
-                        (and (eq_attr "cpu" "k8,generic")
+                        (and (eq_attr "cpu" "k8")
                              (eq_attr "type" "ssecmp"))
                         "athlon-double,athlon-fpsched,(athlon-fadd*2)")
 (define_insn_reservation "athlon_ssecmpvector_amdfam10" 2
@@ -786,7 +781,7 @@
                                   (eq_attr "memory" "load")))
                         "athlon-vector,athlon-fpload,athlon-fadd")
 (define_insn_reservation "athlon_ssecomi_load_k8" 6
-                        (and (eq_attr "cpu" "k8,generic")
+                        (and (eq_attr "cpu" "k8")
                              (and (eq_attr "type" "ssecomi")
                                   (eq_attr "memory" "load")))
                         "athlon-vector,athlon-fploadk8,athlon-fadd")
@@ -796,7 +791,7 @@
                                   (eq_attr "memory" "load")))
                         "athlon-direct,athlon-fploadk8,athlon-fadd")
 (define_insn_reservation "athlon_ssecomi" 4
-                        (and (eq_attr "cpu" "athlon,k8,generic")
+                        (and (eq_attr "cpu" "athlon,k8")
                              (eq_attr "type" "ssecomi"))
                         "athlon-vector,athlon-fpsched,athlon-fadd")
 (define_insn_reservation "athlon_ssecomi_amdfam10" 3
@@ -811,13 +806,13 @@
                                        (eq_attr "memory" "load"))))
                         "athlon-direct,athlon-fpload,athlon-fadd")
 (define_insn_reservation "athlon_sseadd_load_k8" 6
-                        (and (eq_attr "cpu" "k8,generic,amdfam10")
+                        (and (eq_attr "cpu" "k8,amdfam10")
                              (and (eq_attr "type" "sseadd,sseadd1")
                                   (and (eq_attr "mode" "SF,DF,DI")
                                        (eq_attr "memory" "load"))))
                         "athlon-direct,athlon-fploadk8,athlon-fadd")
 (define_insn_reservation "athlon_sseadd" 4
-                        (and (eq_attr "cpu" "athlon,k8,generic,amdfam10")
+                        (and (eq_attr "cpu" "athlon,k8,amdfam10")
                              (and (eq_attr "type" "sseadd,sseadd1")
                                   (eq_attr "mode" "SF,DF,DI")))
                         "athlon-direct,athlon-fpsched,athlon-fadd")
@@ -827,7 +822,7 @@
                                   (eq_attr "memory" "load")))
                         "athlon-vector,athlon-fpload2,(athlon-fadd*2)")
 (define_insn_reservation "athlon_sseaddvector_load_k8" 7
-                        (and (eq_attr "cpu" "k8,generic")
+                        (and (eq_attr "cpu" "k8")
                              (and (eq_attr "type" "sseadd,sseadd1")
                                   (eq_attr "memory" "load")))
                         "athlon-double,athlon-fpload2k8,(athlon-fadd*2)")
@@ -841,7 +836,7 @@
                              (eq_attr "type" "sseadd,sseadd1"))
                         "athlon-vector,athlon-fpsched,(athlon-fadd*2)")
 (define_insn_reservation "athlon_sseaddvector_k8" 5
-                        (and (eq_attr "cpu" "k8,generic")
+                        (and (eq_attr "cpu" "k8")
                              (eq_attr "type" "sseadd,sseadd1"))
                         "athlon-double,athlon-fpsched,(athlon-fadd*2)")
 (define_insn_reservation "athlon_sseaddvector_amdfam10" 4
@@ -855,7 +850,7 @@
 
 ;; cvtss2sd
 (define_insn_reservation "athlon_ssecvt_cvtss2sd_load_k8" 4
-                        (and (eq_attr "cpu" "k8,athlon,generic")
+                        (and (eq_attr "cpu" "k8,athlon")
                              (and (eq_attr "type" "ssecvt")
                                   (and (eq_attr "athlon_decode" "direct")
                                        (and (eq_attr "mode" "DF")
@@ -869,7 +864,7 @@
                                             (eq_attr "memory" "load")))))
                         "athlon-double,athlon-fploadk8,(athlon-faddmul+athlon-fstore)")
 (define_insn_reservation "athlon_ssecvt_cvtss2sd" 2
-                        (and (eq_attr "cpu" "athlon,k8,generic")
+                        (and (eq_attr "cpu" "athlon,k8")
                              (and (eq_attr "type" "ssecvt")
                                   (and (eq_attr "athlon_decode" "direct")
                                        (eq_attr "mode" "DF"))))
@@ -882,7 +877,7 @@
                         "athlon-vector,athlon-fpsched,athlon-faddmul,(athlon-fstore*2)")
 ;; cvtps2pd.  Model same way the other double decoded FP conversions.
 (define_insn_reservation "athlon_ssecvt_cvtps2pd_load_k8" 5
-                        (and (eq_attr "cpu" "k8,athlon,generic")
+                        (and (eq_attr "cpu" "k8,athlon")
                              (and (eq_attr "type" "ssecvt")
                                   (and (eq_attr "athlon_decode" "double")
                                        (and (eq_attr "mode" "V2DF,V4SF,TI")
@@ -896,7 +891,7 @@
                                             (eq_attr "memory" "load")))))
                         "athlon-direct,athlon-fploadk8,athlon-fstore")
 (define_insn_reservation "athlon_ssecvt_cvtps2pd_k8" 3
-                        (and (eq_attr "cpu" "k8,athlon,generic")
+                        (and (eq_attr "cpu" "k8,athlon")
                              (and (eq_attr "type" "ssecvt")
                                   (and (eq_attr "athlon_decode" "double")
                                        (eq_attr "mode" "V2DF,V4SF,TI"))))
@@ -932,7 +927,7 @@
                                             (eq_attr "memory" "load")))))
                         "athlon-vector,athlon-fpload,(athlon-fstore*2)")
 (define_insn_reservation "athlon_sseicvt_cvtsi2ss_load_k8" 9
-                        (and (eq_attr "cpu" "k8,generic")
+                        (and (eq_attr "cpu" "k8")
                              (and (eq_attr "type" "sseicvt")
                                   (and (eq_attr "athlon_decode" "double")
                                        (and (eq_attr "mode" "SF,DF")
@@ -947,7 +942,7 @@
                         "athlon-double,athlon-fploadk8,(athlon-faddmul+athlon-fstore)")
 ;; cvtsi2sd reg,reg is double decoded (vector on Athlon)
 (define_insn_reservation "athlon_sseicvt_cvtsi2sd_k8" 11
-                        (and (eq_attr "cpu" "k8,athlon,generic")
+                        (and (eq_attr "cpu" "k8,athlon")
                              (and (eq_attr "type" "sseicvt")
                                   (and (eq_attr "athlon_decode" "double")
                                        (and (eq_attr "mode" "SF,DF")
@@ -962,7 +957,7 @@
                         "athlon-vector,athlon-fploadk8,(athlon-faddmul+athlon-fstore)")
 ;; cvtsi2ss reg, reg is doublepath
 (define_insn_reservation "athlon_sseicvt_cvtsi2ss" 14
-                        (and (eq_attr "cpu" "athlon,k8,generic")
+                        (and (eq_attr "cpu" "athlon,k8")
                              (and (eq_attr "type" "sseicvt")
                                   (and (eq_attr "athlon_decode" "vector")
                                        (and (eq_attr "mode" "SF,DF")
@@ -977,7 +972,7 @@
                         "athlon-vector,athlon-fploadk8,(athlon-faddmul+athlon-fstore)")
 ;; cvtsd2ss mem,reg is doublepath, troughput unknown, latency 9
 (define_insn_reservation "athlon_ssecvt_cvtsd2ss_load_k8" 9
-                        (and (eq_attr "cpu" "k8,athlon,generic")
+                        (and (eq_attr "cpu" "k8,athlon")
                              (and (eq_attr "type" "ssecvt")
                                   (and (eq_attr "athlon_decode" "double")
                                        (and (eq_attr "mode" "SF")
@@ -992,7 +987,7 @@
                         "athlon-double,athlon-fploadk8,(athlon-faddmul+athlon-fstore)")
 ;; cvtsd2ss reg,reg is vectorpath, troughput unknown, latency 12
 (define_insn_reservation "athlon_ssecvt_cvtsd2ss" 12
-                        (and (eq_attr "cpu" "athlon,k8,generic")
+                        (and (eq_attr "cpu" "athlon,k8")
                              (and (eq_attr "type" "ssecvt")
                                   (and (eq_attr "athlon_decode" "vector")
                                        (and (eq_attr "mode" "SF")
@@ -1006,7 +1001,7 @@
                                             (eq_attr "memory" "none")))))
                         "athlon-vector,athlon-fpsched,athlon-faddmul,(athlon-fstore*2)")
 (define_insn_reservation "athlon_ssecvt_cvtpd2ps_load_k8" 8
-                        (and (eq_attr "cpu" "athlon,k8,generic")
+                        (and (eq_attr "cpu" "athlon,k8")
                              (and (eq_attr "type" "ssecvt")
                                   (and (eq_attr "athlon_decode" "vector")
                                        (and (eq_attr "mode" "V4SF,V2DF,TI")
@@ -1022,7 +1017,7 @@
 ;; cvtpd2ps mem,reg is vectorpath, troughput unknown, latency 10
 ;; ??? Why it is fater than cvtsd2ss?
 (define_insn_reservation "athlon_ssecvt_cvtpd2ps" 8
-                        (and (eq_attr "cpu" "athlon,k8,generic")
+                        (and (eq_attr "cpu" "athlon,k8")
                              (and (eq_attr "type" "ssecvt")
                                   (and (eq_attr "athlon_decode" "vector")
                                        (and (eq_attr "mode" "V4SF,V2DF,TI")
@@ -1037,7 +1032,7 @@
                         "athlon-double,athlon-fpsched,(athlon-faddmul+athlon-fstore)")
 ;; cvtsd2si mem,reg is doublepath, troughput 1, latency 9
 (define_insn_reservation "athlon_secvt_cvtsX2si_load" 9
-                        (and (eq_attr "cpu" "athlon,k8,generic")
+                        (and (eq_attr "cpu" "athlon,k8")
                              (and (eq_attr "type" "sseicvt")
                                   (and (eq_attr "athlon_decode" "vector")
                                        (and (eq_attr "mode" "SI,DI")
@@ -1059,7 +1054,7 @@
                                             (eq_attr "memory" "none")))))
                         "athlon-vector,athlon-fpsched,athlon-fvector")
 (define_insn_reservation "athlon_ssecvt_cvtsX2si_k8" 9
-                        (and (eq_attr "cpu" "k8,generic")
+                        (and (eq_attr "cpu" "k8")
                              (and (eq_attr "type" "sseicvt")
                                   (and (eq_attr "athlon_decode" "double")
                                        (and (eq_attr "mode" "SI,DI")
@@ -1097,13 +1092,13 @@
                                        (eq_attr "memory" "load"))))
                         "athlon-direct,athlon-fpload,athlon-fmul")
 (define_insn_reservation "athlon_ssemul_load_k8" 6
-                        (and (eq_attr "cpu" "k8,generic,amdfam10")
+                        (and (eq_attr "cpu" "k8,amdfam10")
                              (and (eq_attr "type" "ssemul")
                                   (and (eq_attr "mode" "SF,DF")
                                        (eq_attr "memory" "load"))))
                         "athlon-direct,athlon-fploadk8,athlon-fmul")
 (define_insn_reservation "athlon_ssemul" 4
-                        (and (eq_attr "cpu" "athlon,k8,generic,amdfam10")
+                        (and (eq_attr "cpu" "athlon,k8,amdfam10")
                              (and (eq_attr "type" "ssemul")
                                   (eq_attr "mode" "SF,DF")))
                         "athlon-direct,athlon-fpsched,athlon-fmul")
@@ -1113,7 +1108,7 @@
                                   (eq_attr "memory" "load")))
                         "athlon-vector,athlon-fpload2,(athlon-fmul*2)")
 (define_insn_reservation "athlon_ssemulvector_load_k8" 7
-                        (and (eq_attr "cpu" "k8,generic")
+                        (and (eq_attr "cpu" "k8")
                              (and (eq_attr "type" "ssemul")
                                   (eq_attr "memory" "load")))
                         "athlon-double,athlon-fpload2k8,(athlon-fmul*2)")
@@ -1127,7 +1122,7 @@
                              (eq_attr "type" "ssemul"))
                         "athlon-vector,athlon-fpsched,(athlon-fmul*2)")
 (define_insn_reservation "athlon_ssemulvector_k8" 5
-                        (and (eq_attr "cpu" "k8,generic")
+                        (and (eq_attr "cpu" "k8")
                              (eq_attr "type" "ssemul"))
                         "athlon-double,athlon-fpsched,(athlon-fmul*2)")
 (define_insn_reservation "athlon_ssemulvector_amdfam10" 4
@@ -1142,13 +1137,13 @@
                                        (eq_attr "memory" "load"))))
                         "athlon-direct,athlon-fpload,athlon-fmul*17")
 (define_insn_reservation "athlon_ssediv_load_k8" 22
-                        (and (eq_attr "cpu" "k8,generic,amdfam10")
+                        (and (eq_attr "cpu" "k8,amdfam10")
                              (and (eq_attr "type" "ssediv")
                                   (and (eq_attr "mode" "SF,DF")
                                        (eq_attr "memory" "load"))))
                         "athlon-direct,athlon-fploadk8,athlon-fmul*17")
 (define_insn_reservation "athlon_ssediv" 20
-                        (and (eq_attr "cpu" "athlon,k8,generic,amdfam10")
+                        (and (eq_attr "cpu" "athlon,k8,amdfam10")
                              (and (eq_attr "type" "ssediv")
                                   (eq_attr "mode" "SF,DF")))
                         "athlon-direct,athlon-fpsched,athlon-fmul*17")
@@ -1158,7 +1153,7 @@
                                   (eq_attr "memory" "load")))
                         "athlon-vector,athlon-fpload2,athlon-fmul*34")
 (define_insn_reservation "athlon_ssedivvector_load_k8" 35
-                        (and (eq_attr "cpu" "k8,generic")
+                        (and (eq_attr "cpu" "k8")
                              (and (eq_attr "type" "ssediv")
                                   (eq_attr "memory" "load")))
                         "athlon-double,athlon-fpload2k8,athlon-fmul*34")
@@ -1172,7 +1167,7 @@
                              (eq_attr "type" "ssediv"))
                         "athlon-vector,athlon-fmul*34")
 (define_insn_reservation "athlon_ssedivvector_k8" 39
-                        (and (eq_attr "cpu" "k8,generic")
+                        (and (eq_attr "cpu" "k8")
                              (eq_attr "type" "ssediv"))
                         "athlon-double,athlon-fmul*34")
 (define_insn_reservation "athlon_ssedivvector_amdfam10" 20

diff --git a/gcc/config/i386/haswell.md b/gcc/config/i386/haswell.md
index f59b2efaf497d52cd020fd4422823209c7c845ea..82e110294a6a0b7f7e37e5c85fa1c28df45d97e7 100644 (file)
--- a/gcc/config/i386/haswell.md
+++ b/gcc/config/i386/haswell.md
@@ -74,12 +74,12 @@
 (define_reservation "hsw_p01" "hsw_p0|hsw_p1")
 
 (define_insn_reservation "hsw_complex_insn" 6
-                        (and (eq_attr "cpu" "haswell")
+                        (and (eq_attr "cpu" "generic,haswell")
                              (eq_attr "type" "other,multi,str"))
                         "hsw_decoder0")
 
 (define_insn_reservation "hsw_call" 1
-                        (and (eq_attr "cpu" "haswell")
+                        (and (eq_attr "cpu" "generic,haswell")
                              (eq_attr "type" "call,callv"))
                         "hsw_decoder0")
 
@@ -87,104 +87,104 @@
 ;; imovx always decodes to one uop, and also doesn't use the integer
 ;; units if it has memory operands.
 (define_insn_reservation "hsw_imov" 1
-                        (and (eq_attr "cpu" "haswell")
+                        (and (eq_attr "cpu" "generic,haswell")
                              (and (eq_attr "memory" "none")
                                   (eq_attr "type" "imov,imovx")))
                         "hsw_decodern,hsw_p0156")
 
 (define_insn_reservation "hsw_imov_load" 2
-                        (and (eq_attr "cpu" "haswell")
+                        (and (eq_attr "cpu" "generic,haswell")
                              (and (eq_attr "memory" "load")
                                   (eq_attr "type" "imov,imovx")))
                         "hsw_decodern,hsw_p23")
 
 (define_insn_reservation "hsw_imov_store" 3
-                        (and (eq_attr "cpu" "haswell")
+                        (and (eq_attr "cpu" "generic,haswell")
                              (and (eq_attr "memory" "store")
                                   (eq_attr "type" "imov")))
                         "hsw_decodern,hsw_p4+(hsw_p2|hsw_p3|hsw_p7)")
 
 (define_insn_reservation "hsw_icmov" 2
-                        (and (eq_attr "cpu" "haswell")
+                        (and (eq_attr "cpu" "generic,haswell")
                              (and (eq_attr "memory" "none")
                                   (eq_attr "type" "icmov")))
                         "hsw_decodern,hsw_p0156,hsw_p0156")
 
 (define_insn_reservation "hsw_icmov_load" 2
-                        (and (eq_attr "cpu" "haswell")
+                        (and (eq_attr "cpu" "generic,haswell")
                              (and (eq_attr "memory" "load")
                                   (eq_attr "type" "icmov")))
                         "hsw_decodern,hsw_p23+hsw_p0156,hsw_p0156")
 
 (define_insn_reservation "hsw_push_reg" 3
-                        (and (eq_attr "cpu" "haswell")
+                        (and (eq_attr "cpu" "generic,haswell")
                              (and (eq_attr "memory" "store")
                                   (eq_attr "type" "push")))
                         "hsw_decodern,hsw_p4+hsw_p237")
 
 (define_insn_reservation "hsw_push_mem" 3
-                        (and (eq_attr "cpu" "haswell")
+                        (and (eq_attr "cpu" "generic,haswell")
                              (and (eq_attr "memory" "both")
                                   (eq_attr "type" "push")))
                         "hsw_decodern,hsw_p4+hsw_p237,hsw_p237")
 
 ;; Consider lea latency as having 2 components.
 (define_insn_reservation "hsw_lea" 1
-                        (and (eq_attr "cpu" "haswell")
+                        (and (eq_attr "cpu" "generic,haswell")
                              (and (eq_attr "memory" "none")
                                   (eq_attr "type" "lea")))
                         "hsw_decodern,hsw_p1|hsw_p5")
 
 (define_insn_reservation "hsw_shift_rotate" 1
-                        (and (eq_attr "cpu" "haswell")
+                        (and (eq_attr "cpu" "generic,haswell")
                              (and (eq_attr "memory" "none")
                                   (eq_attr "type" "ishift,ishift1,rotate,rotate1")))
                         "hsw_decodern,hsw_p0|hsw_p6")
 
 (define_insn_reservation "hsw_shift_rotate_mem" 1
-                        (and (eq_attr "cpu" "haswell")
+                        (and (eq_attr "cpu" "generic,haswell")
                              (and (eq_attr "memory" "!none")
                                   (eq_attr "type" "ishift,ishift1,rotate,rotate1")))
                         "hsw_decodern,(hsw_p0|hsw_p6)+hsw_p237+hsw_p4")
 
 (define_insn_reservation "hsw_branch" 1
-                        (and (eq_attr "cpu" "haswell")
+                        (and (eq_attr "cpu" "generic,haswell")
                              (and (eq_attr "memory" "none")
                                   (eq_attr "type" "ibr")))
                         "hsw_decodern,hsw_p6")
 
 (define_insn_reservation "hsw_indirect_branch" 2
-                        (and (eq_attr "cpu" "haswell")
+                        (and (eq_attr "cpu" "generic,haswell")
                              (and (eq_attr "memory" "!none")
                                   (eq_attr "type" "ibr")))
                         "hsw_decoder0,hsw_p23+hsw_p6")
 
 (define_insn_reservation "hsw_leave" 4
-                        (and (eq_attr "cpu" "haswell")
+                        (and (eq_attr "cpu" "generic,haswell")
                              (eq_attr "type" "leave"))
                         "hsw_decoder0,hsw_p23+hsw_p0156,hsw_p0156")
 
 ;; imul and imulx with two/three operands only execute on port 1.
 (define_insn_reservation "hsw_imul" 3
-                        (and (eq_attr "cpu" "haswell")
+                        (and (eq_attr "cpu" "generic,haswell")
                              (and (eq_attr "memory" "none")
                                   (eq_attr "type" "imul")))
                         "hsw_decodern,hsw_p1")
 
 (define_insn_reservation "hsw_imul_mem" 3
-                        (and (eq_attr "cpu" "haswell")
+                        (and (eq_attr "cpu" "generic,haswell")
                              (and (eq_attr "memory" "!none")
                                   (eq_attr "type" "imul")))
                         "hsw_decodern,hsw_p23+hsw_p1")
 
 (define_insn_reservation "hsw_imulx" 4
-                        (and (eq_attr "cpu" "haswell")
+                        (and (eq_attr "cpu" "generic,haswell")
                              (and (eq_attr "memory" "none")
                                   (eq_attr "type" "imulx")))
                         "hsw_decodern,hsw_p0156,hsw_p0156")
 
 (define_insn_reservation "hsw_imulx_mem" 4
-                        (and (eq_attr "cpu" "haswell")
+                        (and (eq_attr "cpu" "generic,haswell")
                              (and (eq_attr "memory" "!none")
                                   (eq_attr "type" "imulx")))
                         "hsw_decodern,hsw_p23+hsw_p0156,(hsw_p0|hsw_p6|hsw_p6)")
@@ -193,13 +193,13 @@
 ;; div and idiv are very similar, so we model them the same.
 ;; Use the same latency for all QI,HI and SI modes.
 (define_insn_reservation "hsw_idiv" 23
-                        (and (eq_attr "cpu" "haswell")
+                        (and (eq_attr "cpu" "generic,haswell")
                              (and (eq_attr "memory" "none")
                                   (eq_attr "type" "idiv")))
                         "hsw_decoder0,(hsw_p0p1p5p6+hsw_idiv)*9")
 
 (define_insn_reservation "hsw_idiv_load" 23
-                        (and (eq_attr "cpu" "haswell")
+                        (and (eq_attr "cpu" "generic,haswell")
                              (and (eq_attr "memory" "load")
                                        (eq_attr "type" "idiv")))
                         "hsw_decoder0,hsw_p23+hsw_p0+hsw_idiv,(hsw_p0p1p5p6+hsw_idiv)*9")
@@ -207,103 +207,103 @@
 ;; x87 floating point operations.
 
 (define_insn_reservation "hsw_fxch" 0
-                        (and (eq_attr "cpu" "haswell")
+                        (and (eq_attr "cpu" "generic,haswell")
                              (eq_attr "type" "fxch"))
                         "hsw_decodern")
 
 (define_insn_reservation "hsw_fop" 3
-                        (and (eq_attr "cpu" "haswell")
+                        (and (eq_attr "cpu" "generic,haswell")
                              (and (eq_attr "memory" "none,unknown")
                                   (eq_attr "type" "fop")))
                         "hsw_decodern,hsw_p1")
 
 (define_insn_reservation "hsw_fop_load" 5
-                        (and (eq_attr "cpu" "haswell")
+                        (and (eq_attr "cpu" "generic,haswell")
                              (and (eq_attr "memory" "load")
                                   (eq_attr "type" "fop")))
                         "hsw_decodern,hsw_p23+hsw_p1,hsw_p1")
 
 (define_insn_reservation "hsw_fop_store" 3
-                        (and (eq_attr "cpu" "haswell")
+                        (and (eq_attr "cpu" "generic,haswell")
                              (and (eq_attr "memory" "store")
                                   (eq_attr "type" "fop")))
                         "hsw_decodern,hsw_p0,hsw_p0,hsw_p0+hsw_p4+hsw_p3")
 
 (define_insn_reservation "hsw_fop_both" 5
-                        (and (eq_attr "cpu" "haswell")
+                        (and (eq_attr "cpu" "generic,haswell")
                              (and (eq_attr "memory" "both")
                                   (eq_attr "type" "fop")))
                         "hsw_decodern,hsw_p2+hsw_p0,hsw_p0+hsw_p4+hsw_p3")
 
 (define_insn_reservation "hsw_fsgn" 1
-                        (and (eq_attr "cpu" "haswell")
+                        (and (eq_attr "cpu" "generic,haswell")
                              (eq_attr "type" "fsgn"))
                         "hsw_decodern,hsw_p0")
 
 (define_insn_reservation "hsw_fistp" 7
-                        (and (eq_attr "cpu" "haswell")
+                        (and (eq_attr "cpu" "generic,haswell")
                              (eq_attr "type" "fistp"))
                         "hsw_decoder0,hsw_p1+hsw_p4+hsw_p23")
 
 (define_insn_reservation "hsw_fcmov" 2
-                        (and (eq_attr "cpu" "haswell")
+                        (and (eq_attr "cpu" "generic,haswell")
                              (eq_attr "type" "fcmov"))
                         "hsw_decoder0,hsw_p0+hsw_p5,hsw_p0")
 
 (define_insn_reservation "hsw_fcmp" 1
-                        (and (eq_attr "cpu" "haswell")
+                        (and (eq_attr "cpu" "generic,haswell")
                              (and (eq_attr "memory" "none")
                                   (eq_attr "type" "fcmp")))
                         "hsw_decodern,hsw_p1")
 
 (define_insn_reservation "hsw_fcmp_load" 1
-                        (and (eq_attr "cpu" "haswell")
+                        (and (eq_attr "cpu" "generic,haswell")
                              (and (eq_attr "memory" "load")
                                   (eq_attr "type" "fcmp")))
                         "hsw_decodern,hsw_p23+hsw_p1")
 
 (define_insn_reservation "hsw_fmov" 1
-                        (and (eq_attr "cpu" "haswell")
+                        (and (eq_attr "cpu" "generic,haswell")
                              (and (eq_attr "memory" "none")
                                   (eq_attr "type" "fmov")))
                         "hsw_decodern,hsw_p01")
 
 (define_insn_reservation "hsw_fmov_load" 3
-                        (and (eq_attr "cpu" "haswell")
+                        (and (eq_attr "cpu" "generic,haswell")
                              (and (eq_attr "memory" "load")
                                   (and (eq_attr "mode" "!XF")
                                        (eq_attr "type" "fmov"))))
                         "hsw_decodern,hsw_p23")
 
 (define_insn_reservation "hsw_fmov_XF_load" 3
-                        (and (eq_attr "cpu" "haswell")
+                        (and (eq_attr "cpu" "generic,haswell")
                              (and (eq_attr "memory" "load")
                                   (and (eq_attr "mode" "XF")
                                        (eq_attr "type" "fmov"))))
                         "hsw_decodern,(hsw_p23+hsw_p0)*2")
 
 (define_insn_reservation "hsw_fmov_store" 1
-                        (and (eq_attr "cpu" "haswell")
+                        (and (eq_attr "cpu" "generic,haswell")
                              (and (eq_attr "memory" "store")
                                   (and (eq_attr "mode" "!XF")
                                        (eq_attr "type" "fmov"))))
                         "hsw_decodern,hsw_p4p7")
 
 (define_insn_reservation "hsw_fmov_XF_store" 3
-                        (and (eq_attr "cpu" "haswell")
+                        (and (eq_attr "cpu" "generic,haswell")
                              (and (eq_attr "memory" "store")
                                   (and (eq_attr "mode" "XF")
                                        (eq_attr "type" "fmov"))))
                         "hsw_decodern,hsw_p4p7,hsw_p4p7")
 
 (define_insn_reservation "hsw_fmul" 4
-                        (and (eq_attr "cpu" "haswell")
+                        (and (eq_attr "cpu" "generic,haswell")
                              (and (eq_attr "memory" "none")
                                   (eq_attr "type" "fmul")))
                         "hsw_decodern,hsw_p01")
 
 (define_insn_reservation "hsw_fmul_load" 4
-                        (and (eq_attr "cpu" "haswell")
+                        (and (eq_attr "cpu" "generic,haswell")
                              (and (eq_attr "memory" "load")
                                   (eq_attr "type" "fmul")))
                         "hsw_decodern,hsw_p23+hsw_p01")
@@ -314,42 +314,42 @@
 ;; that.  Throughput is equal to latency - 1, which we model using the
 ;; hsw_div automaton.
 (define_insn_reservation "hsw_fdiv_SF" 18
-                        (and (eq_attr "cpu" "haswell")
+                        (and (eq_attr "cpu" "generic,haswell")
                              (and (eq_attr "memory" "none")
                                   (and (eq_attr "mode" "SF")
                                        (eq_attr "type" "fdiv,fpspc"))))
                         "hsw_decodern,hsw_p0+hsw_fdiv,hsw_fdiv*16")
 
 (define_insn_reservation "hsw_fdiv_SF_load" 19
-                        (and (eq_attr "cpu" "haswell")
+                        (and (eq_attr "cpu" "generic,haswell")
                              (and (eq_attr "memory" "load")
                                   (and (eq_attr "mode" "SF")
                                        (eq_attr "type" "fdiv,fpspc"))))
                         "hsw_decodern,hsw_p23+hsw_p0+hsw_fdiv,hsw_fdiv*16")
 
 (define_insn_reservation "hsw_fdiv_DF" 32
-                        (and (eq_attr "cpu" "haswell")
+                        (and (eq_attr "cpu" "generic,haswell")
                              (and (eq_attr "memory" "none")
                                   (and (eq_attr "mode" "DF")
                                        (eq_attr "type" "fdiv,fpspc"))))
                         "hsw_decodern,hsw_p0+hsw_fdiv,hsw_fdiv*30")
 
 (define_insn_reservation "hsw_fdiv_DF_load" 33
-                        (and (eq_attr "cpu" "haswell")
+                        (and (eq_attr "cpu" "generic,haswell")
                              (and (eq_attr "memory" "load")
                                   (and (eq_attr "mode" "DF")
                                        (eq_attr "type" "fdiv,fpspc"))))
                         "hsw_decodern,hsw_p23+hsw_p0+hsw_fdiv,hsw_fdiv*30")
 
 (define_insn_reservation "hsw_fdiv_XF" 38
-                        (and (eq_attr "cpu" "haswell")
+                        (and (eq_attr "cpu" "generic,haswell")
                              (and (eq_attr "memory" "none")
                                   (and (eq_attr "mode" "XF")
                                        (eq_attr "type" "fdiv,fpspc"))))
                         "hsw_decodern,hsw_p0+hsw_fdiv,hsw_fdiv*36")
 
 (define_insn_reservation "hsw_fdiv_XF_load" 39
-                        (and (eq_attr "cpu" "haswell")
+                        (and (eq_attr "cpu" "generic,haswell")
                              (and (eq_attr "memory" "load")
                                   (and (eq_attr "mode" "XF")
                                        (eq_attr "type" "fdiv,fpspc"))))
@@ -358,253 +358,253 @@
 ;; MMX instructions.
 
 (define_insn_reservation "hsw_mmx_add" 1
-                        (and (eq_attr "cpu" "haswell")
+                        (and (eq_attr "cpu" "generic,haswell")
                              (and (eq_attr "memory" "none")
                                   (eq_attr "type" "mmxadd,sseiadd")))
                         "hsw_decodern,hsw_p1|hsw_p5")
 
 (define_insn_reservation "hsw_mmx_add_load" 2
-                        (and (eq_attr "cpu" "haswell")
+                        (and (eq_attr "cpu" "generic,haswell")
                              (and (eq_attr "memory" "load")
                                   (eq_attr "type" "mmxadd,sseiadd")))
                         "hsw_decodern,hsw_p23+(hsw_p1|hsw_p5)")
 
 (define_insn_reservation "hsw_mmx_shft" 1
-                        (and (eq_attr "cpu" "haswell")
+                        (and (eq_attr "cpu" "generic,haswell")
                              (and (eq_attr "memory" "none")
                                   (eq_attr "type" "mmxshft")))
                         "hsw_decodern,hsw_p0")
 
 (define_insn_reservation "hsw_mmx_shft_load" 2
-                        (and (eq_attr "cpu" "haswell")
+                        (and (eq_attr "cpu" "generic,haswell")
                              (and (eq_attr "memory" "load")
                                   (eq_attr "type" "mmxshft")))
                         "hsw_decodern,hsw_p23+hsw_p0")
 
 (define_insn_reservation "hsw_mmx_sse_shft" 1
-                        (and (eq_attr "cpu" "haswell")
+                        (and (eq_attr "cpu" "generic,haswell")
                              (and (eq_attr "memory" "none")
                                   (and (eq_attr "type" "sseishft")
                                        (eq_attr "length_immediate" "!0"))))
                         "hsw_decodern,hsw_p01")
 
 (define_insn_reservation "hsw_mmx_sse_shft_load" 2
-                        (and (eq_attr "cpu" "haswell")
+                        (and (eq_attr "cpu" "generic,haswell")
                              (and (eq_attr "memory" "load")
                                   (and (eq_attr "type" "sseishft")
                                        (eq_attr "length_immediate" "!0"))))
                         "hsw_decodern,hsw_p01+hsw_p23")
 
 (define_insn_reservation "hsw_mmx_sse_shft1" 2
-                        (and (eq_attr "cpu" "haswell")
+                        (and (eq_attr "cpu" "generic,haswell")
                              (and (eq_attr "memory" "none")
                                   (and (eq_attr "type" "sseishft")
                                        (eq_attr "length_immediate" "0"))))
                         "hsw_decodern,hsw_p01")
 
 (define_insn_reservation "hsw_mmx_sse_shft1_load" 3
-                        (and (eq_attr "cpu" "haswell")
+                        (and (eq_attr "cpu" "generic,haswell")
                              (and (eq_attr "memory" "load")
                                   (and (eq_attr "type" "sseishft")
                                        (eq_attr "length_immediate" "0"))))
                         "hsw_decodern,hsw_p01+hsw_p23")
 
 (define_insn_reservation "hsw_mmx_mul" 5
-                        (and (eq_attr "cpu" "haswell")
+                        (and (eq_attr "cpu" "generic,haswell")
                              (and (eq_attr "memory" "none")
                                   (eq_attr "type" "mmxmul,sseimul")))
                         "hsw_decodern,hsw_p01")
 
 (define_insn_reservation "hsw_mmx_mul_load" 5
-                        (and (eq_attr "cpu" "haswell")
+                        (and (eq_attr "cpu" "generic,haswell")
                              (and (eq_attr "memory" "none")
                                   (eq_attr "type" "mmxmul,sseimul")))
                         "hsw_decodern,hsw_p23+hsw_p01")
 
 (define_insn_reservation "hsw_sse_mmxcvt" 4
-                        (and (eq_attr "cpu" "haswell")
+                        (and (eq_attr "cpu" "generic,haswell")
                              (and (eq_attr "mode" "DI")
                                   (eq_attr "type" "mmxcvt")))
                         "hsw_decodern,hsw_p1")
 
 ;; (define_insn_reservation "hsw_sse_mmxshft" 2
-;;                      (and (eq_attr "cpu" "haswell")
+;;                      (and (eq_attr "cpu" "generic,haswell")
 ;;                           (and (eq_attr "mode" "TI")
 ;;                                (eq_attr "type" "mmxshft")))
 ;;                      "hsw_decodern,hsw_p01")
 
 ;; The sfence instruction.
 (define_insn_reservation "hsw_sse_sfence" 2
-                        (and (eq_attr "cpu" "haswell")
+                        (and (eq_attr "cpu" "generic,haswell")
                              (and (eq_attr "memory" "unknown")
                                   (eq_attr "type" "sse")))
                         "hsw_decoder0,hsw_p23+hsw_p4")
 
 (define_insn_reservation "hsw_sse_SFDF" 3
-                        (and (eq_attr "cpu" "haswell")
+                        (and (eq_attr "cpu" "generic,haswell")
                              (and (eq_attr "mode" "SF,DF")
                                   (eq_attr "type" "sse")))
                         "hsw_decodern,hsw_p01")
 
 (define_insn_reservation "hsw_sse_V4SF" 4
-                        (and (eq_attr "cpu" "haswell")
+                        (and (eq_attr "cpu" "generic,haswell")
                              (and (eq_attr "mode" "V4SF")
                                   (eq_attr "type" "sse")))
                         "hsw_decodern,hsw_p01")
 
 (define_insn_reservation "hsw_sse_V8SF" 4
-                        (and (eq_attr "cpu" "haswell")
+                        (and (eq_attr "cpu" "generic,haswell")
                              (and (eq_attr "mode" "V8SF,V4DF")
                                   (eq_attr "type" "sse")))
                         "hsw_decodern,hsw_p01")
 
 (define_insn_reservation "hsw_sse_addcmp" 3
-                        (and (eq_attr "cpu" "haswell")
+                        (and (eq_attr "cpu" "generic,haswell")
                              (and (eq_attr "memory" "none")
                                   (eq_attr "type" "sseadd1,ssecmp,ssecomi")))
                         "hsw_decodern,hsw_p01")
 
 (define_insn_reservation "hsw_sse_addcmp_load" 3
-                        (and (eq_attr "cpu" "haswell")
+                        (and (eq_attr "cpu" "generic,haswell")
                              (and (eq_attr "memory" "load")
                                   (eq_attr "type" "sseadd1,ssecmp,ssecomi")))
                         "hsw_decodern,hsw_p23+hsw_p01")
 
 (define_insn_reservation "hsw_sse_logic" 1
-                        (and (eq_attr "cpu" "haswell")
+                        (and (eq_attr "cpu" "generic,haswell")
                              (and (eq_attr "memory" "none")
                                   (eq_attr "type" "sselog,sselog1")))
                         "hsw_decodern,hsw_p015")
 
 (define_insn_reservation "hsw_sse_logic_load" 2
-                        (and (eq_attr "cpu" "haswell")
+                        (and (eq_attr "cpu" "generic,haswell")
                              (and (eq_attr "memory" "load")
                                   (eq_attr "type" "sselog,sselog1")))
                         "hsw_decodern,hsw_p015+hsw_p23")
 
 (define_insn_reservation "hsw_sse_add" 3
-                        (and (eq_attr "cpu" "haswell")
+                        (and (eq_attr "cpu" "generic,haswell")
                              (and (eq_attr "memory" "none")
                                   (eq_attr "type" "sseadd")))
                        "hsw_decodern,hsw_p1|hsw_p5")
 
 (define_insn_reservation "hsw_sse_add_load" 3
-                        (and (eq_attr "cpu" "haswell")
+                        (and (eq_attr "cpu" "generic,haswell")
                              (and (eq_attr "memory" "load")
                                   (eq_attr "type" "sseadd")))
                        "hsw_decodern,(hsw_p1|hsw_p5)+hsw_p23")
 
 (define_insn_reservation "hsw_sse_mul" 5
-                        (and (eq_attr "cpu" "haswell")
+                        (and (eq_attr "cpu" "generic,haswell")
                              (and (eq_attr "memory" "none")
                                   (eq_attr "type" "ssemul")))
                        "hsw_decodern,hsw_p0")
 
 (define_insn_reservation "hsw_sse_mul_load" 5
-                        (and (eq_attr "cpu" "haswell")
+                        (and (eq_attr "cpu" "generic,haswell")
                              (and (eq_attr "memory" "load")
                                   (eq_attr "type" "ssemul")))
                        "hsw_decodern,hsw_p0+hsw_p23")
 ;; Use skylake pipeline.
 (define_insn_reservation "hsw_sse_muladd" 5
-                        (and (eq_attr "cpu" "haswell")
+                        (and (eq_attr "cpu" "generic,haswell")
                              (and (eq_attr "memory" "none")
                                        (eq_attr "type" "ssemuladd")))
                        "hsw_decodern,hsw_p01")
 
 (define_insn_reservation "hsw_sse_muladd_load" 5
-                        (and (eq_attr "cpu" "haswell")
+                        (and (eq_attr "cpu" "generic,haswell")
                              (and (eq_attr "memory" "load")
                                        (eq_attr "type" "ssemuladd")))
                        "hsw_decodern,hsw_p01+hsw_p23")
 
 (define_insn_reservation "hsw_sse_div_SF" 18
-                        (and (eq_attr "cpu" "haswell")
+                        (and (eq_attr "cpu" "generic,haswell")
                              (and (eq_attr "memory" "none")
                                   (and (eq_attr "mode" "SF,V4SF,V8SF")
                                        (eq_attr "type" "ssediv"))))
                         "hsw_decodern,hsw_p0,hsw_ssediv*14")
 
 (define_insn_reservation "hsw_sse_div_SF_load" 18
-                        (and (eq_attr "cpu" "haswell")
+                        (and (eq_attr "cpu" "generic,haswell")
                              (and (eq_attr "memory" "none")
                                   (and (eq_attr "mode" "SF,V4SF,V8SF")
                                        (eq_attr "type" "ssediv"))))
                         "hsw_decodern,(hsw_p23+hsw_p0),hsw_ssediv*14")
 
 (define_insn_reservation "hsw_sse_div_DF" 28
-                        (and (eq_attr "cpu" "haswell")
+                        (and (eq_attr "cpu" "generic,haswell")
                              (and (eq_attr "memory" "none")
                                   (and (eq_attr "mode" "DF,V2DF,V4DF")
                                        (eq_attr "type" "ssediv"))))
                         "hsw_decodern,hsw_p0,hsw_ssediv*20")
 
 (define_insn_reservation "hsw_sse_div_DF_load" 28
-                        (and (eq_attr "cpu" "haswell")
+                        (and (eq_attr "cpu" "generic,haswell")
                              (and (eq_attr "memory" "none")
                                   (and (eq_attr "mode" "DF,V2DF,V4DF")
                                        (eq_attr "type" "ssediv"))))
                         "hsw_decodern,(hsw_p23+hsw_p0),hsw_ssediv*20")
 
 (define_insn_reservation "hsw_sse_icvt" 4
-                        (and (eq_attr "cpu" "haswell")
+                        (and (eq_attr "cpu" "generic,haswell")
                              (and (eq_attr "memory" "none")
                                   (eq_attr "type" "sseicvt")))
                         "hsw_decodern,hsw_p1")
 
 (define_insn_reservation "hsw_sse_icvt_load" 4
-                        (and (eq_attr "cpu" "haswell")
+                        (and (eq_attr "cpu" "generic,haswell")
                              (and (eq_attr "memory" "!none")
                                   (eq_attr "type" "sseicvt")))
                         "hsw_decodern,hsw_p23+hsw_p1")
 
 
 (define_insn_reservation "hsw_sse_icvt_SI" 3
-                        (and (eq_attr "cpu" "haswell")
+                        (and (eq_attr "cpu" "generic,haswell")
                              (and (eq_attr "memory" "none")
                                   (and (eq_attr "mode" "SI")
                                        (eq_attr "type" "sseicvt"))))
                         "hsw_decodern,hsw_p1")
 
 (define_insn_reservation "hsw_sse_icvt_SI_load" 3
-                        (and (eq_attr "cpu" "haswell")
+                        (and (eq_attr "cpu" "generic,haswell")
                              (and (eq_attr "memory" "!none")
                                   (and (eq_attr "mode" "SI")
                                        (eq_attr "type" "sseicvt"))))
                         "hsw_decodern,hsw_p23+hsw_p1")
 
 (define_insn_reservation "hsw_sse_mov" 1
-                        (and (eq_attr "cpu" "haswell")
+                        (and (eq_attr "cpu" "generic,haswell")
                              (and (eq_attr "memory" "none")
                                   (eq_attr "type" "ssemov")))
                         "hsw_decodern,hsw_p015")
 
 (define_insn_reservation "hsw_sse_mov_load" 2
-                        (and (eq_attr "cpu" "haswell")
+                        (and (eq_attr "cpu" "generic,haswell")
                              (and (eq_attr "memory" "load")
                                   (eq_attr "type" "ssemov")))
                         "hsw_decodern,hsw_p23")
 
 (define_insn_reservation "hsw_sse_mov_store" 1
-                        (and (eq_attr "cpu" "haswell")
+                        (and (eq_attr "cpu" "generic,haswell")
                              (and (eq_attr "memory" "store")
                                   (eq_attr "type" "ssemov")))
                         "hsw_decodern,hsw_p4p7")
 
 (define_insn_reservation "hsw_insn" 1
-                        (and (eq_attr "cpu" "haswell")
+                        (and (eq_attr "cpu" "generic,haswell")
                              (and (eq_attr "memory" "none,unknown")
                                   (eq_attr "type" "alu,alu1,negnot,incdec,icmp,test,setcc,sseishft1,mmx,mmxcmp")))
                         "hsw_decodern,hsw_p0156")
 
 (define_insn_reservation "hsw_insn_load" 1
-                        (and (eq_attr "cpu" "haswell")
+                        (and (eq_attr "cpu" "generic,haswell")
                              (and (eq_attr "memory" "load")
                                   (eq_attr "type" "alu,alu1,negnot,incdec,icmp,test,setcc,pop,sseishft1,mmx,mmxcmp")))
                         "hsw_decodern,hsw_p23+hsw_p0156")
 
 (define_insn_reservation "hsw_insn_store" 1
-                        (and (eq_attr "cpu" "haswell")
+                        (and (eq_attr "cpu" "generic,haswell")
                              (and (eq_attr "memory" "store")
                                   (eq_attr "type" "alu,alu1,negnot,incdec,icmp,test,setcc,sseishft1,mmx,mmxcmp")))
                         "hsw_decodern,hsw_p0156+hsw_p4p7")
@@ -612,7 +612,7 @@
 ;; read-modify-store instructions produce 4 uops so they have to be
 ;; decoded on hsw_decoder0 as well.
 (define_insn_reservation "hsw_insn_both" 4
-                        (and (eq_attr "cpu" "haswell")
+                        (and (eq_attr "cpu" "generic,haswell")
                              (and (eq_attr "memory" "both")
                                   (eq_attr "type" "alu,alu1,negnot,incdec,icmp,test,setcc,pop,sseishft1,mmx,mmxcmp")))
                         "hsw_decodern,hsw_p23+hsw_p0156+hsw_p4p7")

diff --git a/gcc/config/i386/i386.c b/gcc/config/i386/i386.c
index 5638eea7636a38e333a35520f34416e04334e784..fcf7db115ad3c7bd9a50e76d4e67db21fb70ef76 100644 (file)
--- a/gcc/config/i386/i386.c
+++ b/gcc/config/i386/i386.c
@@ -28844,6 +28844,7 @@ ix86_sched_init_global (FILE *, int, int)
     case PROCESSOR_NEHALEM:
     case PROCESSOR_SANDYBRIDGE:
     case PROCESSOR_HASWELL:
+    case PROCESSOR_GENERIC:
       /* Do not perform multipass scheduling for pre-reload schedule
          to save compile time.  */
       if (reload_completed)

diff --git a/gcc/config/i386/x86-tune-sched.c b/gcc/config/i386/x86-tune-sched.c
index aac2bae806155daf0f98faaef9bd6bbd76d12dc3..5bcaf2c59daa60106a0fcacf7d94fb118fab97cd 100644 (file)
--- a/gcc/config/i386/x86-tune-sched.c
+++ b/gcc/config/i386/x86-tune-sched.c
@@ -54,7 +54,6 @@ ix86_issue_rate (void)
     case PROCESSOR_ATHLON:
     case PROCESSOR_K8:
     case PROCESSOR_AMDFAM10:
-    case PROCESSOR_GENERIC:
     case PROCESSOR_BTVER1:
       return 3;
 
@@ -67,6 +66,7 @@ ix86_issue_rate (void)
     case PROCESSOR_NEHALEM:
     case PROCESSOR_SANDYBRIDGE:
     case PROCESSOR_HASWELL:
+    case PROCESSOR_GENERIC:
       return 4;
 
     default:
@@ -354,7 +354,6 @@ ix86_adjust_cost (rtx_insn *insn, int dep_type, rtx_insn *dep_insn, int cost,
     case PROCESSOR_BDVER4:
     case PROCESSOR_BTVER1:
     case PROCESSOR_BTVER2:
-    case PROCESSOR_GENERIC:
       /* Stack engine allows to execute push&pop instructions in parall.  */
       if ((insn_type == TYPE_PUSH || insn_type == TYPE_POP)
          && (dep_insn_type == TYPE_PUSH || dep_insn_type == TYPE_POP))
@@ -424,6 +423,7 @@ ix86_adjust_cost (rtx_insn *insn, int dep_type, rtx_insn *dep_insn, int cost,
     case PROCESSOR_NEHALEM:
     case PROCESSOR_SANDYBRIDGE:
     case PROCESSOR_HASWELL:
+    case PROCESSOR_GENERIC:
       /* Stack engine allows to execute push&pop instructions in parall.  */
       if ((insn_type == TYPE_PUSH || insn_type == TYPE_POP)
          && (dep_insn_type == TYPE_PUSH || dep_insn_type == TYPE_POP))