projects
/
yosys.git
/ commitdiff
commit
grep
author
committer
pickaxe
?
search:
re
summary
|
shortlog
|
log
|
commit
| commitdiff |
tree
raw
|
patch
| inline |
side by side
(parent:
99ccb31
)
Fixed sharing of $memrd cells
author
Clifford Wolf
<clifford@clifford.at>
Sat, 12 Sep 2015 14:01:20 +0000
(16:01 +0200)
committer
Clifford Wolf
<clifford@clifford.at>
Sat, 12 Sep 2015 14:01:20 +0000
(16:01 +0200)
passes/opt/share.cc
patch
|
blob
|
history
diff --git
a/passes/opt/share.cc
b/passes/opt/share.cc
index 2c39708bb7cdb38c0d20a803a9d89b529e8b0991..9dd0dc0a34ec46b38bf65b2ed29355431a8ebebc 100644
(file)
--- a/
passes/opt/share.cc
+++ b/
passes/opt/share.cc
@@
-708,6
+708,10
@@
struct ShareWorker
if (c1->type == "$memrd")
{
RTLIL::Cell *supercell = module->addCell(NEW_ID, c1);
+ RTLIL::SigSpec addr1 = c1->getPort("\\ADDR");
+ RTLIL::SigSpec addr2 = c2->getPort("\\ADDR");
+ if (addr1 != addr2)
+ supercell->setPort("\\ADDR", module->Mux(NEW_ID, addr2, addr1, act));
supercell_aux.insert(module->addPos(NEW_ID, supercell->getPort("\\DATA"), c2->getPort("\\DATA")));
supercell_aux.insert(supercell);
return supercell;