This is because by enabling ainterrupt group at the cpu interface, we
need to check if a previously pending interrupt needs to be forwarded to
the PE.
We are doing the same when globally enabling irqs in the distributor
(GICD_CTLR).
Change-Id: I80aeb87b2a58a108de899006d5a2f12eadbe6c2e
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/20629
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>
return setMiscReg(MISCREG_ICV_IGRPEN0_EL1, val);
}
- break;
+ isa->setMiscRegNoEffect(MISCREG_ICC_IGRPEN0_EL1, val);
+ updateDistributor();
+ return;
}
// Virtual Interrupt Group 0 Enable register
}
setBankedMiscReg(MISCREG_ICC_IGRPEN1_EL1, val);
+ updateDistributor();
return;
}