tmp_req = new MemReq();
tmp_req->paddr = ref.paddr;
tmp_req->asid = ref.asid;
+ // Assume asid == thread_num
+ tmp_req->thread_num = ref.asid;
tmp_req->cmd = (MemCmdEnum)ref.cmd;
tmp_req->size = ref.size;
tmp_req->dest = ref.dest;
MemTraceReader *data_trace,
int icache_ports,
int dcache_ports)
- : BaseCPU(name, 1), icacheInterface(icache_interface),
+ : BaseCPU(name, 4), icacheInterface(icache_interface),
dcacheInterface(dcache_interface), instTrace(inst_trace),
dataTrace(data_trace), icachePorts(icache_ports),
dcachePorts(dcache_ports), outstandingRequests(0), tickEvent(this)
while (nextDataReq && (dataReqs < dcachePorts) &&
curTick >= nextDataCycle) {
+ assert(nextDataReq->thread_num < 4 && "Not enough threads");
if (dcacheInterface->isBlocked())
break;
- ++outstandingRequests;
++dataReqs;
nextDataReq->time = curTick;
nextDataReq->completionEvent =
while (nextInstReq && (instReqs < icachePorts) &&
curTick >= nextInstCycle) {
+ assert(nextInstReq->thread_num < 4 && "Not enough threads");
if (icacheInterface->isBlocked())
break;
if (nextInstReq->cmd == Squash) {
icacheInterface->squash(nextInstReq->asid);
} else {
- ++outstandingRequests;
++instReqs;
nextInstReq->completionEvent =
new TraceCompleteEvent(nextInstReq, this);
void
TraceCPU::completeRequest(MemReqPtr& req)
{
- --outstandingRequests;
}
void