(no commit message)

diff --git a/openpower/sv/svp_rewrite/svp64.mdwn b/openpower/sv/svp_rewrite/svp64.mdwn
index 077e2a356b580862e3b0d21cfd4f458ec04172a5..40511198dd10ba5f3c824df94ef423295186dae2 100644 (file)
--- a/openpower/sv/svp_rewrite/svp64.mdwn
+++ b/openpower/sv/svp_rewrite/svp64.mdwn
@@ -143,6 +143,14 @@ alternative which is understandable and, if EXTRA3 is zero, maps to "no effect"
 | 110       | Vector | `` | `RA 0b10`      |
 | 111       | Vector | `` | `RA 0b11`      |
 
+algorithm for original version:
+
+    spec = EXTRA3
+    if spec[2]: # vector
+         return RA << 2 + spec[0:1]
+    else:         # scalar
+         return RA + spec[0:1] << 5
+
 2 bit version
 
 (**TODO, i simply cannot interpret the names, they have absolutely zero meaning to me so i have no idea how to fill in the table.  this is a bad sign, indicative that the names have to go, to be replaced by something xlear snd obvious**)
@@ -163,6 +171,14 @@ alternative which is understandable and, if EXTRA2 is zero will map to "no effec
 | 10       | Vector | `` | `RA 0b00`      |
 | 11       | Vector | `` | `RA 0b10`   |
 
+algorithm for original version:
+
+    spec = EXTRA2 << 1
+    if spec[2]: # vector
+         return RA << 2 + spec[0:1]
+    else:         # scalar
+         return RA + spec[0:1] << 5
+
 ## ELWIDTH Encoding
 
 Default behaviour is set to 0b00 so that zeros follow the convention of "npt doing anything".  In this case it means that elwidth overrides are not applicable.  Thus if a 32 bit instruction operates on 32 bit, `elwidth=0b00` specifies that this behaviour is unmodified.  Likewise when a processor is switched from 64 bit to 32 bit mode, `elwidth=0b00` states that, again, the behaviour is not to be modified.