#endif
}
+RTLIL::Wire::~Wire()
+{
+#ifdef WITH_PYTHON
+ RTLIL::Wire::get_all_wires()->erase(hashidx_);
+#endif
+}
+
#ifdef WITH_PYTHON
static std::map<unsigned int, RTLIL::Wire*> *all_wires = new std::map<unsigned int, RTLIL::Wire*>();
std::map<unsigned int, RTLIL::Wire*> *RTLIL::Wire::get_all_wires(void)
#endif
}
+RTLIL::Cell::~Cell()
+{
+#ifdef WITH_PYTHON
+ RTLIL::Cell::get_all_cells()->erase(hashidx_);
+#endif
+}
+
#ifdef WITH_PYTHON
static std::map<unsigned int, RTLIL::Cell*> *all_cells = new std::map<unsigned int, RTLIL::Cell*>();
std::map<unsigned int, RTLIL::Cell*> *RTLIL::Cell::get_all_cells(void)
// use module->addWire() and module->remove() to create or destroy wires
friend struct RTLIL::Module;
Wire();
- ~Wire() { };
+ ~Wire();
public:
// do not simply copy wires
// use module->addCell() and module->remove() to create or destroy cells
friend struct RTLIL::Module;
Cell();
+ ~Cell();
public:
// do not simply copy cells