Hook up $aldff support in various passes.

diff --git a/backends/btor/btor.cc b/backends/btor/btor.cc
index 6370b53bd2cbcf0c34414f53474a3524c7d079e5..96df54a2c8e1e4ead82a38957ecdbb700c740b8e 100644 (file)
--- a/backends/btor/btor.cc
+++ b/backends/btor/btor.cc
@@ -865,7 +865,7 @@ struct BtorWorker
                        log_error("Unsupported cell type %s for cell %s.%s -- please run `dffunmap` before `write_btor`.\n",
                                        log_id(cell->type), log_id(module), log_id(cell));
                }
-               if (cell->type.in(ID($adff), ID($adffe), ID($dffsr), ID($dffsre)) || cell->type.str().substr(0, 5) == "$_DFF") {
+               if (cell->type.in(ID($adff), ID($adffe), ID($aldff), ID($aldffe), ID($dffsr), ID($dffsre)) || cell->type.str().substr(0, 5) == "$_DFF" || cell->type.str().substr(0, 7) == "$_ALDFF") {
                        log_error("Unsupported cell type %s for cell %s.%s -- please run `async2sync; dffunmap` or `clk2fflogic` before `write_btor`.\n",
                                        log_id(cell->type), log_id(module), log_id(cell));
                }

diff --git a/backends/cxxrtl/cxxrtl_backend.cc b/backends/cxxrtl/cxxrtl_backend.cc
index 40e61e5af6e1ec8c7f14ffc14010d356a7987611..ff28c20b394b083ca246036e860825567d7a12e5 100644 (file)
--- a/backends/cxxrtl/cxxrtl_backend.cc
+++ b/backends/cxxrtl/cxxrtl_backend.cc
@@ -206,6 +206,7 @@ bool is_ff_cell(RTLIL::IdString type)
        return type.in(
                ID($dff), ID($dffe), ID($sdff), ID($sdffe), ID($sdffce),
                ID($adff), ID($adffe), ID($dffsr), ID($dffsre),
+               ID($aldff), ID($aldffe),
                ID($dlatch), ID($adlatch), ID($dlatchsr), ID($sr));
 }
 
@@ -1267,6 +1268,20 @@ struct CxxrtlWorker {
                                dec_indent();
                                f << indent << "}\n";
                        }
+                       if (cell->hasPort(ID::ALOAD)) {
+                               // Asynchronous load
+                               f << indent << "if (";
+                               dump_sigspec_rhs(cell->getPort(ID::ALOAD));
+                               f << " == value<1> {" << cell->getParam(ID::ALOAD_POLARITY).as_bool() << "u}) {\n";
+                               inc_indent();
+                                       f << indent;
+                                       dump_sigspec_lhs(cell->getPort(ID::Q));
+                                       f << " = ";
+                                       dump_sigspec_rhs(cell->getPort(ID::AD));
+                                       f << ";\n";
+                               dec_indent();
+                               f << indent << "}\n";
+                       }
                        if (cell->hasPort(ID::SET)) {
                                // Asynchronous set (for individual bits)
                                f << indent;
@@ -2573,7 +2588,7 @@ struct CxxrtlWorker {
                                flow.add_node(cell);
 
                                // Various DFF cells are treated like posedge/negedge processes, see above for details.
-                               if (cell->type.in(ID($dff), ID($dffe), ID($adff), ID($adffe), ID($dffsr), ID($dffsre), ID($sdff), ID($sdffe), ID($sdffce))) {
+                               if (cell->type.in(ID($dff), ID($dffe), ID($adff), ID($adffe), ID($aldff), ID($aldffe), ID($dffsr), ID($dffsre), ID($sdff), ID($sdffe), ID($sdffce))) {
                                        if (is_valid_clock(cell->getPort(ID::CLK)))
                                                register_edge_signal(sigmap, cell->getPort(ID::CLK),
                                                        cell->parameters[ID::CLK_POLARITY].as_bool() ? RTLIL::STp : RTLIL::STn);

diff --git a/backends/smt2/smt2.cc b/backends/smt2/smt2.cc
index f44827942796bb1accc7726ee07903d14bd7a5e5..f2fa003bcb665bc2d29409b1d0c711cb67121d24 100644 (file)
--- a/backends/smt2/smt2.cc
+++ b/backends/smt2/smt2.cc
@@ -860,7 +860,7 @@ struct Smt2Worker
                        log_error("Unsupported cell type %s for cell %s.%s -- please run `dffunmap` before `write_smt2`.\n",
                                        log_id(cell->type), log_id(module), log_id(cell));
                }
-               if (cell->type.in(ID($adff), ID($adffe), ID($dffsr), ID($dffsre)) || cell->type.str().substr(0, 5) == "$_DFF") {
+               if (cell->type.in(ID($adff), ID($adffe), ID($aldff), ID($aldffe), ID($dffsr), ID($dffsre)) || cell->type.str().substr(0, 5) == "$_DFF" || cell->type.str().substr(0, 7) == "$_ALDFF") {
                        log_error("Unsupported cell type %s for cell %s.%s -- please run `async2sync; dffunmap` or `clk2fflogic` before `write_smt2`.\n",
                                        log_id(cell->type), log_id(module), log_id(cell));
                }

diff --git a/backends/smv/smv.cc b/backends/smv/smv.cc
index f4723d2a675b59cfb3f580f0f960d6af5f09656c..7bace69120f43e0ba91ad9405f423c43d020ee5b 100644 (file)
--- a/backends/smv/smv.cc
+++ b/backends/smv/smv.cc
@@ -578,7 +578,7 @@ struct SmvWorker
                                        log_error("Unsupported cell type %s for cell %s.%s -- please run `dffunmap` before `write_smv`.\n",
                                                        log_id(cell->type), log_id(module), log_id(cell));
                                }
-                               if (cell->type.in(ID($adff), ID($adffe), ID($dffsr), ID($dffsre)) || cell->type.str().substr(0, 5) == "$_DFF") {
+                               if (cell->type.in(ID($adff), ID($adffe), ID($aldff), ID($aldffe), ID($dffsr), ID($dffsre)) || cell->type.str().substr(0, 5) == "$_DFF" || cell->type.str().substr(0, 7) == "$_ALDFF") {
                                        log_error("Unsupported cell type %s for cell %s.%s -- please run `async2sync; dffunmap` or `clk2fflogic` before `write_smv`.\n",
                                                        log_id(cell->type), log_id(module), log_id(cell));
                                }

diff --git a/kernel/ff.h b/kernel/ff.h
index a06eb0a1c839028597bf5a67527be1a9f6de98db..7f01b8a368d13a900d20610a4bfdfdca3f99cf75 100644 (file)
--- a/kernel/ff.h
+++ b/kernel/ff.h
@@ -173,7 +173,7 @@ struct FfData {
 
                std::string type_str = cell->type.str();
 
-               if (cell->type.in(ID($ff), ID($dff), ID($dffe), ID($dffsr), ID($dffsre), ID($adff), ID($adffe), ID($sdff), ID($sdffe), ID($sdffce), ID($dlatch), ID($adlatch), ID($dlatchsr), ID($sr))) {
+               if (cell->type.in(ID($ff), ID($dff), ID($dffe), ID($dffsr), ID($dffsre), ID($adff), ID($adffe), ID($aldff), ID($aldffe), ID($sdff), ID($sdffe), ID($sdffce), ID($dlatch), ID($adlatch), ID($dlatchsr), ID($sr))) {
                        if (cell->type == ID($ff)) {
                                has_gclk = true;
                                sig_d = cell->getPort(ID::D);
@@ -190,7 +190,7 @@ struct FfData {
                                pol_clk = cell->getParam(ID::CLK_POLARITY).as_bool();
                                sig_d = cell->getPort(ID::D);
                        }
-                       if (cell->type.in(ID($dffe), ID($dffsre), ID($adffe), ID($sdffe), ID($sdffce))) {
+                       if (cell->type.in(ID($dffe), ID($dffsre), ID($adffe), ID($aldffe), ID($sdffe), ID($sdffce))) {
                                has_ce = true;
                                sig_ce = cell->getPort(ID::EN);
                                pol_ce = cell->getParam(ID::EN_POLARITY).as_bool();
@@ -202,6 +202,12 @@ struct FfData {
                                pol_clr = cell->getParam(ID::CLR_POLARITY).as_bool();
                                pol_set = cell->getParam(ID::SET_POLARITY).as_bool();
                        }
+                       if (cell->type.in(ID($aldff), ID($aldffe))) {
+                               has_aload = true;
+                               sig_aload = cell->getPort(ID::ALOAD);
+                               pol_aload = cell->getParam(ID::ALOAD_POLARITY).as_bool();
+                               sig_ad = cell->getPort(ID::AD);
+                       }
                        if (cell->type.in(ID($adff), ID($adffe), ID($adlatch))) {
                                has_arst = true;
                                sig_arst = cell->getPort(ID::ARST);
@@ -264,6 +270,29 @@ struct FfData {
                        has_ce = true;
                        pol_ce = type_str[10] == 'P';
                        sig_ce = cell->getPort(ID::E);
+               } else if (type_str.substr(0, 8) == "$_ALDFF_" && type_str.size() == 11) {
+                       is_fine = true;
+                       sig_d = cell->getPort(ID::D);
+                       has_clk = true;
+                       pol_clk = type_str[8] == 'P';
+                       sig_clk = cell->getPort(ID::C);
+                       has_aload = true;
+                       pol_aload = type_str[9] == 'P';
+                       sig_aload = cell->getPort(ID::L);
+                       sig_ad = cell->getPort(ID::AD);
+               } else if (type_str.substr(0, 9) == "$_ALDFFE_" && type_str.size() == 13) {
+                       is_fine = true;
+                       sig_d = cell->getPort(ID::D);
+                       has_clk = true;
+                       pol_clk = type_str[9] == 'P';
+                       sig_clk = cell->getPort(ID::C);
+                       has_aload = true;
+                       pol_aload = type_str[10] == 'P';
+                       sig_aload = cell->getPort(ID::L);
+                       sig_ad = cell->getPort(ID::AD);
+                       has_ce = true;
+                       pol_ce = type_str[11] == 'P';
+                       sig_ce = cell->getPort(ID::E);
                } else if (type_str.substr(0, 8) == "$_DFFSR_" && type_str.size() == 12) {
                        is_fine = true;
                        sig_d = cell->getPort(ID::D);
@@ -514,6 +543,11 @@ struct FfData {
                                                cell = module->addAdffe(name, sig_clk, sig_ce, sig_arst, sig_d, sig_q, val_arst, pol_clk, pol_ce, pol_arst);
                                        else
                                                cell = module->addAdff(name, sig_clk, sig_arst, sig_d, sig_q, val_arst, pol_clk, pol_arst);
+                               } else if (has_aload) {
+                                       if (has_ce)
+                                               cell = module->addAldffe(name, sig_clk, sig_ce, sig_aload, sig_d, sig_q, sig_ad, pol_clk, pol_ce, pol_aload);
+                                       else
+                                               cell = module->addAldff(name, sig_clk, sig_aload, sig_d, sig_q, sig_ad, pol_clk, pol_aload);
                                } else if (has_srst) {
                                        if (has_ce)
                                                if (ce_over_srst)
@@ -560,6 +594,11 @@ struct FfData {
                                                cell = module->addAdffeGate(name, sig_clk, sig_ce, sig_arst, sig_d, sig_q, val_arst.as_bool(), pol_clk, pol_ce, pol_arst);
                                        else
                                                cell = module->addAdffGate(name, sig_clk, sig_arst, sig_d, sig_q, val_arst.as_bool(), pol_clk, pol_arst);
+                               } else if (has_aload) {
+                                       if (has_ce)
+                                               cell = module->addAldffeGate(name, sig_clk, sig_ce, sig_aload, sig_d, sig_q, sig_ad, pol_clk, pol_ce, pol_aload);
+                                       else
+                                               cell = module->addAldffGate(name, sig_clk, sig_aload, sig_d, sig_q, sig_ad, pol_clk, pol_aload);
                                } else if (has_srst) {
                                        if (has_ce)
                                                if (ce_over_srst)

diff --git a/passes/cmds/stat.cc b/passes/cmds/stat.cc
index 422810526ccb1e0c39a14aef9762aad743d68585..14a27ed99952d03129187eca0aeee2f114c7395a 100644 (file)
--- a/passes/cmds/stat.cc
+++ b/passes/cmds/stat.cc
@@ -120,7 +120,7 @@ struct statdata_t
                                else if (cell_type.in(
                                                ID($sr), ID($ff), ID($dff), ID($dffe), ID($dffsr), ID($dffsre),
                                                ID($adff), ID($adffe), ID($sdff), ID($sdffe), ID($sdffce),
-                                               ID($dlatch), ID($adlatch), ID($dlatchsr)))
+                                               ID($aldff), ID($aldffe), ID($dlatch), ID($adlatch), ID($dlatchsr)))
                                        cell_type = stringf("%s_%d", cell_type.c_str(), GetSize(cell->getPort(ID::Q)));
                        }
 

diff --git a/passes/opt/opt_expr.cc b/passes/opt/opt_expr.cc
index cdd821c52e6c8024118b69e95d749ae57bda79a6..be0cd470be5233150e08082f2374a7710dc42d53 100644 (file)
--- a/passes/opt/opt_expr.cc
+++ b/passes/opt/opt_expr.cc
@@ -441,7 +441,7 @@ void replace_const_cells(RTLIL::Design *design, RTLIL::Module *module, bool cons
 
                if (!noclkinv)
                {
-                       if (cell->type.in(ID($dff), ID($dffe), ID($dffsr), ID($dffsre), ID($adff), ID($adffe), ID($sdff), ID($sdffe), ID($sdffce), ID($fsm), ID($memrd), ID($memrd_v2), ID($memwr), ID($memwr_v2)))
+                       if (cell->type.in(ID($dff), ID($dffe), ID($dffsr), ID($dffsre), ID($adff), ID($adffe), ID($aldff), ID($aldffe), ID($sdff), ID($sdffe), ID($sdffce), ID($fsm), ID($memrd), ID($memrd_v2), ID($memwr), ID($memwr_v2)))
                                handle_polarity_inv(cell, ID::CLK, ID::CLK_POLARITY, assign_map, invert_map);
 
                        if (cell->type.in(ID($sr), ID($dffsr), ID($dffsre), ID($dlatchsr))) {
@@ -452,10 +452,13 @@ void replace_const_cells(RTLIL::Design *design, RTLIL::Module *module, bool cons
                        if (cell->type.in(ID($adff), ID($adffe), ID($adlatch)))
                                handle_polarity_inv(cell, ID::ARST, ID::ARST_POLARITY, assign_map, invert_map);
 
+                       if (cell->type.in(ID($aldff), ID($aldffe)))
+                               handle_polarity_inv(cell, ID::ALOAD, ID::ALOAD_POLARITY, assign_map, invert_map);
+
                        if (cell->type.in(ID($sdff), ID($sdffe), ID($sdffce)))
                                handle_polarity_inv(cell, ID::SRST, ID::SRST_POLARITY, assign_map, invert_map);
 
-                       if (cell->type.in(ID($dffe), ID($adffe), ID($sdffe), ID($sdffce), ID($dffsre), ID($dlatch), ID($adlatch), ID($dlatchsr)))
+                       if (cell->type.in(ID($dffe), ID($adffe), ID($aldffe), ID($sdffe), ID($sdffce), ID($dffsre), ID($dlatch), ID($adlatch), ID($dlatchsr)))
                                handle_polarity_inv(cell, ID::EN, ID::EN_POLARITY, assign_map, invert_map);
 
                        handle_clkpol_celltype_swap(cell, "$_SR_N?_", "$_SR_P?_", ID::S, assign_map, invert_map);
@@ -484,6 +487,13 @@ void replace_const_cells(RTLIL::Design *design, RTLIL::Module *module, bool cons
                        handle_clkpol_celltype_swap(cell, "$_SDFFCE_?N??_", "$_SDFFCE_?P??_", ID::R, assign_map, invert_map);
                        handle_clkpol_celltype_swap(cell, "$_SDFFCE_???N_", "$_SDFFCE_???P_", ID::E, assign_map, invert_map);
 
+                       handle_clkpol_celltype_swap(cell, "$_ALDFF_N?_", "$_ALDFF_P?_", ID::C, assign_map, invert_map);
+                       handle_clkpol_celltype_swap(cell, "$_ALDFF_?N_", "$_ALDFF_?P_", ID::L, assign_map, invert_map);
+
+                       handle_clkpol_celltype_swap(cell, "$_ALDFFE_N??_", "$_ALDFFE_P??_", ID::C, assign_map, invert_map);
+                       handle_clkpol_celltype_swap(cell, "$_ALDFFE_?N?_", "$_ALDFFE_?P?_", ID::L, assign_map, invert_map);
+                       handle_clkpol_celltype_swap(cell, "$_ALDFFE_??N_", "$_ALDFFE_??P_", ID::E, assign_map, invert_map);
+
                        handle_clkpol_celltype_swap(cell, "$_DFFSR_N??_", "$_DFFSR_P??_", ID::C, assign_map, invert_map);
                        handle_clkpol_celltype_swap(cell, "$_DFFSR_?N?_", "$_DFFSR_?P?_", ID::S, assign_map, invert_map);
                        handle_clkpol_celltype_swap(cell, "$_DFFSR_??N_", "$_DFFSR_??P_", ID::R, assign_map, invert_map);

diff --git a/passes/techmap/simplemap.cc b/passes/techmap/simplemap.cc
index 69f9da075324818d18df6b2e96368e63442c46cb..04d7ec87471d9cb8a98efc9e5550fc1727d746b8 100644 (file)
--- a/passes/techmap/simplemap.cc
+++ b/passes/techmap/simplemap.cc
@@ -415,6 +415,8 @@ void simplemap_get_mappers(dict<IdString, void(*)(RTLIL::Module*, RTLIL::Cell*)>
        mappers[ID($adffe)]       = simplemap_ff;
        mappers[ID($sdffe)]       = simplemap_ff;
        mappers[ID($sdffce)]      = simplemap_ff;
+       mappers[ID($aldff)]       = simplemap_ff;
+       mappers[ID($aldffe)]      = simplemap_ff;
        mappers[ID($dlatch)]      = simplemap_ff;
        mappers[ID($adlatch)]     = simplemap_ff;
        mappers[ID($dlatchsr)]    = simplemap_ff;
@@ -450,7 +452,7 @@ struct SimplemapPass : public Pass {
                log("  $not, $pos, $and, $or, $xor, $xnor\n");
                log("  $reduce_and, $reduce_or, $reduce_xor, $reduce_xnor, $reduce_bool\n");
                log("  $logic_not, $logic_and, $logic_or, $mux, $tribuf\n");
-               log("  $sr, $ff, $dff, $dffe, $dffsr, $dffsre, $adff, $adffe, $sdff, $sdffe, $sdffce, $dlatch, $adlatch, $dlatchsr\n");
+               log("  $sr, $ff, $dff, $dffe, $dffsr, $dffsre, $adff, $adffe, $aldff, $aldffe, $sdff, $sdffe, $sdffce, $dlatch, $adlatch, $dlatchsr\n");
                log("\n");
        }
        void execute(std::vector<std::string> args, RTLIL::Design *design) override

diff --git a/techlibs/common/techmap.v b/techlibs/common/techmap.v
index d3dc85f248022a06c74e67459f05d135331a8384..667773e1bfb9d6a352b289bf8ad1ffbdb59e918a 100644 (file)
--- a/techlibs/common/techmap.v
+++ b/techlibs/common/techmap.v
@@ -64,7 +64,7 @@ module _90_simplemap_various;
 endmodule
 
 (* techmap_simplemap *)
-(* techmap_celltype = "$sr $ff $dff $dffe $adff $adffe $sdff $sdffe $sdffce $dffsr $dffsre $dlatch $adlatch $dlatchsr" *)
+(* techmap_celltype = "$sr $ff $dff $dffe $adff $adffe $aldff $aldffe $sdff $sdffe $sdffce $dffsr $dffsre $dlatch $adlatch $dlatchsr" *)
 module _90_simplemap_registers;
 endmodule