help = "type of cpu to run with")
parser.add_option("--checker", action="store_true");
parser.add_option("-n", "--num-cpus", type="int", default=1)
+ parser.add_option("--sys-voltage", action="store", type="string",
+ default='1.0V',
+ help = """Top-level voltage for blocks running at system
+ power supply""")
parser.add_option("--sys-clock", action="store", type="string",
default='1GHz',
help = """Top-level clock for blocks running at system
else:
fatal("Incapable of building %s full system!", buildEnv['TARGET_ISA'])
+# Create a top-level voltage domain
+test_sys.voltage_domain = VoltageDomain(voltage = options.sys_voltage)
+
# Create a source clock for the system and set the clock period
-test_sys.clk_domain = SrcClockDomain(clock = options.sys_clock)
+test_sys.clk_domain = SrcClockDomain(clock = options.sys_clock,
+ voltage_domain = test_sys.voltage_domain)
+
+# Create a CPU voltage domain
+test_sys.cpu_voltage_domain = VoltageDomain()
# Create a source clock for the CPUs and set the clock period
-test_sys.cpu_clk_domain = SrcClockDomain(clock = options.cpu_clock)
+test_sys.cpu_clk_domain = SrcClockDomain(clock = options.cpu_clock,
+ voltage_domain =
+ test_sys.cpu_voltage_domain)
if options.kernel is not None:
test_sys.kernel = binary(options.kernel)
elif buildEnv['TARGET_ISA'] == 'arm':
drive_sys = makeArmSystem(drive_mem_mode, options.machine_type, bm[1])
+ # Create a top-level voltage domain
+ drive_sys.voltage_domain = VoltageDomain(voltage = options.sys_voltage)
+
# Create a source clock for the system and set the clock period
drive_sys.clk_domain = SrcClockDomain(clock = options.sys_clock)
+ # Create a CPU voltage domain
+ drive_sys.cpu_voltage_domain = VoltageDomain()
+
# Create a source clock for the CPUs and set the clock period
- drive_sys.cpu_clk_domain = SrcClockDomain(clock = options.cpu_clock)
+ drive_sys.cpu_clk_domain = SrcClockDomain(clock = options.cpu_clock,
+ voltage_domain =
+ drive_sys.cpu_voltage_domain)
drive_sys.cpu = DriveCPUClass(clk_domain=drive_sys.cpu_clk_domain,
cpu_id=0)
system = System(cpu = [CPUClass(cpu_id=i) for i in xrange(np)],
physmem = MemClass(range=AddrRange(options.mem_size)),
mem_mode = test_mem_mode,
- clk_domain = SrcClockDomain(clock = options.sys_clock),
cache_line_size = options.cacheline_size)
+# Create a top-level voltage domain
+system.voltage_domain = VoltageDomain(voltage = options.sys_voltage)
+
+# Create a source clock for the system and set the clock period
+system.clk_domain = SrcClockDomain(clock = options.sys_clock,
+ voltage_domain = system.voltage_domain)
+
+# Create a CPU voltage domain
+system.cpu_voltage_domain = VoltageDomain()
+
# Create a separate clock domain for the CPUs
-system.cpu_clk_domain = SrcClockDomain(clock = options.cpu_clock)
+system.cpu_clk_domain = SrcClockDomain(clock = options.cpu_clock,
+ voltage_domain =
+ system.cpu_voltage_domain)
# All cpus belong to a common cpu_clk_domain, therefore running at a common
# frequency.
def ini_str(self):
return self.period.ini_str()
+class Voltage(float,ParamValue):
+ cxx_type = 'double'
+ def __new__(cls, value):
+ # convert to voltage
+ val = convert.toVoltage(value)
+ return super(cls, Voltage).__new__(cls, val)
+
+ def __str__(self):
+ return str(self.val)
+
+ def getValue(self):
+ value = float(self)
+ return value
+
+ def ini_str(self):
+ return '%f' % self.getValue()
+
class NetworkBandwidth(float,ParamValue):
cxx_type = 'float'
def __new__(cls, value):
'TcpPort', 'UdpPort', 'EthernetAddr',
'IpAddress', 'IpNetmask', 'IpWithPort',
'MemorySize', 'MemorySize32',
- 'Latency', 'Frequency', 'Clock',
+ 'Latency', 'Frequency', 'Clock', 'Voltage',
'NetworkBandwidth', 'MemoryBandwidth',
'AddrRange',
'MaxAddr', 'MaxTick', 'AllMemory',
if not 0 <= int(port) <= 0xffff:
raise ValueError, 'invalid port %s' % port
return (ip, int(port))
+
+def toVoltage(value):
+ if not isinstance(value, str):
+ raise TypeError, "wrong type '%s' should be str" % type(value)
+
+ if value.endswith('mV'):
+ return float(value[:-2]) * milli
+ elif value.endswith('V'):
+ return float(value[:-1])
+
+ raise ValueError, "cannot convert '%s' to voltage" % value
+
from m5.params import *
from m5.SimObject import SimObject
+from m5.proxy import *
# Abstract clock domain
class ClockDomain(SimObject):
cxx_header = "sim/clock_domain.hh"
clock = Param.Clock("Clock period")
+ # A source clock must be associated with a voltage domain
+ voltage_domain = Param.VoltageDomain("Voltage domain")
+
# Derived clock domain with a parent clock domain and a frequency
# divider
class DerivedClockDomain(ClockDomain):
SimObject('Root.py')
SimObject('InstTracer.py')
SimObject('ClockDomain.py')
+SimObject('VoltageDomain.py')
Source('arguments.cc')
Source('async.cc')
Source('stat_control.cc')
Source('syscall_emul.cc')
Source('clock_domain.cc')
+Source('voltage_domain.cc')
if env['TARGET_ISA'] != 'no':
SimObject('Process.py')
DebugFlag('VtoPhys')
DebugFlag('WorkItems')
DebugFlag('ClockDomain')
+DebugFlag('VoltageDomain')
--- /dev/null
+# Copyright (c) 2012 ARM Limited
+# All rights reserved.
+#
+# The license below extends only to copyright in the software and shall
+# not be construed as granting a license to any other intellectual
+# property including but not limited to intellectual property relating
+# to a hardware implementation of the functionality of the software
+# licensed hereunder. You may use the software subject to the license
+# terms below provided that you ensure that this notice is replicated
+# unmodified and in its entirety in all distributions of the software,
+# modified or unmodified, in source code or in binary form.
+#
+# Redistribution and use in source and binary forms, with or without
+# modification, are permitted provided that the following conditions are
+# met: redistributions of source code must retain the above copyright
+# notice, this list of conditions and the following disclaimer;
+# redistributions in binary form must reproduce the above copyright
+# notice, this list of conditions and the following disclaimer in the
+# documentation and/or other materials provided with the distribution;
+# neither the name of the copyright holders nor the names of its
+# contributors may be used to endorse or promote products derived from
+# this software without specific prior written permission.
+#
+# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+#
+# Authors: Vasileios Spiliopoulos
+# Akash Bagdia
+
+from m5.SimObject import SimObject
+from m5.params import *
+
+class VoltageDomain(SimObject):
+ type = 'VoltageDomain'
+ cxx_header = "sim/voltage_domain.hh"
+ # We use a default voltage of 1V to avoid forcing users to set it
+ # even if they are not interested in using the functionality
+ voltage = Param.Voltage('1V', "Operational voltage")
#include "params/DerivedClockDomain.hh"
#include "params/SrcClockDomain.hh"
#include "sim/clock_domain.hh"
+#include "sim/voltage_domain.hh"
-SrcClockDomain::SrcClockDomain(const Params *p) : ClockDomain(p)
+double
+ClockDomain::voltage() const
+{
+ return _voltageDomain->voltage();
+}
+
+SrcClockDomain::SrcClockDomain(const Params *p) :
+ ClockDomain(p, p->voltage_domain)
{
clockPeriod(p->clock);
}
}
DerivedClockDomain::DerivedClockDomain(const Params *p) :
- ClockDomain(p),
+ ClockDomain(p, p->clk_domain->voltageDomain()),
parent(*p->clk_domain),
clockDivider(p->clk_divider)
{
* Forward declaration
*/
class DerivedClockDomain;
+class VoltageDomain;
/**
* The ClockDomain provides clock to group of clocked objects bundled
- * under the same clock domain. The clock domains provide support for
+ * under the same clock domain. The clock domains, in turn, are
+ * grouped into voltage domains. The clock domains provide support for
* a hierarchial structure with source and derived domains.
*/
class ClockDomain : public SimObject
*/
Tick _clockPeriod;
+ /**
+ * Voltage domain this clock domain belongs to
+ */
+ VoltageDomain *_voltageDomain;
+
/**
* Pointers to potential derived clock domains so we can propagate
* changes.
public:
typedef ClockDomainParams Params;
- ClockDomain(const Params *p) : SimObject(p), _clockPeriod(0) {}
+ ClockDomain(const Params *p, VoltageDomain *voltage_domain) :
+ SimObject(p),
+ _clockPeriod(0),
+ _voltageDomain(voltage_domain) {}
/**
* Get the clock period.
*/
inline Tick clockPeriod() const { return _clockPeriod; }
+ /**
+ * Get the voltage domain.
+ *
+ * @return Voltage domain this clock domain belongs to
+ */
+ inline VoltageDomain *voltageDomain() const { return _voltageDomain; }
+
+
+ /**
+ * Get the current voltage this clock domain operates at.
+ *
+ * @return Voltage applied to the clock domain
+ */
+ inline double voltage() const;
+
/**
* Add a derived domain.
*
--- /dev/null
+/*
+ * Copyright (c) 2012 ARM Limited
+ * All rights reserved
+ *
+ * The license below extends only to copyright in the software and shall
+ * not be construed as granting a license to any other intellectual
+ * property including but not limited to intellectual property relating
+ * to a hardware implementation of the functionality of the software
+ * licensed hereunder. You may use the software subject to the license
+ * terms below provided that you ensure that this notice is replicated
+ * unmodified and in its entirety in all distributions of the software,
+ * modified or unmodified, in source code or in binary form.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are
+ * met: redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer;
+ * redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution;
+ * neither the name of the copyright holders nor the names of its
+ * contributors may be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+ * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ * Authors: Vasileios Spiliopoulos
+ * Akash Bagdia
+ */
+
+#include "debug/VoltageDomain.hh"
+#include "params/VoltageDomain.hh"
+#include "sim/sim_object.hh"
+#include "sim/voltage_domain.hh"
+
+VoltageDomain::VoltageDomain(const Params *p)
+ : SimObject(p), _voltage(0)
+{
+ voltage(p->voltage);
+}
+
+void
+VoltageDomain::voltage(double voltage)
+{
+ if (voltage <= 0) {
+ fatal("Voltage should be greater than zero.\n");
+ }
+
+ _voltage = voltage;
+ DPRINTF(VoltageDomain,
+ "Setting voltage to %f for domain %s\n", _voltage, name());
+}
+
+VoltageDomain *
+VoltageDomainParams::create()
+{
+ return new VoltageDomain(this);
+}
--- /dev/null
+/*
+ * Copyright (c) 2012 ARM Limited
+ * All rights reserved
+ *
+ * The license below extends only to copyright in the software and shall
+ * not be construed as granting a license to any other intellectual
+ * property including but not limited to intellectual property relating
+ * to a hardware implementation of the functionality of the software
+ * licensed hereunder. You may use the software subject to the license
+ * terms below provided that you ensure that this notice is replicated
+ * unmodified and in its entirety in all distributions of the software,
+ * modified or unmodified, in source code or in binary form.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are
+ * met: redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer;
+ * redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution;
+ * neither the name of the copyright holders nor the names of its
+ * contributors may be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+ * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ * Authors: Vasileios Spiliopoulos
+ * Akash Bagdia
+ */
+
+#ifndef __SIM_VOLTAGE_DOMAIN_HH__
+#define __SIM_VOLTAGE_DOMAIN_HH__
+
+#include "base/statistics.hh"
+#include "params/VoltageDomain.hh"
+#include "sim/sim_object.hh"
+
+/**
+ * A VoltageDomain is used to group clock domains that operate under
+ * the same voltage. The class provides methods for setting and
+ * getting the voltage.
+ */
+class VoltageDomain : public SimObject
+{
+
+ private:
+
+ /**
+ * The voltage of the domain expressed in Volts
+ */
+ double _voltage;
+
+ public:
+
+ typedef VoltageDomainParams Params;
+ VoltageDomain(const Params *p);
+
+ /**
+ * Get the current volate.
+ *
+ * @return Voltage of the domain
+ */
+ inline double voltage() const { return _voltage; }
+
+ /**
+ * Set the voltage of the domain.
+ *
+ * @param Voltage value to be set
+ */
+ void voltage(double voltage);
+
+};
+
+#endif
# Create system clock domain. This provides clock value to every
# clocked object that lies beneath it unless explicitly overwritten
# by a different clock domain.
- system.clk_domain = SrcClockDomain(clock = '1GHz')
+ system.voltage_domain = VoltageDomain()
+ system.clk_domain = SrcClockDomain(clock = '1GHz',
+ voltage_domain =
+ system.voltage_domain)
# Create a seperate clock domain for components that should
# run at CPUs frequency
- system.cpu_clk_domain = SrcClockDomain(clock = '2GHz')
+ system.cpu_clk_domain = SrcClockDomain(clock = '2GHz',
+ voltage_domain =
+ system.voltage_domain)
@abstractmethod
def create_system(self):
system = System(cpu = cpus,
funcmem = SimpleMemory(in_addr_map = False),
physmem = SimpleMemory(null = True),
- funcbus = NoncoherentBus(),
- clk_domain = SrcClockDomain(clock = options.sys_clock))
+ funcbus = NoncoherentBus())
+# Dummy voltage domain for all our clock domains
+system.voltage_domain = VoltageDomain()
+system.clk_domain = SrcClockDomain(clock = '1GHz',
+ voltage_domain = system.voltage_domain)
# Create a seperate clock domain for components that should run at
# CPUs frequency
-system.cpu_clk_domain = SrcClockDomain(clock = '2GHz')
+system.cpu_clk_domain = SrcClockDomain(clock = '2GHz',
+ voltage_domain = system.voltage_domain)
# All cpus are associated with cpu_clk_domain
for cpu in cpus:
Ruby.create_system(options, system)
# Create a separate clock domain for Ruby
-system.ruby.clk_domain = SrcClockDomain(clock = options.ruby_clock)
+system.ruby.clk_domain = SrcClockDomain(clock = options.ruby_clock,
+ voltage_domain = system.voltage_domain)
assert(len(cpus) == len(system.ruby._cpu_ruby_ports))
system = System(cpu = cpus, funcmem = SimpleMemory(in_addr_map = False),
funcbus = NoncoherentBus(),
physmem = SimpleMemory(),
- membus = CoherentBus(width=16),
- clk_domain = SrcClockDomain(clock = '1GHz'))
+ membus = CoherentBus(width=16))
+# Dummy voltage domain for all our clock domains
+system.voltage_domain = VoltageDomain()
+system.clk_domain = SrcClockDomain(clock = '1GHz',
+ voltage_domain = system.voltage_domain)
# Create a seperate clock domain for components that should run at
# CPUs frequency
-system.cpu_clk_domain = SrcClockDomain(clock = '2GHz')
+system.cpu_clk_domain = SrcClockDomain(clock = '2GHz',
+ voltage_domain = system.voltage_domain)
system.toL2Bus = CoherentBus(clk_domain = system.cpu_clk_domain, width=16)
system.l2c = L2Cache(clk_domain = system.cpu_clk_domain, size='64kB', assoc=8)
mdesc = SysConfig(disk = 'linux-x86.img')
system = FSConfig.makeLinuxX86System('timing', options.num_cpus,
mdesc=mdesc, Ruby=True)
+# Dummy voltage domain for all our clock domains
+system.voltage_domain = VoltageDomain(voltage = options.sys_voltage)
system.kernel = FSConfig.binary('x86_64-vmlinux-2.6.22.9.smp')
-system.clk_domain = SrcClockDomain(clock = '1GHz')
-system.cpu_clk_domain = SrcClockDomain(clock = '2GHz')
+system.clk_domain = SrcClockDomain(clock = '1GHz',
+ voltage_domain = system.voltage_domain)
+system.cpu_clk_domain = SrcClockDomain(clock = '2GHz',
+ voltage_domain = system.voltage_domain)
system.cpu = [TimingSimpleCPU(cpu_id=i, clk_domain = system.cpu_clk_domain)
for i in xrange(options.num_cpus)]
Ruby.create_system(options, system, system.piobus, system._dma_ports)
# Create a seperate clock domain for Ruby
-system.ruby.clk_domain = SrcClockDomain(clock = options.ruby_clock)
+system.ruby.clk_domain = SrcClockDomain(clock = options.ruby_clock,
+ voltage_domain = system.voltage_domain)
for (i, cpu) in enumerate(system.cpu):
# create the interrupt controller
tester = RubyTester(check_flush = check_flush, checks_to_complete = 100,
wakeup_frequency = 10, num_cpus = options.num_cpus)
-system = System(tester = tester, physmem = SimpleMemory(null = True),
- clk_domain = SrcClockDomain(clock = options.sys_clock))
+system = System(tester = tester, physmem = SimpleMemory(null = True))
+# Dummy voltage domain for all our clock domains
+system.voltage_domain = VoltageDomain(voltage = options.sys_voltage)
+system.clk_domain = SrcClockDomain(clock = '1GHz',
+ voltage_domain = system.voltage_domain)
system.mem_ranges = AddrRange('256MB')
Ruby.create_system(options, system)
# Create a separate clock domain for Ruby
-system.ruby.clk_domain = SrcClockDomain(clock = '1GHz')
+system.ruby.clk_domain = SrcClockDomain(clock = '1GHz',
+ voltage_domain = system.voltage_domain)
assert(options.num_cpus == len(system.ruby._cpu_ruby_ports))
options.num_cpus = 1
cpu = TimingSimpleCPU(cpu_id=0)
-system = System(cpu = cpu, physmem = SimpleMemory(null = True),
- clk_domain = SrcClockDomain(clock = '1GHz'))
+system = System(cpu = cpu, physmem = SimpleMemory(null = True))
+# Dummy voltage domain for all our clock domains
+system.voltage_domain = VoltageDomain(voltage = options.sys_voltage)
+system.clk_domain = SrcClockDomain(clock = '1GHz',
+ voltage_domain = system.voltage_domain)
# Create a seperate clock domain for components that should run at
# CPUs frequency
-system.cpu.clk_domain = SrcClockDomain(clock = '2GHz')
+system.cpu.clk_domain = SrcClockDomain(clock = '2GHz',
+ voltage_domain = system.voltage_domain)
system.mem_ranges = AddrRange('256MB')
Ruby.create_system(options, system)
# Create a separate clock for Ruby
-system.ruby.clk_domain = SrcClockDomain(clock = options.ruby_clock)
+system.ruby.clk_domain = SrcClockDomain(clock = options.ruby_clock,
+ voltage_domain = system.voltage_domain)
assert(len(system.ruby._cpu_ruby_ports) == 1)
import FSConfig
system = FSConfig.makeSparcSystem('atomic')
-system.clk_domain = SrcClockDomain(clock = '1GHz')
-system.cpu_clk_domain = SrcClockDomain(clock = '1GHz')
+system.voltage_domain = VoltageDomain()
+system.clk_domain = SrcClockDomain(clock = '1GHz',
+ voltage_domain = system.voltage_domain)
+system.cpu_clk_domain = SrcClockDomain(clock = '1GHz',
+ voltage_domain = system.voltage_domain)
cpu = AtomicSimpleCPU(cpu_id=0, clk_domain = system.cpu_clk_domain)
system.cpu = cpu
# create the interrupt controller
# system simulated
system = System(cpu = cpu, physmem = DDR3_1600_x64(),
membus = NoncoherentBus(width = 16),
- clk_domain = SrcClockDomain(clock = '1GHz'))
+ clk_domain = SrcClockDomain(clock = '1GHz',
+ voltage_domain =
+ VoltageDomain()))
# add a communication monitor
system.monitor = CommMonitor()
# system simulated
system = System(cpu = cpu, physmem = SimpleMemory(),
membus = NoncoherentBus(width = 16),
- clk_domain = SrcClockDomain(clock = '1GHz'))
+ clk_domain = SrcClockDomain(clock = '1GHz',
+ voltage_domain =
+ VoltageDomain()))
# add a communication monitor, and also trace all the packets
system.monitor = CommMonitor(trace_file = "monitor.ptrc.gz")
test_sys = makeLinuxAlphaSystem('atomic',
SysConfig('netperf-stream-client.rcS'))
+# Dummy voltage domain for all test_sys clock domains
+test_sys.voltage_domain = VoltageDomain()
+
# Create the system clock domain
-test_sys.clk_domain = SrcClockDomain(clock = '1GHz')
+test_sys.clk_domain = SrcClockDomain(clock = '1GHz',
+ voltage_domain = test_sys.voltage_domain)
test_sys.cpu = AtomicSimpleCPU(cpu_id=0)
# create the interrupt controller
# Create a seperate clock domain for components that should run at
# CPUs frequency
-test_sys.cpu.clk_domain = SrcClockDomain(clock = '2GHz')
+test_sys.cpu.clk_domain = SrcClockDomain(clock = '2GHz',
+ voltage_domain =
+ test_sys.voltage_domain)
# Create a separate clock domain for Ethernet
-test_sys.tsunami.ethernet.clk_domain = SrcClockDomain(clock = '500MHz')
+test_sys.tsunami.ethernet.clk_domain = SrcClockDomain(clock = '500MHz',
+ voltage_domain =
+ test_sys.voltage_domain)
# In contrast to the other (one-system) Tsunami configurations we do
# not have an IO cache but instead rely on an IO bridge for accesses
drive_sys = makeLinuxAlphaSystem('atomic',
SysConfig('netperf-server.rcS'))
+# Dummy voltage domain for all drive_sys clock domains
+drive_sys.voltage_domain = VoltageDomain()
# Create the system clock domain
-drive_sys.clk_domain = SrcClockDomain(clock = '1GHz')
+drive_sys.clk_domain = SrcClockDomain(clock = '1GHz',
+ voltage_domain =
+ drive_sys.voltage_domain)
drive_sys.cpu = AtomicSimpleCPU(cpu_id=0)
# create the interrupt controller
drive_sys.cpu.createInterruptController()
# Create a seperate clock domain for components that should run at
# CPUs frequency
-drive_sys.cpu.clk_domain = SrcClockDomain(clock = '4GHz')
+drive_sys.cpu.clk_domain = SrcClockDomain(clock = '4GHz',
+ voltage_domain =
+ drive_sys.voltage_domain)
# Create a separate clock domain for Ethernet
-drive_sys.tsunami.ethernet.clk_domain = SrcClockDomain(clock = '500MHz')
+drive_sys.tsunami.ethernet.clk_domain = SrcClockDomain(clock = '500MHz',
+ voltage_domain =
+ drive_sys.voltage_domain)
drive_sys.iobridge = Bridge(delay='50ns', ranges = drive_sys.mem_ranges)
drive_sys.iobridge.slave = drive_sys.iobus.master
projects / gem5.git / commitdiff