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add SIMD comparison section
author
Luke Kenneth Casson Leighton
<lkcl@lkcl.net>
Mon, 16 Apr 2018 18:23:13 +0000
(19:23 +0100)
committer
Luke Kenneth Casson Leighton
<lkcl@lkcl.net>
Mon, 16 Apr 2018 18:23:13 +0000
(19:23 +0100)
simple_v_extension.mdwn
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diff --git
a/simple_v_extension.mdwn
b/simple_v_extension.mdwn
index c19db7a0523090b067abc55212bdee91adbe335b..d1b6dd20a11e0df0a2821f4a14a4496b9b2ada01 100644
(file)
--- a/
simple_v_extension.mdwn
+++ b/
simple_v_extension.mdwn
@@
-1119,7
+1119,7
@@
instruction decode) with minimum disruption and effort.
RVV is extremely well-designed and has some amazing features, including
2D reorganisation of memory through LOAD/STORE "strides".
-* plus: regular predictable workload means that implmentations may
+* plus: regular predictable workload means that impl
e
mentations may
streamline effects on L1/L2 Cache.
* plus: regular and clear parallel workload also means that lanes
(similar to Alt-RVP) may be used as an implementation detail,