radv: store the ESGS ring size as part of gfx10_ngg_info

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>

diff --git a/src/amd/vulkan/radv_pipeline.c b/src/amd/vulkan/radv_pipeline.c
index b7750052010cb52048d32b763ac7be4d8191fb55..70f62725ac0cf70b5dcba754ac6105f30758cae5 100644 (file)
--- a/src/amd/vulkan/radv_pipeline.c
+++ b/src/amd/vulkan/radv_pipeline.c
@@ -1833,6 +1833,7 @@ gfx10_get_ngg_info(const VkGraphicsPipelineCreateInfo *pCreateInfo,
        ngg->prim_amp_factor = prim_amp_factor;
        ngg->max_vert_out_per_gs_instance = max_vert_out_per_gs_instance;
        ngg->ngg_emit_size = max_gsprims * gsprim_lds_size;
+       ngg->esgs_ring_size = 4 * max_esverts * esvert_lds_size;
 
        if (gs_type == MESA_SHADER_GEOMETRY) {
                ngg->vgt_esgs_ring_itemsize = es_info->esgs_itemsize / 4;
@@ -1840,7 +1841,7 @@ gfx10_get_ngg_info(const VkGraphicsPipelineCreateInfo *pCreateInfo,
                ngg->vgt_esgs_ring_itemsize = 1;
        }
 
-       pipeline->graphics.esgs_ring_size = 4 * max_esverts * esvert_lds_size;
+       pipeline->graphics.esgs_ring_size = ngg->esgs_ring_size;
 
        assert(ngg->hw_max_esverts >= 24); /* HW limitation */
 }

diff --git a/src/amd/vulkan/radv_shader.h b/src/amd/vulkan/radv_shader.h
index 8574939b82f9319c7b8165a157a9dca22ee86939..61431cc9683cc9b445f2aacb11a1a817a40b7569 100644 (file)
--- a/src/amd/vulkan/radv_shader.h
+++ b/src/amd/vulkan/radv_shader.h
@@ -209,6 +209,7 @@ struct gfx10_ngg_info {
        uint32_t max_out_verts;
        uint32_t prim_amp_factor;
        uint32_t vgt_esgs_ring_itemsize;
+       uint32_t esgs_ring_size;
        bool max_vert_out_per_gs_instance;
 };