// ** IN_PORTS **
// Trigger Queue
- in_port(triggerQueue_in, TriggerMsg, triggerQueue) {
+ in_port(triggerQueue_in, TriggerMsg, triggerQueue, rank=5) {
if (triggerQueue_in.isReady()) {
peek(triggerQueue_in, TriggerMsg) {
if (in_msg.Type == TriggerType:ALL_ACKS) {
}
}
- in_port(unblockNetwork_in, ResponseMsg, unblockToDir) {
+ in_port(unblockNetwork_in, ResponseMsg, unblockToDir, rank=4) {
if (unblockNetwork_in.isReady()) {
peek(unblockNetwork_in, ResponseMsg) {
if (in_msg.Type == CoherenceResponseType:UNBLOCK) {
}
// Response Network
- in_port(responseToDir_in, ResponseMsg, responseToDir) {
+ in_port(responseToDir_in, ResponseMsg, responseToDir, rank=3) {
if (responseToDir_in.isReady()) {
peek(responseToDir_in, ResponseMsg) {
if (in_msg.Type == CoherenceResponseType:ACK) {
}
}
- in_port(dmaRequestQueue_in, DMARequestMsg, dmaRequestToDir) {
- if (dmaRequestQueue_in.isReady()) {
- peek(dmaRequestQueue_in, DMARequestMsg) {
- if (in_msg.Type == DMARequestType:READ) {
- trigger(Event:DMA_READ, in_msg.LineAddress);
- } else if (in_msg.Type == DMARequestType:WRITE) {
- trigger(Event:DMA_WRITE, in_msg.LineAddress);
- } else {
- error("Invalid message");
- }
- }
- }
- }
-
// off-chip memory request/response is done
- in_port(memQueue_in, MemoryMsg, memBuffer) {
+ in_port(memQueue_in, MemoryMsg, memBuffer, rank=2) {
if (memQueue_in.isReady()) {
peek(memQueue_in, MemoryMsg) {
if (in_msg.Type == MemoryRequestType:MEMORY_READ) {
}
}
- in_port(requestQueue_in, RequestMsg, requestToDir) {
+ in_port(requestQueue_in, RequestMsg, requestToDir, rank=1) {
if (requestQueue_in.isReady()) {
peek(requestQueue_in, RequestMsg) {
if (in_msg.Type == CoherenceRequestType:PUT) {
}
}
+ in_port(dmaRequestQueue_in, DMARequestMsg, dmaRequestToDir, rank=0) {
+ if (dmaRequestQueue_in.isReady()) {
+ peek(dmaRequestQueue_in, DMARequestMsg) {
+ if (in_msg.Type == DMARequestType:READ) {
+ trigger(Event:DMA_READ, in_msg.LineAddress);
+ } else if (in_msg.Type == DMARequestType:WRITE) {
+ trigger(Event:DMA_WRITE, in_msg.LineAddress);
+ } else {
+ error("Invalid message");
+ }
+ }
+ }
+ }
+
// Actions
action(r_setMRU, "\rr", desc="manually set the MRU bit for pf entry" ) {
unblockNetwork_in.dequeue();
}
+ action(k_wakeUpDependents, "k", desc="wake-up dependents") {
+ wake_up_dependents(address);
+ }
+
action(l_popMemQueue, "q", desc="Pop off-chip request queue") {
memQueue_in.dequeue();
}
dmaRequestQueue_in.dequeue();
}
- action(y_recycleDmaRequestQueue, "y", desc="recycle dma request queue") {
- dmaRequestQueue_in.recycle();
+ action(zd_stallAndWaitDMARequest, "zd", desc="Stall and wait the dma request queue") {
+ peek(dmaRequestQueue_in, DMARequestMsg) {
+ APPEND_TRANSITION_COMMENT(in_msg.Requestor);
+ }
+ stall_and_wait(dmaRequestQueue_in, address);
}
action(r_recordMemoryData, "rd", desc="record data from memory to TBE") {
}
}
- action(zz_recycleRequest, "\z", desc="Recycle the request queue") {
+ action(z_stallAndWaitRequest, "z", desc="Recycle the request queue") {
peek(requestQueue_in, RequestMsg) {
APPEND_TRANSITION_COMMENT(in_msg.Requestor);
}
- requestQueue_in.recycle();
+ stall_and_wait(requestQueue_in, address);
}
// TRANSITIONS
NO_DR_B, O_DR_B, O_B_W, O_DR_B_W, NO_DW_W,
NO_W, O_W, WB, WB_E_W, WB_O_W, O_R, S_R, NO_R},
{GETS, GETX, PUT, Pf_Replacement}) {
- zz_recycleRequest;
+ z_stallAndWaitRequest;
}
transition({NO_B, O_B, NO_DR_B_W, NO_DW_B_W, NO_B_W, NO_DR_B_D,
NO_DR_B, O_DR_B, O_B_W, O_DR_B_W, NO_DW_W,
NO_W, O_W, WB, WB_E_W, WB_O_W, O_R, S_R, NO_R},
{DMA_READ, DMA_WRITE}) {
- y_recycleDmaRequestQueue;
+ zd_stallAndWaitDMARequest;
}
transition(NO_B, UnblockS, NX) {
+ k_wakeUpDependents;
j_popIncomingUnblockQueue;
}
transition(NO_B, UnblockM, NO) {
uo_updateOwnerIfPf;
+ k_wakeUpDependents;
j_popIncomingUnblockQueue;
}
transition(O_B, UnblockS, O) {
+ k_wakeUpDependents;
j_popIncomingUnblockQueue;
}
transition({O_R, S_R, NO_R}, All_acks_and_data_no_sharers, E) {
w_deallocateTBE;
+ k_wakeUpDependents;
g_popTriggerQueue;
}
dt_sendDmaDataFromTbe;
wdt_writeDataFromTBE;
w_deallocateTBE;
+ k_wakeUpDependents;
g_popTriggerQueue;
}
dt_sendDmaDataFromTbe;
wdt_writeDataFromTBE;
w_deallocateTBE;
+ k_wakeUpDependents;
g_popTriggerQueue;
}
dt_sendDmaDataFromTbe;
wdt_writeDataFromTBE;
w_deallocateTBE;
+ k_wakeUpDependents;
g_popTriggerQueue;
}
dt_sendDmaDataFromTbe;
wdt_writeDataFromTBE;
w_deallocateTBE;
+ k_wakeUpDependents;
g_popTriggerQueue;
}
transition(O_DR_B, All_acks_and_owner_data, O) {
wdt_writeDataFromTBE;
w_deallocateTBE;
+ k_wakeUpDependents;
g_popTriggerQueue;
}
wdt_writeDataFromTBE;
w_deallocateTBE;
pfd_probeFilterDeallocate;
+ k_wakeUpDependents;
g_popTriggerQueue;
}
wdt_writeDataFromTBE;
w_deallocateTBE;
ppfd_possibleProbeFilterDeallocate;
+ k_wakeUpDependents;
g_popTriggerQueue;
}
wdt_writeDataFromTBE;
w_deallocateTBE;
ppfd_possibleProbeFilterDeallocate;
+ k_wakeUpDependents;
g_popTriggerQueue;
}
da_sendDmaAck;
w_deallocateTBE;
ppfd_possibleProbeFilterDeallocate;
+ k_wakeUpDependents;
l_popMemQueue;
}
transition(NO_W, Memory_Data, NO) {
w_deallocateTBE;
+ k_wakeUpDependents;
l_popMemQueue;
}
transition(O_W, Memory_Data, O) {
w_deallocateTBE;
+ k_wakeUpDependents;
l_popMemQueue;
}
transition(WB_E_W, Memory_Ack, E) {
pfd_probeFilterDeallocate;
+ k_wakeUpDependents;
l_popMemQueue;
}
transition(WB_O_W, Memory_Ack, O) {
+ k_wakeUpDependents;
l_popMemQueue;
}
transition(WB, Writeback_Clean, O) {
ll_checkIncomingWriteback;
+ k_wakeUpDependents;
j_popIncomingUnblockQueue;
}
transition(WB, Writeback_Exclusive_Clean, E) {
ll_checkIncomingWriteback;
pfd_probeFilterDeallocate;
+ k_wakeUpDependents;
j_popIncomingUnblockQueue;
}
transition(WB, Unblock, NO) {
auno_assertUnblockerNotOwner;
+ k_wakeUpDependents;
j_popIncomingUnblockQueue;
}
}
g_eventQueue_ptr->getTime() + m_recycle_latency);
}
+void
+MessageBuffer::reanalyzeMessages(const Address& addr)
+{
+ DEBUG_MSG(QUEUE_COMP, MedPrio, "reanalyzeMessages " + m_name);
+ assert(m_stall_msg_map.count(addr) > 0);
+
+ //
+ // Put all stalled messages associated with this address back on the
+ // prio heap
+ //
+ while(!m_stall_msg_map[addr].empty()) {
+ m_msg_counter++;
+ MessageBufferNode msgNode(g_eventQueue_ptr->getTime() + 1,
+ m_msg_counter,
+ m_stall_msg_map[addr].front());
+
+ m_prio_heap.push_back(msgNode);
+ push_heap(m_prio_heap.begin(), m_prio_heap.end(),
+ greater<MessageBufferNode>());
+
+ g_eventQueue_ptr->scheduleEventAbsolute(m_consumer_ptr, msgNode.m_time);
+ m_stall_msg_map[addr].pop_front();
+ }
+}
+
+void
+MessageBuffer::stallMessage(const Address& addr)
+{
+ DEBUG_MSG(QUEUE_COMP, MedPrio, "stalling " + m_name);
+ assert(isReady());
+ assert(addr.getOffset() == 0);
+ MsgPtr message = m_prio_heap.front().m_msgptr;
+
+ pop();
+
+ //
+ // Note: no event is scheduled to analyze the map at a later time.
+ // Instead the controller is responsible to call reanalyzeMessages when
+ // these addresses change state.
+ //
+ (m_stall_msg_map[addr]).push_back(message);
+}
+
int
MessageBuffer::setAndReturnDelayCycles(MsgPtr msg_ptr)
{
#include "mem/ruby/common/Global.hh"
#include "mem/ruby/eventqueue/RubyEventQueue.hh"
#include "mem/ruby/slicc_interface/Message.hh"
+#include "mem/ruby/common/Address.hh"
class MessageBuffer
{
m_recycle_latency = recycle_latency;
}
+ void reanalyzeMessages(const Address& addr);
+ void stallMessage(const Address& addr);
+
// TRUE if head of queue timestamp <= SystemTime
bool
isReady() const
// Data Members (m_ prefix)
Consumer* m_consumer_ptr; // Consumer to signal a wakeup(), can be NULL
std::vector<MessageBufferNode> m_prio_heap;
+
+ typedef m5::hash_map< Address, std::list<MsgPtr> > StallMsgMapType;
+ typedef std::vector<MsgPtr>::iterator MsgListIter;
+
+ StallMsgMapType m_stall_msg_map;
std::string m_name;
int m_max_size;
from slicc.symbols import Func, Type, Var
class InPortDeclAST(DeclAST):
+ max_port_rank = 0
+
def __init__(self, slicc, ident, msg_type, var_expr, pairs, statements):
super(InPortDeclAST, self).__init__(slicc, pairs)
self.var_expr = var_expr
self.statements = statements
self.queue_type = TypeAST(slicc, "InPort")
+ if self.pairs.has_key("rank"):
+ InPortDeclAST.max_port_rank = max(self.pairs["rank"],
+ InPortDeclAST.max_port_rank)
def __repr__(self):
return "[InPortDecl: %s]" % self.ident
self.error("InPort declaration not part of a machine.")
machine.addInPort(in_port)
+
+ # Include max_rank to be used by StateMachine.py
+ in_port["max_port_rank"] = InPortDeclAST.max_port_rank
}
''')
+ if self.pairs.has_key("wake_up"):
+ address_field = self.pairs['wake_up']
+ code('''
+ if (m_waiting_buffers.count(in_msg_ptr->m_$address_field) > 0) {
+ wakeUpBuffers(in_msg_ptr->m_$address_field);
+ }
+ ''')
+
# The other statements
self.statements.generate(code, return_type)
self.symtab.popFrame()
--- /dev/null
+# Copyright (c) 1999-2008 Mark D. Hill and David A. Wood
+# Copyright (c) 2009 The Hewlett-Packard Development Company
+# Copyright (c) 2010 Advanced Micro Devices, Inc.
+# All rights reserved.
+#
+# Redistribution and use in source and binary forms, with or without
+# modification, are permitted provided that the following conditions are
+# met: redistributions of source code must retain the above copyright
+# notice, this list of conditions and the following disclaimer;
+# redistributions in binary form must reproduce the above copyright
+# notice, this list of conditions and the following disclaimer in the
+# documentation and/or other materials provided with the distribution;
+# neither the name of the copyright holders nor the names of its
+# contributors may be used to endorse or promote products derived from
+# this software without specific prior written permission.
+#
+# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+
+from slicc.ast.StatementAST import StatementAST
+
+class StallAndWaitStatementAST(StatementAST):
+ def __init__(self, slicc, in_port, address):
+ super(StatementAST, self).__init__(slicc)
+ self.in_port = in_port
+ self.address = address
+
+ def __repr__(self):
+ return "[StallAndWaitStatementAst: %r]" % self.variable
+
+ def generate(self, code, return_type):
+ self.in_port.assertType("InPort")
+ self.address.assertType("Address")
+
+ in_port_code = self.in_port.var.code
+ address_code = self.address.var.code
+ code('''
+ stallBuffer(&($in_port_code), $address_code);
+ $in_port_code.stallMessage($address_code);
+ ''')
--- /dev/null
+# Copyright (c) 1999-2008 Mark D. Hill and David A. Wood
+# Copyright (c) 2009 The Hewlett-Packard Development Company
+# Copyright (c) 2010 Advanced Micro Devices, Inc.
+# All rights reserved.
+#
+# Redistribution and use in source and binary forms, with or without
+# modification, are permitted provided that the following conditions are
+# met: redistributions of source code must retain the above copyright
+# notice, this list of conditions and the following disclaimer;
+# redistributions in binary form must reproduce the above copyright
+# notice, this list of conditions and the following disclaimer in the
+# documentation and/or other materials provided with the distribution;
+# neither the name of the copyright holders nor the names of its
+# contributors may be used to endorse or promote products derived from
+# this software without specific prior written permission.
+#
+# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+
+from slicc.ast.StatementAST import StatementAST
+
+class WakeUpDependentsStatementAST(StatementAST):
+ def __init__(self, slicc, address):
+ super(StatementAST, self).__init__(slicc)
+ self.address = address
+
+ def __repr__(self):
+ return "[WakeUpDependentsStatementAst: %r]" % self.variable
+
+ def generate(self, code, return_type):
+ self.address.assertType("Address")
+ address_code = self.address.var.code
+ code('''
+ if (m_waiting_buffers.count($address_code) > 0) {
+ wakeUpBuffers($address_code);
+ }
+ ''')
from slicc.ast.PairListAST import *
from slicc.ast.PeekStatementAST import *
from slicc.ast.ReturnStatementAST import *
+from slicc.ast.StallAndWaitStatementAST import *
from slicc.ast.StatementAST import *
from slicc.ast.StatementListAST import *
from slicc.ast.StaticCastAST import *
from slicc.ast.TypeFieldMemberAST import *
from slicc.ast.TypeFieldMethodAST import *
from slicc.ast.VarExprAST import *
+from slicc.ast.WakeUpDependentsStatementAST import *
'external_type' : 'EXTERN_TYPE',
'enumeration' : 'ENUM',
'peek' : 'PEEK',
+ 'stall_and_wait' : 'STALL_AND_WAIT',
+ 'wake_up_dependents' : 'WAKE_UP_DEPENDENTS',
'enqueue' : 'ENQUEUE',
'copy_head' : 'COPY_HEAD',
'check_allocate' : 'CHECK_ALLOCATE',
def p_pair__assign(self, p):
"""pair : ident '=' STRING
- | ident '=' ident"""
+ | ident '=' ident
+ | ident '=' NUMBER"""
p[0] = ast.PairAST(self, p[1], p[3])
def p_pair__literal(self, p):
"statement : ENQUEUE '(' var ',' type pairs ')' statements"
p[0] = ast.EnqueueStatementAST(self, p[3], p[5], p[6], p[8])
+ def p_statement__stall_and_wait(self, p):
+ "statement : STALL_AND_WAIT '(' var ',' var ')' SEMI"
+ p[0] = ast.StallAndWaitStatementAST(self, p[3], p[5])
+
+ def p_statement__wake_up_dependents(self, p):
+ "statement : WAKE_UP_DEPENDENTS '(' var ')' SEMI"
+ p[0] = ast.WakeUpDependentsStatementAST(self, p[3])
+
def p_statement__peek(self, p):
"statement : PEEK '(' var ',' type pairs ')' statements"
p[0] = ast.PeekStatementAST(self, p[3], p[5], p[6], p[8], "peek")
const std::string toString() const;
const std::string getName() const;
const MachineType getMachineType() const;
+ void stallBuffer(MessageBuffer* buf, Address addr);
+ void wakeUpBuffers(Address addr);
void initNetworkPtr(Network* net_ptr) { m_net_ptr = net_ptr; }
void print(std::ostream& out) const;
void printConfig(std::ostream& out) const;
MachineID m_machineID;
bool m_is_blocking;
std::map<Address, MessageBuffer*> m_block_map;
+typedef std::vector<MessageBuffer*> MsgVecType;
+typedef m5::hash_map< Address, MsgVecType* > WaitingBufType;
+WaitingBufType m_waiting_buffers;
+int m_max_in_port_rank;
+int m_cur_in_port_rank;
static ${ident}_ProfileDumper s_profileDumper;
${ident}_Profiler m_profiler;
static int m_num_controllers;
m_number_of_TBEs = p->number_of_TBEs;
m_is_blocking = false;
''')
+ #
+ # max_port_rank is used to size vectors and thus should be one plus the
+ # largest port rank
+ #
+ max_port_rank = self.in_ports[0].pairs["max_port_rank"] + 1
+ code(' m_max_in_port_rank = $max_port_rank;')
code.indent()
#
return MachineType_${ident};
}
+void
+$c_ident::stallBuffer(MessageBuffer* buf, Address addr)
+{
+ if (m_waiting_buffers.count(addr) == 0) {
+ MsgVecType* msgVec = new MsgVecType;
+ msgVec->resize(m_max_in_port_rank, NULL);
+ m_waiting_buffers[addr] = msgVec;
+ }
+ (*(m_waiting_buffers[addr]))[m_cur_in_port_rank] = buf;
+}
+
+void
+$c_ident::wakeUpBuffers(Address addr)
+{
+ //
+ // Wake up all possible lower rank (i.e. lower priority) buffers that could
+ // be waiting on this message.
+ //
+ for (int in_port_rank = m_cur_in_port_rank - 1;
+ in_port_rank >= 0;
+ in_port_rank--) {
+ if ((*(m_waiting_buffers[addr]))[in_port_rank] != NULL) {
+ (*(m_waiting_buffers[addr]))[in_port_rank]->reanalyzeMessages(addr);
+ }
+ }
+ delete m_waiting_buffers[addr];
+ m_waiting_buffers.erase(addr);
+}
+
void
$c_ident::blockOnQueue(Address addr, MessageBuffer* port)
{
for port in self.in_ports:
code.indent()
code('// ${ident}InPort $port')
+ if port.pairs.has_key("rank"):
+ code('m_cur_in_port_rank = ${{port.pairs["rank"]}};')
+ else:
+ code('m_cur_in_port_rank = 0;')
code('${{port["c_code_in_port"]}}')
code.dedent()
projects / gem5.git / commitdiff